+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <command.h>
#include <cpu.h>
+#include <cpu_func.h>
#include <dm.h>
#include <errno.h>
+#include <event.h>
+#include <init.h>
+#include <irq_func.h>
#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <asm/system.h>
DECLARE_GLOBAL_DATA_PTR;
-#if defined (CONFIG_SYS_NIOS_SYSID_BASE)
-extern void display_sysid (void);
-#endif /* CONFIG_SYS_NIOS_SYSID_BASE */
-
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
- printf ("CPU : Nios-II\n");
-#if !defined(CONFIG_SYS_NIOS_SYSID_BASE)
- printf ("SYSID : <unknown>\n");
-#else
- display_sysid ();
-#endif
- return (0);
+ printf("CPU: Nios-II\n");
+ return 0;
}
#endif /* CONFIG_DISPLAY_CPUINFO */
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+#ifdef CONFIG_ALTERA_SYSID
+int checkboard(void)
{
- disable_interrupts();
- /* indirect call to go beyond 256MB limitation of toolchain */
- nios2_callr(CONFIG_SYS_RESET_ADDR);
+ display_sysid();
return 0;
}
+#endif
-int dcache_status(void)
-{
- return 1;
-}
-
-void dcache_enable(void)
+int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
- flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
+ disable_interrupts();
+ /* indirect call to go beyond 256MB limitation of toolchain */
+ nios2_callr(gd->arch.reset_addr);
+ return 0;
}
-void dcache_disable(void)
+/*
+ * COPY EXCEPTION TRAMPOLINE -- copy the tramp to the
+ * exception address. Define CONFIG_ROM_STUBS to prevent
+ * the copy (e.g. exception in flash or in other
+ * softare/firmware component).
+ */
+#ifndef CONFIG_ROM_STUBS
+static void copy_exception_trampoline(void)
{
- flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
+ extern int _except_start, _except_end;
+ void *except_target = (void *)gd->arch.exception_addr;
+
+ if (&_except_start != except_target) {
+ memcpy(except_target, &_except_start,
+ &_except_end - &_except_start);
+ flush_cache(gd->arch.exception_addr,
+ &_except_end - &_except_start);
+ }
}
+#endif
-int arch_cpu_init_dm(void)
+static int nios_cpu_setup(void *ctx, struct event *event)
{
struct udevice *dev;
int ret;
- ret = uclass_first_device(UCLASS_CPU, &dev);
+ ret = uclass_first_device_err(UCLASS_CPU, &dev);
if (ret)
return ret;
- if (!dev)
- return -ENODEV;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ gd->ram_size = CFG_SYS_SDRAM_SIZE;
+#ifndef CONFIG_ROM_STUBS
+ copy_exception_trampoline();
+#endif
return 0;
}
+EVENT_SPY(EVT_DM_POST_INIT, nios_cpu_setup);
-static int altera_nios2_get_desc(struct udevice *dev, char *buf, int size)
+static int altera_nios2_get_desc(const struct udevice *dev, char *buf,
+ int size)
{
const char *cpu_name = "Nios-II";
return 0;
}
-static int altera_nios2_get_info(struct udevice *dev, struct cpu_info *info)
+static int altera_nios2_get_info(const struct udevice *dev,
+ struct cpu_info *info)
{
info->cpu_freq = gd->cpu_clk;
info->features = (1 << CPU_FEAT_L1_CACHE) |
return 0;
}
-static int altera_nios2_get_count(struct udevice *dev)
+static int altera_nios2_get_count(const struct udevice *dev)
{
return 1;
}
static int altera_nios2_probe(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
gd->cpu_clk = fdtdec_get_int(blob, node,
"clock-frequency", 0);
"altr,has-initda", 0);
gd->arch.has_mmu = fdtdec_get_int(blob, node,
"altr,has-mmu", 0);
- gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x8000000;
+ gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x80000000;
+ gd->arch.mem_region_base = gd->arch.has_mmu ? 0xc0000000 : 0x00000000;
+ gd->arch.physaddr_mask = gd->arch.has_mmu ? 0x1fffffff : 0x7fffffff;
return 0;
}
.ops = &altera_nios2_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+
+/* This is a dummy function on nios2 */
+int dram_init(void)
+{
+ return 0;
+}