+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2006-2010
* Texas Instruments, <www.ti.com>
*
* Aneesh V <aneesh@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CPU_H
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
+#include <asm/ti-common/omap_wdt.h>
+
struct gptimer {
u32 tidr; /* 0x00 r */
u8 res1[0xc];
/* enable sys_clk NO-prescale /1 */
#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
+#define WDT_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
/* Watchdog */
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
-#define BIT(x) (1 << (x))
-
#define WD_UNLOCK1 0xAAAA
#define WD_UNLOCK2 0x5555
#define CPSW_BASE 0x48484000
#define CPSW_MDIO_BASE 0x48485000
+/* gmii_sel register defines */
+#define GMII1_SEL_MII 0x0
+#define GMII1_SEL_RMII 0x1
+#define GMII1_SEL_RGMII 0x2
+#define GMII2_SEL_MII (GMII1_SEL_MII << 4)
+#define GMII2_SEL_RMII (GMII1_SEL_RMII << 4)
+#define GMII2_SEL_RGMII (GMII1_SEL_RGMII << 4)
+
+#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
+
#endif /* _CPU_H */