global: Move remaining CONFIG_SYS_* to CFG_SYS_*

[platform/kernel/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / config.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 0669222..c9c72e3 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -20,13 +20,13 @@
  * Reserve secure memory
  * To be aligned with MMU block size
  */
-#define CONFIG_SYS_MEM_RESERVE_SECURE  (66 * 1024 * 1024)      /* 66MB */
+#define CFG_SYS_MEM_RESERVE_SECURE     (66 * 1024 * 1024)      /* 66MB */
 #define SPL_TLB_SETBACK        0x1000000       /* 16MB under effective memory top */
 
 #ifdef CONFIG_ARCH_LS2080A
 #define CFG_SYS_FSL_CLUSTER_CLOCKS             { 1, 1, 4, 4 }
 #define        SRDS_MAX_LANES  8
-#define CONFIG_SYS_PAGE_SIZE           0x10000
+#define CFG_SYS_PAGE_SIZE              0x10000
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT         6
 #define L1_CACHE_BYTES         BIT(L1_CACHE_SHIFT)
@@ -37,8 +37,8 @@
 #define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
 
 /* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE        ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED          CFG_SYS_DDR_BLOCK1_SIZE
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE                      0x06000000
@@ -96,7 +96,7 @@
 
 #elif defined(CONFIG_ARCH_LS1088A)
 #define CFG_SYS_FSL_CLUSTER_CLOCKS             { 1, 1 }
-#define CONFIG_SYS_PAGE_SIZE           0x10000
+#define CFG_SYS_PAGE_SIZE              0x10000
 
 #define        SRDS_MAX_LANES  4
 #define        SRDS_BITS_PER_LANE      4
@@ -122,8 +122,8 @@
 #define SMMU_BASE                      0x05000000 /* GR0 Base */
 
 /* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE        ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED          CFG_SYS_DDR_BLOCK1_SIZE
 
 /* DCFG - GUR */
 #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
@@ -141,15 +141,15 @@
 #endif
 #define CFG_SYS_FSL_CLUSTER_CLOCKS             { 1, 1, 1, 1, 4, 4, 4, 4 }
 
-#define CONFIG_SYS_PAGE_SIZE                   0x10000
+#define CFG_SYS_PAGE_SIZE                      0x10000
 
 #define CFG_SYS_FSL_OCRAM_BASE         0x18000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE               0x00200000 /* 2M space */
 #define CFG_SYS_FSL_OCRAM_SIZE         0x00040000 /* Real size 256K */
 
 /* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE                ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED                  CFG_SYS_DDR_BLOCK1_SIZE
 
 /* Generic Interrupt Controller Definitions */
 #define GICD_BASE                              0x06000000
@@ -192,8 +192,8 @@
 #define SMMU_BASE                              0x05000000 /* GR0 Base */
 
 /* DDR */
-#define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE        ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED          CFG_SYS_DDR_BLOCK1_SIZE
 
 /* SEC */
 
@@ -212,8 +212,8 @@
 #define CFG_SYS_NUM_FMAN                       1
 #define CFG_SYS_NUM_FM1_DTSEC          7
 #define CFG_SYS_NUM_FM1_10GEC          1
-#define CONFIG_SYS_DDR_BLOCK1_SIZE             ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED                  CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE                ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED                  CFG_SYS_DDR_BLOCK1_SIZE
 
 #define QE_MURAM_SIZE          0x6000UL
 #define MAX_QE_RISC            1
@@ -251,15 +251,15 @@
 #elif defined(CONFIG_ARCH_LS1012A)
 #define GICD_BASE              0x01401000
 #define GICC_BASE              0x01402000
-#define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE        ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED          CFG_SYS_DDR_BLOCK1_SIZE
 
 #elif defined(CONFIG_ARCH_LS1046A)
 #define CFG_SYS_NUM_FMAN                       1
 #define CFG_SYS_NUM_FM1_DTSEC          8
 #define CFG_SYS_NUM_FM1_10GEC          2
-#define CONFIG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED           CONFIG_SYS_DDR_BLOCK1_SIZE
+#define CFG_SYS_DDR_BLOCK1_SIZE  ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED           CFG_SYS_DDR_BLOCK1_SIZE
 
 /* SMMU Defintions */
 #define SMMU_BASE              0x09000000