global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*

[platform/kernel/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / cpu.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index ef71e2c..bbaa91f 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1441,7 +1441,7 @@ int dram_init_banksize(void)
        }
 #endif
 
-       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+       gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
        if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
                gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
                gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
@@ -1571,7 +1571,7 @@ void update_early_mmu_table(void)
 
        if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
                mmu_change_region_attr(
-                                       CONFIG_SYS_SDRAM_BASE,
+                                       CFG_SYS_SDRAM_BASE,
                                        gd->ram_size,
                                        PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
                                        PTE_BLOCK_OUTER_SHARE           |
@@ -1579,7 +1579,7 @@ void update_early_mmu_table(void)
                                        PTE_TYPE_VALID);
        } else {
                mmu_change_region_attr(
-                                       CONFIG_SYS_SDRAM_BASE,
+                                       CFG_SYS_SDRAM_BASE,
                                        CONFIG_SYS_DDR_BLOCK1_SIZE,
                                        PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
                                        PTE_BLOCK_OUTER_SHARE           |