config ARCH_LS1012A
bool
+ select ARMV8_SET_SMPEN
select FSL_LSCH2
select SYS_FSL_DDR_BE
select SYS_FSL_MMDC
select SYS_FSL_ERRATUM_A010315
+ select ARCH_EARLY_INIT_R
+ select BOARD_EARLY_INIT_F
config ARCH_LS1043A
bool
+ select ARMV8_SET_SMPEN
select FSL_LSCH2
+ select SYS_FSL_DDR
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008850
+ select SYS_FSL_ERRATUM_A009660
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009929
+ select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
+ select SYS_FSL_HAS_DDR3
+ select SYS_FSL_HAS_DDR4
+ select ARCH_EARLY_INIT_R
+ select BOARD_EARLY_INIT_F
+ imply SCSI
+ imply CMD_PCI
config ARCH_LS1046A
bool
+ select ARMV8_SET_SMPEN
select FSL_LSCH2
+ select SYS_FSL_DDR
select SYS_FSL_DDR_BE
- select SYS_FSL_DDR4
select SYS_FSL_DDR_VER_50
+ select SYS_FSL_ERRATUM_A008336
+ select SYS_FSL_ERRATUM_A008511
+ select SYS_FSL_ERRATUM_A008850
+ select SYS_FSL_ERRATUM_A009801
+ select SYS_FSL_ERRATUM_A009803
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
+ select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
+ select ARCH_EARLY_INIT_R
+ select BOARD_EARLY_INIT_F
+ imply SCSI
config ARCH_LS2080A
bool
+ select ARMV8_SET_SMPEN
+ select ARM_ERRATA_826974
+ select ARM_ERRATA_828024
+ select ARM_ERRATA_829520
+ select ARM_ERRATA_833471
select FSL_LSCH3
- select SYS_FSL_DDR4
+ select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_HAS_SEC
+ select SYS_FSL_HAS_DDR4
select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_LE
select SYS_FSL_SRDS_2
+ select FSL_TZASC_1
+ select FSL_TZASC_2
+ select SYS_FSL_ERRATUM_A008336
+ select SYS_FSL_ERRATUM_A008511
+ select SYS_FSL_ERRATUM_A008514
+ select SYS_FSL_ERRATUM_A008585
+ select SYS_FSL_ERRATUM_A009635
+ select SYS_FSL_ERRATUM_A009663
+ select SYS_FSL_ERRATUM_A009801
+ select SYS_FSL_ERRATUM_A009803
+ select SYS_FSL_ERRATUM_A009942
+ select SYS_FSL_ERRATUM_A010165
+ select SYS_FSL_ERRATUM_A009203
+ select ARCH_EARLY_INIT_R
+ select BOARD_EARLY_INIT_F
config FSL_LSCH2
bool
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
+ select SYS_FSL_SEC_BE
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
+config FSL_MC_ENET
+ bool "Management Complex network"
+ depends on ARCH_LS2080A
+ default y
+ select RESV_RAM
+ help
+ Enable Management Complex (MC) network
+
menu "Layerscape architecture"
depends on FSL_LSCH2 || FSL_LSCH3
+config FSL_PCIE_COMPAT
+ string "PCIe compatible of Kernel DT"
+ depends on PCIE_LAYERSCAPE
+ default "fsl,ls1012a-pcie" if ARCH_LS1012A
+ default "fsl,ls1043a-pcie" if ARCH_LS1043A
+ default "fsl,ls1046a-pcie" if ARCH_LS1046A
+ default "fsl,ls2080a-pcie" if ARCH_LS2080A
+ help
+ This compatible is used to find pci controller node in Kernel DT
+ to complete fixup.
+
+config HAS_FEATURE_GIC64K_ALIGN
+ bool
+ default y if ARCH_LS1043A
+
+config HAS_FEATURE_ENHANCED_MSI
+ bool
+ default y if ARCH_LS1043A
+
menu "Layerscape PPA"
config FSL_LS_PPA
bool "FSL Layerscape PPA firmware support"
depends on !ARMV8_PSCI
- depends on ARCH_LS1043A || ARCH_LS1046A
- select FSL_PPA_ARMV8_PSCI
+ select ARMV8_SEC_FIRMWARE_SUPPORT
+ select SEC_FIRMWARE_ARMV8_PSCI
+ select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
help
The FSL Primary Protected Application (PPA) is a software component
which is loaded during boot stage, and then remains resident in RAM
and runs in the TrustZone after boot.
Say y to enable it.
-config FSL_PPA_ARMV8_PSCI
- bool "PSCI implementation in PPA firmware"
+config SPL_FSL_LS_PPA
+ bool "FSL Layerscape PPA firmware support for SPL build"
+ depends on !ARMV8_PSCI
+ select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+ select SEC_FIRMWARE_ARMV8_PSCI
+ select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
+ help
+ The FSL Primary Protected Application (PPA) is a software component
+ which is loaded during boot stage, and then remains resident in RAM
+ and runs in the TrustZone after boot. This is to load PPA during SPL
+ stage instead of the RAM version of U-Boot. Once PPA is initialized,
+ the rest of U-Boot (including RAM version) runs at EL2.
+choice
+ prompt "FSL Layerscape PPA firmware loading-media select"
depends on FSL_LS_PPA
+ default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
+ default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
+ default SYS_LS_PPA_FW_IN_XIP
+
+config SYS_LS_PPA_FW_IN_XIP
+ bool "XIP"
help
- This config enables the ARMv8 PSCI implementation in PPA firmware.
- This is a private PSCI implementation and different from those
- implemented under the common ARMv8 PSCI framework.
-endmenu
+ Say Y here if the PPA firmware locate at XIP flash, such
+ as NOR or QSPI flash.
-config SYS_FSL_MMDC
- bool
+config SYS_LS_PPA_FW_IN_MMC
+ bool "eMMC or SD Card"
+ help
+ Say Y here if the PPA firmware locate at eMMC/SD card.
+
+config SYS_LS_PPA_FW_IN_NAND
+ bool "NAND"
+ help
+ Say Y here if the PPA firmware locate at NAND flash.
+
+endchoice
+
+config SYS_LS_PPA_FW_ADDR
+ hex "Address of PPA firmware loading from"
+ depends on FSL_LS_PPA
+ default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
+ default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
+ default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+ default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
+ default 0x400000 if SYS_LS_PPA_FW_IN_MMC
+ default 0x400000 if SYS_LS_PPA_FW_IN_NAND
+
+ help
+ If the PPA firmware locate at XIP flash, such as NOR or
+ QSPI flash, this address is a directly memory-mapped.
+ If it is in a serial accessed flash, such as NAND and SD
+ card, it is a byte offset.
+
+config SYS_LS_PPA_ESBC_ADDR
+ hex "hdr address of PPA firmware loading from"
+ depends on FSL_LS_PPA && CHAIN_OF_TRUST
+ default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
+ default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
+ default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
+ default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
+ default 0x700000 if SYS_LS_PPA_FW_IN_MMC
+ default 0x700000 if SYS_LS_PPA_FW_IN_NAND
+ help
+ If the PPA header firmware locate at XIP flash, such as NOR or
+ QSPI flash, this address is a directly memory-mapped.
+ If it is in a serial accessed flash, such as NAND and SD
+ card, it is a byte offset.
+
+config LS_PPA_ESBC_HDR_SIZE
+ hex "Length of PPA ESBC header"
+ depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
+ default 0x2000
+ help
+ Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
+ NAND to memory to validate PPA image.
+
+endmenu
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
-config NUM_DDR_CONTROLLERS
- int "Maximum DDR controllers"
- default 3 if ARCH_LS2080A
- default 1
-
config SECURE_BOOT
- bool
+ bool "Secure Boot"
help
Enable Freescale Secure Boot feature
config SYS_HAS_SERDES
bool
-config SYS_FSL_DDR
- bool "Freescale DDR driver"
- help
- Select Freescale General DDR driver, shared between most Freescale
- PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
- based Layerscape SoCs (such as ls2080a).
+config FSL_TZASC_1
+ bool
-config SYS_FSL_DDR_BE
+config FSL_TZASC_2
bool
+
+endmenu
+
+menu "Layerscape clock tree configuration"
+ depends on FSL_LSCH2 || FSL_LSCH3
+
+config SYS_FSL_CLK
+ bool "Enable clock tree initialization"
+ default y
+
+config CLUSTER_CLK_FREQ
+ int "Reference clock of core cluster"
+ depends on ARCH_LS1012A
+ default 100000000
+ help
+ This number is the reference clock frequency of core PLL.
+ For most platforms, the core PLL and Platform PLL have the same
+ reference clock, but for some platforms, LS1012A for instance,
+ they are provided sepatately.
+
+config SYS_FSL_PCLK_DIV
+ int "Platform clock divider"
+ default 1 if ARCH_LS1043A
+ default 1 if ARCH_LS1046A
+ default 2
help
- Access DDR registers in big-endian.
+ This is the divider that is used to derive Platform clock from
+ Platform PLL, in another word:
+ Platform_clk = Platform_PLL_freq / this_divider
-config SYS_FSL_DDR_LE
+config SYS_FSL_DSPI_CLK_DIV
+ int "DSPI clock divider"
+ default 1 if ARCH_LS1043A
+ default 2
+ help
+ This is the divider that is used to derive DSPI clock from Platform
+ clock, in another word DSPI_clk = Platform_clk / this_divider.
+
+config SYS_FSL_DUART_CLK_DIV
+ int "DUART clock divider"
+ default 1 if ARCH_LS1043A
+ default 2
+ help
+ This is the divider that is used to derive DUART clock from Platform
+ clock, in another word DUART_clk = Platform_clk / this_divider.
+
+config SYS_FSL_I2C_CLK_DIV
+ int "I2C clock divider"
+ default 1 if ARCH_LS1043A
+ default 2
+ help
+ This is the divider that is used to derive I2C clock from Platform
+ clock, in another word I2C_clk = Platform_clk / this_divider.
+
+config SYS_FSL_IFC_CLK_DIV
+ int "IFC clock divider"
+ default 1 if ARCH_LS1043A
+ default 2
+ help
+ This is the divider that is used to derive IFC clock from Platform
+ clock, in another word IFC_clk = Platform_clk / this_divider.
+
+config SYS_FSL_LPUART_CLK_DIV
+ int "LPUART clock divider"
+ default 1 if ARCH_LS1043A
+ default 2
+ help
+ This is the divider that is used to derive LPUART clock from Platform
+ clock, in another word LPUART_clk = Platform_clk / this_divider.
+
+config SYS_FSL_SDHC_CLK_DIV
+ int "SDHC clock divider"
+ default 1 if ARCH_LS1043A
+ default 1 if ARCH_LS1012A
+ default 2
+ help
+ This is the divider that is used to derive SDHC clock from Platform
+ clock, in another word SDHC_clk = Platform_clk / this_divider.
+endmenu
+
+config RESV_RAM
bool
help
- Access DDR registers in little-endian.
+ Reserve memory from the top, tracked by gd->arch.resv_ram. This
+ reserved RAM can be used by special driver that resides in memory
+ after U-Boot exits. It's up to implementation to allocate and allow
+ access to this reserved memory. For example, the reserved RAM can
+ be at the high end of physical memory. The reserve RAM may be
+ excluded from memory bank(s) passed to OS, or marked as reserved.
-config SYS_FSL_DDR_VER
- int
- default 50 if SYS_FSL_DDR_VER_50
+config SYS_FSL_ERRATUM_A008336
+ bool
-config SYS_FSL_DDR_VER_50
+config SYS_FSL_ERRATUM_A008514
bool
-config SYS_FSL_DDRC_ARM_GEN3
+config SYS_FSL_ERRATUM_A008585
bool
-config SYS_FSL_DDRC_GEN4
+config SYS_FSL_ERRATUM_A008850
bool
-config SYS_FSL_DDR3
- bool "Freescale DDR3 controller"
- depends on !SYS_FSL_DDR4
- select SYS_FSL_DDR
- select SYS_FSL_DDRC_ARM_GEN3
- help
- Enable Freescale DDR3 controller on ARM-based SoCs.
+config SYS_FSL_ERRATUM_A009203
+ bool
-config SYS_FSL_DDR4
- bool "Freescale DDR4 controller"
- select SYS_FSL_DDR
- select SYS_FSL_DDRC_GEN4
- help
- Enable Freescale DDR4 controller.
+config SYS_FSL_ERRATUM_A009635
+ bool
-endmenu
+config SYS_FSL_ERRATUM_A009660
+ bool
+
+config SYS_FSL_ERRATUM_A009929
+ bool
+
+config SYS_MC_RSV_MEM_ALIGN
+ hex "Management Complex reserved memory alignment"
+ depends on RESV_RAM
+ default 0x20000000
+ help
+ Reserved memory needs to be aligned for MC to use. Default value
+ is 512MB.
projects / platform / kernel / u-boot.git / blobdiff