sunxi: Use CONFIG_MACH_SUN?I from Kconfig instead of CONFIG_SUN?I

[platform/kernel/u-boot.git] / arch / arm / cpu / armv7 / sunxi / clock_sun4i.c

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
index b8b16cf..a0e49d1 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
@@ -35,10 +35,14 @@ void clock_init_safe(void)
               APB0_DIV_1 << APB0_DIV_SHIFT |
               CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
               &ccm->cpu_ahb_apb0_cfg);
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
        setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
 #endif
        writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+#ifdef CONFIG_SUNXI_AHCI
+       setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
+       setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
+#endif
 }
 #endif
 
@@ -176,6 +180,17 @@ void clock_set_pll1(unsigned int hz)
 }
 #endif
 
+unsigned int clock_get_pll5p(void)
+{
+       struct sunxi_ccm_reg *const ccm =
+               (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+       uint32_t rval = readl(&ccm->pll5_cfg);
+       int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT);
+       int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1;
+       int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT);
+       return (24000000 * n * k) >> p;
+}
+
 unsigned int clock_get_pll6(void)
 {
        struct sunxi_ccm_reg *const ccm =