#include <common.h>
#include <clock_legacy.h>
#include <net.h>
+#include <asm/global_data.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/io.h>
continue;
}
+#ifdef CONFIG_DM_ETH
+ priv = dev_get_priv(dev);
+#else
priv = dev->priv;
+#endif
if (priv->flags & TSEC_SGMII)
continue;
}
}
-void ft_cpu_setup(void *blob, bd_t *bd)
+void ft_cpu_setup(void *blob, struct bd_info *bd)
{
int off;
int val;
const char *sysclk_path;
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr;
svr = in_be32(&gur->svr);
else {
ccsr_sec_t __iomem *sec;
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
#ifdef CONFIG_SYS_NS16550
do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
- "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+ "clock-frequency", CFG_SYS_NS16550_CLK, 1);
#endif
sysclk_path = fdt_get_alias(blob, "sysclk");
if (sysclk_path)
do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
- CONFIG_SYS_CLK_FREQ, 1);
+ get_board_sys_clk(), 1);
do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
- "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
+ "clock-frequency", get_board_sys_clk(), 1);
#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
#define UBOOT_HEAD_LEN 0x1000
* Since second uboot binary has a head, that space need to be
* reserved either(assuming its size is less than 0x1000).
*/
- off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
- CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
- UBOOT_HEAD_LEN);
+ off = fdt_add_mem_rsv(blob, CONFIG_TEXT_BASE - UBOOT_HEAD_LEN,
+ CONFIG_SYS_MONITOR_LEN +
+ CONFIG_SYS_SPL_MALLOC_SIZE + UBOOT_HEAD_LEN);
if (off < 0)
printf("Failed to reserve memory for SD boot deep sleep: %s\n",
fdt_strerror(off));
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
- CONFIG_SYS_IFC_ADDR);
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ CFG_SYS_IFC_ADDR);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
#else
off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
QSPI0_BASE_ADDR);
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
DSPI1_BASE_ADDR);
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
#endif
}