include/configs/ls2085a_common.h

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS2_COMMON_H
   8 #define __LS2_COMMON_H
   9
  10 #define CONFIG_SYS_GENERIC_BOARD
  11
  12 #define CONFIG_REMAKE_ELF
  13 #define CONFIG_FSL_LSCH3
  14 #define CONFIG_LS2085A
  15 #define CONFIG_GICV3
  16
  17 /* Link Definitions */
  18 #define CONFIG_SYS_TEXT_BASE            0x30000000
  19
  20 #define CONFIG_SYS_NO_FLASH
  21
  22 #define CONFIG_SUPPORT_RAW_INITRD
  23
  24 #define CONFIG_SKIP_LOWLEVEL_INIT
  25 #define CONFIG_BOARD_EARLY_INIT_F       1
  26
  27 #define CONFIG_IDENT_STRING             " LS2085A-EMU"
  28 #define CONFIG_BOOTP_VCI_STRING         "U-boot.LS2085A-EMU"
  29
  30 /* Flat Device Tree Definitions */
  31 #define CONFIG_OF_LIBFDT
  32 #define CONFIG_OF_BOARD_SETUP
  33
  34 /* new uImage format support */
  35 #define CONFIG_FIT
  36 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
  37
  38 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  39 #ifndef CONFIG_SYS_FSL_DDR4
  40 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
  41 #define CONFIG_SYS_DDR_RAW_TIMING
  42 #endif
  43 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  44 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  45
  46 #define CONFIG_SYS_FSL_DDR_INTLV_256B   /* force 256 byte interleaving */
  47
  48 /* SMP Definitions */
  49 #define CPU_RELEASE_ADDR                CONFIG_SYS_INIT_SP_ADDR
  50
  51 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  52 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  53 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  54 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x8080000000ULL
  55
  56 /* Generic Timer Definitions */
  57 #define COUNTER_FREQUENCY               12000000        /* 12MHz */
  58
  59 /* Size of malloc() pool */
  60 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128 * 1024)
  61
  62 /* I2C */
  63 #define CONFIG_CMD_I2C
  64 #define CONFIG_SYS_I2C
  65 #define CONFIG_SYS_I2C_MXC
  66 #define CONFIG_SYS_MXC_I2C1_SPEED       40000000
  67 #define CONFIG_SYS_MXC_I2C2_SPEED       40000000
  68
  69 /* Serial Port */
  70 #define CONFIG_CONS_INDEX       2
  71 #define CONFIG_SYS_NS16550
  72 #define CONFIG_SYS_NS16550_SERIAL
  73 #define CONFIG_SYS_NS16550_REG_SIZE     1
  74 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
  75
  76 #define CONFIG_BAUDRATE                 115200
  77 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  78
  79 /* IFC */
  80 #define CONFIG_FSL_IFC
  81 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  82 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
  83 /*
  84  * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
  85  * address 0. But this region is limited to 256MB. To accommodate bigger NOR
  86  * flash and other devices, we will map CS0 to 0x580000000 after relocation.
  87  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  88  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  89  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  90  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
  91  */
  92 #define CONFIG_SYS_FLASH_BASE                   0x580000000ULL
  93 #define CONFIG_SYS_FLASH_BASE_PHYS              0x80000000
  94 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
  95
  96 /*
  97  * NOR Flash Timing Params
  98  */
  99 #define CONFIG_SYS_NOR0_CSPR                                    \
 100         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
 101         CSPR_PORT_SIZE_16                                       | \
 102         CSPR_MSEL_NOR                                           | \
 103         CSPR_V)
 104 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
 105         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
 106         CSPR_PORT_SIZE_16                                       | \
 107         CSPR_MSEL_NOR                                           | \
 108         CSPR_V)
 109 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
 110 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
 111                                 FTIM0_NOR_TEADC(0x1) | \
 112                                 FTIM0_NOR_TEAHC(0x1))
 113 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
 114                                 FTIM1_NOR_TRAD_NOR(0x1))
 115 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
 116                                 FTIM2_NOR_TCH(0x0) | \
 117                                 FTIM2_NOR_TWP(0x1))
 118 #define CONFIG_SYS_NOR_FTIM3    0x04000000
 119 #define CONFIG_SYS_IFC_CCR      0x01000000
 120
 121 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 122 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 123 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 124 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 125 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 126 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 127 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 128 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 129 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 130
 131 /* MC firmware */
 132 #define CONFIG_FSL_MC_ENET
 133 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE    (512UL * 1024 * 1024)
 134 #define CONFIG_SYS_LS_MC_FW_IN_NOR
 135 #define CONFIG_SYS_LS_MC_FW_ADDR        0x580200000ULL
 136 /* TODO Actual FW length needs to be determined at runtime from FW header */
 137 #define CONFIG_SYS_LS_MC_FW_LENGTH      (4U * 1024 * 1024)
 138 #define CONFIG_SYS_LS_MC_DPL_IN_NOR
 139 #define CONFIG_SYS_LS_MC_DPL_ADDR       0x5806C0000ULL
 140 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
 141 #define CONFIG_SYS_LS_MC_DPL_LENGTH     4096
 142 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0xe00000
 143
 144 /* Carve the MC private DRAM block from the end of DRAM */
 145 #ifdef CONFIG_FSL_MC_ENET
 146 #define CONFIG_SYS_MEM_TOP_HIDE         mc_get_dram_block_size()
 147 #endif
 148
 149 /* Command line configuration */
 150 #define CONFIG_CMD_CACHE
 151 #define CONFIG_CMD_BDI
 152 #define CONFIG_CMD_DHCP
 153 #define CONFIG_CMD_ENV
 154 #define CONFIG_CMD_FLASH
 155 #define CONFIG_CMD_IMI
 156 #define CONFIG_CMD_MEMORY
 157 #define CONFIG_CMD_MII
 158 #define CONFIG_CMD_NET
 159 #define CONFIG_CMD_PING
 160 #define CONFIG_CMD_SAVEENV
 161 #define CONFIG_CMD_RUN
 162 #define CONFIG_CMD_BOOTD
 163 #define CONFIG_CMD_ECHO
 164 #define CONFIG_CMD_SOURCE
 165 #define CONFIG_CMD_FAT
 166 #define CONFIG_DOS_PARTITION
 167
 168 /* Miscellaneous configurable options */
 169 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 170
 171 /* Physical Memory Map */
 172 /* fixme: these need to be checked against the board */
 173 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 174 #define CONFIG_SYS_CLK_FREQ     133333333
 175
 176
 177 #define CONFIG_NR_DRAM_BANKS            2
 178
 179 #define CONFIG_SYS_HZ                   1000
 180
 181 #define CONFIG_HWCONFIG
 182 #define HWCONFIG_BUFFER_SIZE            128
 183
 184 #define CONFIG_DISPLAY_CPUINFO
 185
 186 /* Initial environment variables */
 187 #define CONFIG_EXTRA_ENV_SETTINGS               \
 188         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 189         "loadaddr=0x80100000\0"                 \
 190         "kernel_addr=0x100000\0"                \
 191         "ramdisk_addr=0x800000\0"               \
 192         "ramdisk_size=0x2000000\0"              \
 193         "fdt_high=0xffffffffffffffff\0"         \
 194         "initrd_high=0xffffffffffffffff\0"      \
 195         "kernel_start=0x581200000\0"            \
 196         "kernel_load=0x806f0000\0"              \
 197         "kernel_size=0x1000000\0"               \
 198         "console=ttyAMA0,38400n8\0"
 199
 200 #define CONFIG_BOOTARGS                 "console=ttyS1,115200 root=/dev/ram0 " \
 201                                         "earlyprintk=uart8250-8bit,0x21c0600"
 202 #define CONFIG_BOOTCOMMAND              "cp.b $kernel_start $kernel_load "     \
 203                                         "$kernel_size && bootm $kernel_load"
 204 #define CONFIG_BOOTDELAY                1
 205
 206 /* Store environment at top of flash */
 207 #define CONFIG_ENV_IS_NOWHERE           1
 208 #define CONFIG_ENV_SIZE                 0x1000
 209
 210 /* Monitor Command Prompt */
 211 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 212 #define CONFIG_SYS_PROMPT               "> "
 213 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 214                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 215 #define CONFIG_SYS_HUSH_PARSER
 216 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 217 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 218 #define CONFIG_SYS_LONGHELP
 219 #define CONFIG_CMDLINE_EDITING          1
 220 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 221
 222 #ifndef __ASSEMBLY__
 223 unsigned long mc_get_dram_block_size(void);
 224 #endif
 225
 226 #endif /* __LS2_COMMON_H */