Upstream version 9.38.198.0

[platform/framework/web/crosswalk.git] / src / v8 / src / base / atomicops_internals_x86_gcc.h

diff --git a/src/v8/src/base/atomicops_internals_x86_gcc.h b/src/v8/src/base/atomicops_internals_x86_gcc.h
index 00b6448..ec87c42 100644 (file)
--- a/src/v8/src/base/atomicops_internals_x86_gcc.h
+++ b/src/v8/src/base/atomicops_internals_x86_gcc.h
@@ -17,7 +17,9 @@ namespace base {
 struct AtomicOps_x86CPUFeatureStruct {
   bool has_amd_lock_mb_bug;  // Processor has AMD memory-barrier bug; do lfence
                              // after acquire compare-and-swap.
+#if !defined(__SSE2__)
   bool has_sse2;             // Processor has SSE2.
+#endif
 };
 extern struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures;
 
@@ -92,7 +94,7 @@ inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
   *ptr = value;
 }
 
-#if defined(__x86_64__)
+#if defined(__x86_64__) || defined(__SSE2__)
 
 // 64-bit implementations of memory barrier can be simpler, because it
 // "mfence" is guaranteed to exist.