#include "src/v8.h"
-#include "src/globals.h"
-#include "src/utils.h"
#include "src/allocation.h"
-#include "src/assembler.h"
#include "src/arm64/assembler-arm64.h"
#include "src/arm64/decoder-arm64.h"
#include "src/arm64/disasm-arm64.h"
#include "src/arm64/instrument-arm64.h"
+#include "src/assembler.h"
+#include "src/globals.h"
+#include "src/utils.h"
#define REGISTER_CODE_LIST(R) \
R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \
public:
template<typename T>
explicit CallArgument(T argument) {
- ASSERT(sizeof(argument) <= sizeof(bits_));
+ bits_ = 0;
+ DCHECK(sizeof(argument) <= sizeof(bits_));
memcpy(&bits_, &argument, sizeof(argument));
type_ = X_ARG;
}
explicit CallArgument(double argument) {
- ASSERT(sizeof(argument) == sizeof(bits_));
+ DCHECK(sizeof(argument) == sizeof(bits_));
memcpy(&bits_, &argument, sizeof(argument));
type_ = D_ARG;
}
UNIMPLEMENTED();
// Make the D register a NaN to try to trap errors if the callee expects a
// double. If it expects a float, the callee should ignore the top word.
- ASSERT(sizeof(kFP64SignallingNaN) == sizeof(bits_));
+ DCHECK(sizeof(kFP64SignallingNaN) == sizeof(bits_));
memcpy(&bits_, &kFP64SignallingNaN, sizeof(kFP64SignallingNaN));
// Write the float payload to the S register.
- ASSERT(sizeof(argument) <= sizeof(bits_));
+ DCHECK(sizeof(argument) <= sizeof(bits_));
memcpy(&bits_, &argument, sizeof(argument));
type_ = D_ARG;
}
// Simulation helpers.
template <typename T>
void set_pc(T new_pc) {
- ASSERT(sizeof(T) == sizeof(pc_));
+ DCHECK(sizeof(T) == sizeof(pc_));
memcpy(&pc_, &new_pc, sizeof(T));
pc_modified_ = true;
}
}
void ExecuteInstruction() {
- ASSERT(IsAligned(reinterpret_cast<uintptr_t>(pc_), kInstructionSize));
+ DCHECK(IsAligned(reinterpret_cast<uintptr_t>(pc_), kInstructionSize));
CheckBreakNext();
Decode(pc_);
LogProcessorState();
//
template<typename T>
T reg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
- ASSERT(code < kNumberOfRegisters);
+ DCHECK(code < kNumberOfRegisters);
if (IsZeroRegister(code, r31mode)) {
return 0;
}
template<typename T>
void set_reg(unsigned code, T value,
Reg31Mode r31mode = Reg31IsZeroRegister) {
- ASSERT(code < kNumberOfRegisters);
+ DCHECK(code < kNumberOfRegisters);
if (!IsZeroRegister(code, r31mode))
registers_[code].Set(value);
}
// Commonly-used special cases.
template<typename T>
void set_lr(T value) {
- ASSERT(sizeof(T) == kPointerSize);
+ DCHECK(sizeof(T) == kPointerSize);
set_reg(kLinkRegCode, value);
}
template<typename T>
void set_sp(T value) {
- ASSERT(sizeof(T) == kPointerSize);
+ DCHECK(sizeof(T) == kPointerSize);
set_reg(31, value, Reg31IsStackPointer);
}
template<typename T>
T fpreg(unsigned code) const {
- ASSERT(code < kNumberOfRegisters);
+ DCHECK(code < kNumberOfRegisters);
return fpregisters_[code].Get<T>();
}
// This behaviour matches AArch64 register writes.
template<typename T>
void set_fpreg(unsigned code, T value) {
- ASSERT((sizeof(value) == kDRegSize) || (sizeof(value) == kSRegSize));
- ASSERT(code < kNumberOfFPRegisters);
+ DCHECK((sizeof(value) == kDRegSize) || (sizeof(value) == kSRegSize));
+ DCHECK(code < kNumberOfFPRegisters);
fpregisters_[code].Set(value);
}
// functions, or to save and restore it when entering and leaving generated
// code.
void AssertSupportedFPCR() {
- ASSERT(fpcr().FZ() == 0); // No flush-to-zero support.
- ASSERT(fpcr().RMode() == FPTieEven); // Ties-to-even rounding only.
+ DCHECK(fpcr().FZ() == 0); // No flush-to-zero support.
+ DCHECK(fpcr().RMode() == FPTieEven); // Ties-to-even rounding only.
// The simulator does not support half-precision operations so fpcr().AHP()
// is irrelevant, and is not checked here.