#include "src/cpu-profiler.h"
#include "src/debug.h"
#include "src/isolate-inl.h"
-#include "src/runtime.h"
+#include "src/runtime/runtime.h"
namespace v8 {
namespace internal {
add(fp, sp, Operand(StandardFrameConstants::kFixedFrameSizeFromFp));
if (FLAG_enable_ool_constant_pool) {
LoadConstantPoolPointerRegister();
- set_constant_pool_available(true);
+ set_ool_constant_pool_available(true);
}
}
}
if (FLAG_enable_ool_constant_pool) {
LoadConstantPoolPointerRegister();
- set_constant_pool_available(true);
+ set_ool_constant_pool_available(true);
}
}
void MacroAssembler::EnterFrame(StackFrame::Type type,
- bool load_constant_pool) {
+ bool load_constant_pool_pointer_reg) {
// r0-r3: preserved
PushFixedFrame();
- if (FLAG_enable_ool_constant_pool && load_constant_pool) {
+ if (FLAG_enable_ool_constant_pool && load_constant_pool_pointer_reg) {
LoadConstantPoolPointerRegister();
}
mov(ip, Operand(Smi::FromInt(type)));
}
-// Allocates a simd128 object or jumps to the need_gc label if the young space
-// is full and a scavenge is needed.
-void MacroAssembler::AllocateSIMDHeapObject(int size,
- Register result,
- Register scratch1,
- Register scratch2,
- Register map,
- Label* gc_required,
- TaggingMode tagging_mode) {
- UNREACHABLE(); // NOTIMPLEMENTED
-}
-
-
// Copies a fixed number of fields of heap objects from src to dst.
void MacroAssembler::CopyFields(Register dst,
Register src,
DCHECK(!dividend.is(ip));
DCHECK(!result.is(ip));
base::MagicNumbersForDivision<uint32_t> mag =
- base::SignedDivisionByConstant(static_cast<uint32_t>(divisor));
+ base::SignedDivisionByConstant(bit_cast<uint32_t>(divisor));
mov(ip, Operand(mag.multiplier));
- smull(ip, result, dividend, ip);
- bool neg = (mag.multiplier & (static_cast<uint32_t>(1) << 31)) != 0;
+ bool neg = (mag.multiplier & (1U << 31)) != 0;
if (divisor > 0 && neg) {
- add(result, result, Operand(dividend));
- }
- if (divisor < 0 && !neg && mag.multiplier > 0) {
- sub(result, result, Operand(dividend));
+ smmla(result, dividend, ip, dividend);
+ } else {
+ smmul(result, dividend, ip);
+ if (divisor < 0 && !neg && mag.multiplier > 0) {
+ sub(result, result, Operand(dividend));
+ }
}
if (mag.shift > 0) mov(result, Operand(result, ASR, mag.shift));
add(result, result, Operand(dividend, LSR, 31));
}
-
-} } // namespace v8::internal
+} // namespace internal
+} // namespace v8
#endif // V8_TARGET_ARCH_ARM