From: Yoshihito Ogawa Date: Fri, 21 Nov 2014 02:55:22 +0000 (+0900) Subject: drm: rcar-du: Fix the DU register setting for Hsync X-Git-Tag: submit/tizen_ivi/20150108.095140~2 X-Git-Url: http://review.tizen.org/git/?p=platform%2Fadaptation%2Frenesas_rcar%2Frenesas_kernel.git;a=commitdiff_plain;h=6dedd8628e97910887d1fc6f40f8c3d61d3c964a drm: rcar-du: Fix the DU register setting for Hsync Change-Id: Ic5b2b7d00eca9e121d6f9ffa0f3d1bf4c221c303 Signed-off-by: Damian Hobson-Garcia --- diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 4b4b4a7..59a7586 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -106,7 +106,7 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL) | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL) | DSMR_DIPM_DE; - rcar_du_crtc_write(rcrtc, DSMR, value); + rcar_du_crtc_write(rcrtc, DSMR, value | DSMR_CSPM); /* Display timings */ rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);