drm/i915: merge VLV eDP and DP AUX clock divider calculation
authorImre Deak <imre.deak@intel.com>
Thu, 16 May 2013 11:40:35 +0000 (14:40 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 31 May 2013 18:54:00 +0000 (20:54 +0200)
commita62d0834dee83994e41fcd0e5b7f10aad3d80de0
tree3bd1930537c7d8afb5335f4fab878403c738e3bc
parent982a38667dd9f175f8dd8a78651426ae6baac463
drm/i915: merge VLV eDP and DP AUX clock divider calculation

On ValleyView for both eDP and DP the AUX input clock is 200MHz, so we
can calculate for both the clock divider for the 2MHz target rate at the
same place. Afterwards we can also replace the is_cpu_edp() check with a
check for port A.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_dp.c