From: Brendan Le Foll <brendan.le.foll@intel.com>
Date: Tue, 28 Jul 2015 08:32:12 +0000 (+0100)
Subject: galileorevh.md: Add instructions for using uart1 on gen2
X-Git-Tag: v0.7.4~31
X-Git-Url: http://review.tizen.org/git/?p=contrib%2Fmraa.git;a=commitdiff_plain;h=9e67788eb0c414251acdfb613a30e4145a618575

galileorevh.md: Add instructions for using uart1 on gen2

Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
---

diff --git a/docs/galileorevh.md b/docs/galileorevh.md
index 42063f1..4afe5fa 100644
--- a/docs/galileorevh.md
+++ b/docs/galileorevh.md
@@ -17,3 +17,40 @@ The Gen 2 board has the following limitations in libmraa:
   accuracy of 10bits.
 - AIO pins are treated as 0-5 in mraa_aio_init() but as 14-19 for everything
   else. Therefore use mraa_gpio_init(14) to use A0 as a Gpio
+
+Uart 1 on gen2
+--------------
+
+Uart 1 is connected to the FTDI header and the linux console. It's also
+possible to use it from A2(Rx)/A3(Tx). However mraa does not support this
+directly so you need to enable the muxing manually. Here is an example of how
+this is done, this was tested using an FTDI 3.3V TTL cable:
+
+$ systemctl stop serial-getty@ttyS1.service
+
+$ python
+>>> # Configure the Muxes for Uart1 on Aio2/3
+>>> import mraa as m
+>>> p77 = m.Gpio(77, False, True)
+>>> p76 = m.Gpio(76, False, True)
+>>> p16 = m.Gpio(16, False, True)
+>>> p17 = m.Gpio(17, False, True)
+>>> p77.write(1)
+>>> p76.write(1)
+>>> p16.dir(m.DIR_OUT)
+>>> p16.write(0)
+>>> p17.dir(m.DIR_OUT)
+>>> p17.write(1)
+
+>>> # For Rx to work correctly switch the level shifter
+>>> p34 = m.Gpio(34, False, True)
+>>> p34.dir(m.DIR_OUT)
+>>> p34.write(1)
+
+>>> # Use the uart
+>>> x = m.Uart(1)
+>>> x.setBaudRate(115200)
+>>> x.writeStr('hello')
+>>> x.read(5)
+bytearray(b'dsds\n')
+