ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs
[platform/kernel/u-boot.git] / drivers / ddr /
drwxr-xr-x   ..
-rw-r--r-- 36 Kconfig
drwxr-xr-x - altera
drwxr-xr-x - fsl
drwxr-xr-x - marvell
drwxr-xr-x - microchip