The SR (Submit Request) has been accepted to Tizen-Unified-RISCV project.
- Tizen version:tizen
- Git project: platform/adaptation/rpi/pass-hal-rpi
- Git commit: d92be83ac7bfb209fad0e77228a75837c6a6e82c
- URL:https://quickbuild.tizen.org/build/381444