projects / platform / upstream / mesa.git / search
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
spec: gbm enabled by default
2023-02-08 Sagar Ghugeintel/fs: Always stall between the fences on Gen11+
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2022-08-05 Sagar Ghugeiris: Handle new untyped dataport cache flush PIPE_CONTROL...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2022-08-05 Sagar Ghugeanv: Handle bits to flush data-port's Untyped L1 data...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2022-08-05 Sagar Ghugeiris: Specify Untyped L1 cache policy for stateless...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2022-08-05 Sagar Ghugeanv: Specify Untyped L1 cache policy for stateless...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2022-08-05 Sagar Ghugeintel/isl: Setting L1 caching policy to Write-back...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2022-06-01 Sagar Ghugeanv: Disable storage image compression for possible...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2022-03-17 Sagar Ghugeintel/fs: Add Wa_14014435656
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2022-03-17 Sagar Ghugeintel/fs: Add Wa_22013689345
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2022-01-24 Sagar Ghugeintel/genxml: Add Un-Typed Data-Port Cache Flush field...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2022-01-24 Sagar Ghugeintel/genxml: Add L1 Cache Control bit field
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-12-16 Sagar Ghugeanv, iris: Implement Wa_14014890652 for DG2
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-11-23 Sagar Ghugeintel/compiler: Prepare disasm for 16-bit sampler params
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-11-23 Sagar Ghugeintel/fs: Define and set correct sampler simd mode
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-11-23 Sagar Ghugeintel/compiler: Add helper to support half float payload...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-11-23 Sagar Ghugeintel/compiler: Fix instruction size written calculation
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-11-23 Sagar Ghugeintel/compiler: Don't hardcode padding source type...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-11-23 Sagar Ghugeintel/compiler: Set correct return format for brw_SAMPLE
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-10-27 Sagar Ghugeanv: Enable CCS for storage image formats
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-10-27 Sagar Ghugeanv: Pass correct aux usage while filling out surface...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-10-26 Sagar Ghugeiris: Drop hint if primitive id is required or not
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-10-26 Sagar Ghugeanv: Drop hint if primitive id is required or not
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-10-26 Sagar Ghugeintel/compiler: Track primitive id in domain/evaluation...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-10-26 Sagar Ghugeintel/genxml: Add new Primitive ID Not Required bit...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-10-21 Sagar Ghugeintel/compiler: Set correct cache policy for A64 byte...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-10-08 Sagar Ghugeisl: Use software programmable render compression format...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-10-08 Sagar Ghugeisl: Add helper to return render compression format...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-10-08 Sagar Ghugeintel/genxml: Add new bit fields Render Compression...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-10-01 Sagar Ghugeiris: Enable atomic operations on compressed surfaces
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-09-09 Sagar Ghugeanv: No need to lower to A64 messages for 64-bit atomics
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-09-09 Sagar Ghugeintel/compiler: Add support to handle 64-bit atomics...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-09-09 Sagar Ghugeanv: Advertise support for shaderBufferFloat64AtomicMinMax
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-09-09 Sagar Ghugeintel/compiler: Add 64-bit A64 float logical opcode...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-08-18 Sagar Ghugeanv: Fix VK_EXT_memory_budget to consider VRAM if available
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-08-02 Sagar Ghugegenxml/gen125: Update debug register fields according...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-08-02 Sagar Ghugegenxml/gen12: Update debug register fields according...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-07-22 Sagar Ghugeintel/compiler: Handle ternary add in lower_simd_width
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-07-22 Sagar Ghugeintel/compiler: Fix missing break in switch
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-07-16 Sagar Ghugeintel/compiler: Enable has_iadd3 option on XeHP
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-07-16 Sagar Ghugenir: Add optimizations for iadd3
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-07-16 Sagar Ghugeintel/compiler: Allow ternary add to promote source...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-07-16 Sagar Ghugeintel/compiler: Make decision based on source type...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-07-16 Sagar Ghugeintel/compiler: Add support for ternary add instruction...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-07-16 Sagar Ghugenir: Add new opcode for ternary addition
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-06-30 Sagar Ghugeintel/fs: Lower varying pull constant load message...
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-06-30 Sagar Ghugeintel/fs: Lower A64 atomic messages to LSC dataport
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-06-30 Sagar Ghugeintel/fs: Lower A64 byte scattered r/w messages to...
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-06-30 Sagar Ghugeintel/fs: Lower Byte scattered r/w messages to LSC...
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-06-30 Sagar Ghugeintel/fs: Lower untyped float atomic messages to LSC...
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-06-30 Sagar Ghugeintel/disasm: Disassemble LSC message extended descriptors
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-06-30 Sagar Ghugeintel/disasm: Disassmeble LSC messages
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-06-30 Sagar Ghugeintel/compiler: Add helpers for LSC message descriptors
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-06-30 Sagar Ghugeintel/compiler: Add support for LSC fence operations
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-06-30 Sagar Ghugeintel/compiler: Define new LSC data port encodings
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-06-24 Sagar Ghugeanv: Allocate scratch and workaround BO in local memory
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-06-24 Sagar Ghugeanv: Allocate BO in appropriate region
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-06-24 Sagar Ghugeanv: Wrapper around I915_GEM_CREATE_EXT_MEMORY_REGIONS
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-06-24 Sagar Ghugeanv: Query memory region info
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-04-14 Sagar Ghugeanv: Avoid corrupting indirect depth clear values
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-04-14 Sagar Ghugeanv: Set correct fast clear value for depth during...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-03-15 Sagar Ghugeanv: Set correct binding table entry count
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-03-10 Sagar Ghugeintel/blorp: Fix condition to figure out aux_address
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-03-10 Sagar GhugeRevert "Revert "blorp/gen12: Don't use aux address...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-03-08 Sagar Ghugeanv: Add anv_memregion structure
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-03-08 Sagar Ghugeintel/mi_builder: Added support for command streamer...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-01-26 Sagar Ghugeanv: Skip CCS ambiguate which preceed fast-clears
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2021-01-25 Sagar Ghugeanv: Invalidate the correct AUX-TT entry
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-10-22 Sagar Ghugeanv: Enable stencil buffer compression on Gen12+
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-10-22 Sagar Ghugeanv: Pass correct stencil aux usage during MSAA resolve
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-10-22 Sagar Ghugeanv: Return optimal aux state for stencil buffer compression
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-10-22 Sagar Ghugeanv: Don't track clear bo for stencil buffer compression
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-10-22 Sagar Ghugeanv: Get aux usage from plane while clearing stencil...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-10-22 Sagar Ghugeanv: Set stencil_aux_usage flag
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-10-22 Sagar Ghugeanv: Handle compressed stencil buffer transition on...
anv_layout_to_aux_usage (Sagar Ghuge)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-10-22 Sagar Ghugeanv: Return number of layers/levels attached to anv_image
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-10-06 Sagar Ghugeanv: Add driconf option to disable compression for...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-10-06 Sagar Ghugeanv: Factor out dri option initialization code in separate...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-10-01 Sagar Ghugeintel/blorp: Conditionally clear full surface depth...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-09-01 Sagar Ghugeintel/isl: Drop unnecessary check on 16bpp depth format
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-06-17 Sagar Ghugeintel/compiler: Remove unnecessary optimization for MUL
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-06-16 Sagar Ghugeintel/compiler: Optimize integer add with 0 into mov
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-05-15 Sagar Ghugeiris: Use modfiy disables for 3DSTATE_WM_DEPTH_STENCIL...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-03-23 Sagar Ghugeiris: Set patch count threshold in 3DSTATE_HS
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-03-23 Sagar Ghugeanv: Set patch count threshold in 3DSTATE_HS
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-03-23 Sagar Ghugeintel/compiler: Track patch count threshold
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-03-23 Sagar Ghugeintel/genxml: Add patch count threshold field on gen12
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-02-25 Sagar Ghugeintel/tools: Allow i965_disasm to disassemble c_literal...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-02-25 Sagar Ghugeintel/tools: Print c_literals 4 byte wide
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-02-25 Sagar Ghugeintel/tools: Add test for state register as source
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-02-25 Sagar Ghugeintel/tools: Add test for address register as source
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-02-25 Sagar Ghugeintel/tools: Set correct address register file and...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-02-25 Sagar Ghugeintel/tools: Handle STATE_REG in typed source operand
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-02-25 Sagar Ghugeintel/tools: Handle illegal instruction
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-02-13 Sagar Ghugeintel/isl: Switch to R8_UNORM format for compatiblity
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-02-13 Sagar Ghugeintel/isl: Move get_format_encoding function to isl
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2020-01-27 Sagar Ghugeintel/compiler: Clear accumulator register before EOT
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2019-10-29 Sagar Ghugeintel/isl: Allow stencil buffer to support compression...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2019-10-29 Sagar Ghugeiris: Resolve stencil resource prior to copy or used...
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2019-10-29 Sagar Ghugeiris: Prepare resources before stencil blit operation
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
2019-10-29 Sagar Ghugeiris: Prepare depth resource if clear_depth enable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
 commit | commitdiff | tree
next
Domain: Graphics System / GL;