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Merge drm/drm-next into drm-intel-next
2022-08-02 Anusha Srivatsadrm/i915/dg2: Add support for DC5 state
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2022-07-27 Anusha Srivatsadrm/i915: Pass drm_i915_private struct instead of gt...
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2022-07-27 Anusha Srivatsadrm/i915/display: Cleanup intel_phy_is_combo()
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2022-05-16 Anusha Srivatsadrm/i915/dmc: Add MMIO range restrictions
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2022-05-13 Anusha Srivatsadrm/i915/dmc: Add MMIO range restrictions
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2022-05-11 Anusha Srivatsadrm/i915/dmc: Load DMC on DG2
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2022-01-26 Anusha Srivatsadrm/i915/rpl-s: Add stepping info
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-12-08 Anusha Srivatsadrm/i915/rpl-s: Enable guc submission by default
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-12-08 Anusha Srivatsadrm/i915/rpl-s: Add PCH Support for Raptor Lake S
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-12-08 Anusha Srivatsadrm/i915/rpl-s: Add PCI IDS for Raptor Lake S
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-11-01 Anusha Srivatsai915/display/dmc: Add Support for PipeC and PipeD DMC
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-09-17 Anusha Srivatsadrm/i915/dmc: Update to DMC v2.12
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-07-22 Anusha Srivatsadrm/i915/firmware: Update to DMC v2.03 on RKL
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-07-22 Anusha Srivatsadrm/i915/firmware: Update to DMC v2.12 on TGL
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-07-22 Anusha Srivatsadrm/i915/dmc: Change intel_get_stepping_info()
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-07-22 Anusha Srivatsadrm/i915/step: Add macro magic for handling steps
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-07-15 Anusha Srivatsadrm/i915/step: s/<platform>_revid_tbl/<platform>_revids
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-06-21 Anusha Srivatsadrm/i915/adl_p: Load DMC
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-06-21 Anusha Srivatsadrm/i915/adl_p: Pipe B DMC Support
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-06-21 Anusha Srivatsadrm/i915/xelpd: Pipe A DMC plugging
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-06-21 Anusha Srivatsadrm/i915/dmc: Introduce DMC_FW_MAIN
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-06-03 Anusha Srivatsadrm/i915/dmc: Move struct intel_dmc to intel_dmc.h
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-06-03 Anusha Srivatsadrm/i915/dmc: Add intel_dmc_has_payload() helper
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-06-03 Anusha Srivatsadrm/i915/dmc: s/DRM_ERROR/drm_err
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-05-24 Anusha Srivatsadrm/i915/gvt: Add missing macro name changes
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-05-20 Anusha Srivatsadrm/i915/adl_p: Update memory bandwidth parameters
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-05-20 Anusha Srivatsadrm/i915/adlp: Add PIPE_MISC2 programming
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-05-20 Anusha Srivatsadrm/i915/adl_p: Add PLL Support
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-05-20 Anusha Srivatsadrm/i915/adl_p: Setup ports/phys
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-05-20 Anusha Srivatsadrm/i915/dmc: s/intel_csr.c/intel_dmc.c and s/intel_csr...
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-05-20 Anusha Srivatsadrm/i915/dmc: Rename functions names having "csr"
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-05-20 Anusha Srivatsadrm/i915/dmc: Rename macro names containing csr
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-05-20 Anusha Srivatsadrm/i915/dmc: s/HAS_CSR/HAS_DMC
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-05-20 Anusha Srivatsadrm/i915/dmc: s/intel_csr/intel_dmc
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-05-15 Anusha Srivatsadrm/i915/adl_p: Add cdclk support for ADL-P
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-04-27 Anusha Srivatsadrm/i915/lmem: Bypass aperture when lmem is available
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-02-01 Anusha Srivatsadrm/i915/adl_s: Load DMC
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-01-26 Anusha Srivatsadrm/i915/adl_s: Add PHYs for Alderlake S
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-01-26 Anusha Srivatsadrm/i915/adl_s: Add Interrupt Support
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2021-01-26 Anusha Srivatsadrm/i915/adl_s: Add PCH support
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2020-11-04 Anusha Srivatsadrm/i915/ehl: Remove invalid PCI ID
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2020-09-15 Anusha Srivatsadrm/i915/pll: Centralize PLL_ENABLE register lookup
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2020-07-14 Anusha Srivatsadrm/i915/dg1: Remove SHPD_FILTER_CNT register programming
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2020-03-02 Anusha Srivatsadrm/i915/tgl: Extend Wa_1606931601 for all steppings
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2019-09-27 Anusha Srivatsadrm/i915/dmc: Update ICL DMC version to v1.09
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2019-09-20 Anusha Srivatsadrm/i915/uc: Update HuC firmware naming convention...
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2019-08-22 Anusha Srivatsadrm/dp/dsc: Add Support for all BPCs supported by TGL
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2019-08-15 Anusha Srivatsadrm/i915/cml: Add Missing PCI IDs
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2019-08-06 Anusha Srivatsadrm/i915/dmc: Load DMC on TGL
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2019-07-12 Anusha Srivatsadrm/i915: Add modular FIA
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2019-03-22 Anusha Srivatsadrm/i915/ehl: Add Support for DMC on EHL
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2019-03-19 Anusha Srivatsadrm/i915/cml: Introduce Comet Lake PCH
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2019-03-19 Anusha Srivatsadrm/i915/cml: Add CML PCI IDS
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-12-17 Anusha Srivatsadrm/i915/huc: Update the HuC version for BXT
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-11-29 Anusha Srivatsadrm/i915/fec: Disable FEC state.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-11-29 Anusha Srivatsai915/dp/fec: Configure the Forward Error Correction...
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-11-29 Anusha Srivatsadrm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-11-29 Anusha Srivatsai915/dp/fec: Add fec_enable to the crtc state.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-11-03 Anusha Srivatsadrm/dp/fec: DRM helper for Forward Error Correction
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-11-03 Anusha Srivatsai915/dp/fec: Cache the FEC_CAPABLE DPCD register
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-11-02 Anusha Srivatsadrm/i915/fia: FIA registers offset implementation.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-11-02 Anusha Srivatsadrm/i915/icl: Fix DSS_CTL register names
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-11-01 Anusha Srivatsadrm/i915/icl: Fix DC9 Suspend for ICL.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-11-01 Anusha Srivatsadrm/i915/icl: Add DSS_CTL Registers
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-10-31 Anusha Srivatsadrm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-10-18 Anusha Srivatsafirmware/dmc/icl: Add missing MODULE_FIRMWARE() for...
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-10-05 Anusha Srivatsafirmware/dmc/icl: Add missing MODULE_FIRMWARE() for...
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-10-01 Anusha Srivatsadrm/i915: Do not redefine the has_csr parameter.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-09-13 Anusha Srivatsafirmware/dmc/icl: load v1.07 on icelake.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-08-17 Anusha Srivatsadrm/i915: Do not redefine the has_csr parameter.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-07-27 Anusha Srivatsadrm/i915/icl: Set TBT IO in Aux transaction
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-07-27 Anusha Srivatsadrm/i915/icl: Add TBT checks for PLL calculations
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-07-20 Anusha Srivatsadrm/i915/dsc: Add missing _MMIO() from PPS registers
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-07-19 Anusha Srivatsai915/dp/dsc: Add Rate Control Range Parameter Registers
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-07-19 Anusha Srivatsai915/dp/dsc: Add Rate Control Buffer Threshold Registers
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-07-19 Anusha Srivatsai915/dp/dsc: Add DSC PPS register definitions
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-07-19 Anusha Srivatsadrm/i915/icl: Add VIDEO_DIP registers
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-06-27 Anusha Srivatsadrm/i915/icp: Add Interrupt Support
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-06-22 Anusha Srivatsadrm/i915/guc: Remove USES_GUC_SUBMISSION for ads programming
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-06-01 Anusha Srivatsadrm/i915/icl: Add Icelake PCH detection
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-05-02 Anusha Srivatsadrm/i915/firmware: Correct URL for firmware
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-02-15 Anusha Srivatsadrm: Add DPCD definitions for DP 1.4 FEC feature
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-02-01 Anusha Srivatsadrm/i915/glk: Disable Guc and HuC on GLK
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-01-19 Anusha Srivatsadrm/i915/icp: Add the ID for ICL PCH - ICP
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-01-19 Anusha Srivatsadrm/i915/icp: add ICP gmbus and gpio support
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-01-19 Anusha Srivatsadrm/i915/icp: Add backlight Support for ICP
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-01-19 Anusha Srivatsadrm/i915/icp: Add Panel Power Sequencing Support
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-01-19 Anusha Srivatsadrm/i915/icp: Get/set proper Raw clock frequency on ICP
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-01-19 Anusha Srivatsadrm/i915/icp: Introduce Ice Lake PCH
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-01-05 Anusha Srivatsadrm/i915/dmc: DMC 1.07 for Cannonlake
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2018-01-04 Anusha Srivatsadrm/i915/glk: Disable Guc and HuC on GLK
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2017-12-05 Anusha Srivatsadrm/i915/skl: DMC firmware for skylake v1.27
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2017-11-23 Anusha Srivatsadrm/i915/dmc: DMC 1.04 for Kabylake
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2017-10-24 Anusha Srivatsadrm/i915/cnl: Update the DMC version on CNL
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2017-08-17 Anusha Srivatsadrm/i915: Split pin mapping into per platform functions
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2017-06-12 Anusha Srivatsadrm/i915/DMC/CNL: Load DMC on CNL
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2017-06-09 Anusha Srivatsadrm/i915/huc: Load HuC on Coffee Lake
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2017-06-09 Anusha Srivatsadrm/i915/guc: Load GuC on Coffee Lake
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2017-06-09 Anusha Srivatsadrm/i915/cfl: Add Coffee Lake PCI IDs for U Sku.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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2017-06-09 Anusha Srivatsadrm/i915/cfl: Add Coffee Lake PCI IDs for H Sku.
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
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