2017-05-04 | Kito Cheng | RISC-V: Fix disassemble for c.li, c.andi and c.addiw 2017-05-03 Kito Cheng <kito.cheng@gmail.com> |
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2017-03-15 | Kito Cheng | RISC-V: Fix assembler for c.li, c.andi and c.addiw 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
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2017-03-15 | Kito Cheng | RISC-V: Fix assembler for c.addi, rd can be x0 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
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2017-01-03 | Kito Cheng | Add support for the Q extension to the RISCV ISA. |
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2014-09-30 | Kito Cheng | Fix SysV-style hash table when --hash-style=both. |
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