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configs: reset: fu540: enable dm reset framework for SiFive
2020-08-04
Sagar Shrikant Kadam
configs: reset: fu540: enable dm reset framework for...
Signed-off-by:
Sagar Shrikant Kadam
<sagar.kadam@sifive.com>
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2020-08-04
Sagar Shrikant Kadam
sifive: reset: add DM based reset driver for SiFive...
Signed-off-by:
Sagar Shrikant Kadam
<sagar.kadam@sifive.com>
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2020-08-04
Sagar Shrikant Kadam
fu540: dtsi: add reset producer and consumer entries
Signed-off-by:
Sagar Shrikant Kadam
<sagar.kadam@sifive.com>
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2020-08-04
Sagar Shrikant Kadam
fu540: prci: use common reset indexes defined in binding...
Signed-off-by:
Sagar Shrikant Kadam
<sagar.kadam@sifive.com>
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2020-08-04
Sagar Shrikant Kadam
dt-bindings: prci: add indexes for reset signals available...
Signed-off-by:
Sagar Shrikant Kadam
<sagar.kadam@sifive.com>
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2020-07-01
Sagar Shrikant Kadam
riscv: cpu: check and append L1 cache to cpu features
Signed-off-by:
Sagar Shrikant Kadam
<sagar.kadam@sifive.com>
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2020-07-01
Sagar Shrikant Kadam
riscv: cpu: correctly handle the setting of CPU_FEAT_MMU bit
Signed-off-by:
Sagar Shrikant Kadam
<sagar.kadam@sifive.com>
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2020-07-01
Sagar Shrikant Kadam
uclass: cpu: fix to display proper CPU features
Signed-off-by:
Sagar Shrikant Kadam
<sagar.kadam@sifive.com>
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2020-07-01
Sagar Shrikant Kadam
riscv: dts: hifive-unleashed-a00: add cpu aliases
Signed-off-by:
Sagar Shrikant Kadam
<sagar.kadam@sifive.com>
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2019-10-18
Sagar Shrikant Kadam
configs: fu540: enable gpio driver
Signed-off-by:
Sagar Shrikant Kadam
<sagar.kadam@sifive.com>
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2019-10-18
Sagar Shrikant Kadam
gpio: sifive: add support for DM based gpio driver...
Signed-off-by:
Sagar Shrikant Kadam
<sagar.kadam@sifive.com>
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2019-09-03
Sagar Shrikant Kadam
riscv: sifive: fu540: set serial environment variable...
Signed-off-by:
Sagar Shrikant Kadam
<sagar.kadam@sifive.com>
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2019-08-15
Sagar Shrikant Kadam
riscv : serial: use rx watermark to indicate rx data...
Signed-off-by:
Sagar Shrikant Kadam
<sagar.kadam@sifive.com>
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