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drm/amdgpu: Enable VCN on navi14
2019-07-18 James Zhudrm/amdgpu: Enable VCN on navi14
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2019-06-17 James Zhudrm/amdgpu: explicitly set mmGDS_VMID0_BASE to 0
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2019-06-11 James Zhudrm/amdgpu: Add GDS clearing workaround in later init...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2019-06-11 James Zhudrm/amdgpu: Fixed missing to clear some EDC count
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2019-05-24 James Zhudrm/amdgpu: Fix S3 test issue
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2019-05-24 James Zhudrm/amdgpu: add gfx9 gpr EDC workaround when RAS is...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2019-05-24 James Zhudrm/amdgpu: add EDC counter register
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-12-20 James Zhudrm/amdgpu/uvd:Change uvd ring name convention
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-12-18 James Zhudrm/amdgpu:Improves robustness of SOC15_WAIT_ON_RREG
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-12-18 James Zhudrm/amdgpu/vcn:Remove bit 31 for scratch2 to indicate...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-12-18 James Zhudrm/amdgpu/vcn:Scan enc/jpeg fences to init dpg pause...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-12-18 James Zhudrm/amdgpu/vcn:Always check all vcn ring status during...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-12-18 James Zhudrm/amdgpu/vcn:Update ring point to JPEG before init...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-12-18 James Zhudrm/amdgpu/vcn:Always gate vcn block during hw finishing
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-12-18 James Zhudrm/amdgpu/vcn: Update vcn.cur_state during suspend
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-12-05 James Zhudrm/amdgpu/vcn: Update vcn.cur_state during suspend
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-17 James Zhudrm/amdgpu/vcn:Fix uninitialized symbol error
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Update SPG mode UVD status clear
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Set VCPU busy after gate power during...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Remove SPG mode unused steps during...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Add SPG mode Register XX check
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Move SPG mode mc resume after MPC control
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Update SPG mode VCN global tiling
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Update SPG mode VCN memory control
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Apply new UMC enable for VNC DPG mode...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Remove DPG mode unused steps during...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Add DPG mode Register XX check
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Update DPG mode VCN global tiling registers
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Update DPG mode VCN memory control
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Reduce unnecessary local variable
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Add ring W/R PTR check for VCN DPG mode...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Update latest spg mode stop for VCN
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Update latest UVD_MPC register for VCN
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-12 James Zhudrm/amdgpu/vcn:Add new register offset/mask for VCN
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-09 James Zhudrm/amdgpu/vcn:Correct VCN cache window definition
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-09 James Zhudrm/amdgpu/vcn:Replace value with defined macro
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-09 James Zhudrm/amdgpu/vcn:fix dpg pause mode hang issue
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-10-09 James Zhudrm/amdgpu/vcn:Remove unused code
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-09-27 James Zhudrm/amdgpu:Enable DPG mode on PCO
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-09-27 James Zhudrm/amdgpu:Add DPG pause mode support
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-09-27 James Zhudrm/amdgpu:Add DPG pause state
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-09-27 James Zhudrm/amdgpu:Add DPG mode support for vcn 1.0
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-09-27 James Zhudrm/amdgpu:Add DPG mode read/write macro
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-09-27 James Zhudrm/amdgpu:Add DPG support flag
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-09-27 James Zhudrm/amdgpu:Add new register offset/mask to support...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-09-27 James Zhudrm/amdgpu:Use register UVD_SCRATCH9 for VCN ring/ib...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-09-13 James Zhudrm/amdgpu:Add error message when register failed to...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-06-27 James Zhudrm/amdgpu:Support new VCN FW version naming convention
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-06-19 James Zhudrm/amdgpu:All UVD instances share one idle_work handle
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-06-15 James Zhudrm/amdgpu/vg20:support new UVD FW version naming convention
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-05-18 James Zhudrm/amdgpu/vg20:Enable UVD/VCE for Vega20
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-05-18 James Zhudrm/amdgpu/vg20:Enable 2nd instance queue maping for...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-05-18 James Zhudrm/amdgpu/vg20:Enable the 2nd instance IRQ for uvd 7.2
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-05-18 James Zhudrm/amdgpu/vg20:Add IH client ID for the 2nd UVD
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-05-18 James Zhudrm/amdgpu/vg20:Enable the 2nd instance for uvd
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-05-18 James Zhudrm/amdgpu/vg20:increase 3 rings for AMDGPU_MAX_RINGS
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-05-18 James Zhudrm/amdgpu/vg20:Restruct uvd.inst to support multiple...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-05-18 James Zhudrm/amdgpu/vg20:Restruct uvd to support multiple uvds
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-05-17 James Zhudrm/amd/include/vg20: adjust VCE_BASE to reuse vce...
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-04-11 James Zhudrm/amdgpu: Added support for MV packet
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-03-07 James Zhudrm/amdgpu:Always save uvd vcpu_bo in VM Mode
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-03-07 James Zhudrm/amdgpu:Correct max uvd handles
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-03-07 James Zhudrm/amdgpu:Always save uvd vcpu_bo in VM Mode
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-03-07 James Zhudrm/amdgpu:Correct max uvd handles
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-02-28 James Zhudrm/amdgpu:Fixed wrong emit frame size for enc
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-02-28 James Zhudrm/amdgpu:Fixed wrong emit frame size for enc
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2018-01-23 James Zhudrm/amd/amdgpu: Add Polaris version check
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2017-10-06 James Zhudrm/amdgpu: add uvd enc irq
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2017-10-06 James Zhudrm/amdgpu: add uvd enc ib test
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2017-10-06 James Zhudrm/amdgpu: add uvd enc ring test
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2017-10-06 James Zhudrm/amdgpu: add uvd enc vm functions (v2)
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2017-10-06 James Zhudrm/amdgpu: add uvd enc into run queue
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2017-10-06 James Zhudrm/amdgpu: add uvd enc rings
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2017-10-06 James Zhudrm/amdgpu: add new uvd enc ring methods
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2017-10-06 James Zhudrm/amdgpu: add uvd enc command in header
Signed-off-by: James Zhu <James.Zhu@amd.com>
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2017-10-06 James Zhudrm/amdgpu: add uvd enc registers in header
Signed-off-by: James Zhu <James.Zhu@amd.com>
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