2024-01-31 | Monk Chiang | RISC-V: Recognized zihintntl extensions |
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2023-02-03 | Monk Chiang | RISC-V: Remove unnecessary register class. |
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2022-10-26 | Monk Chiang | RISC-V: Recognized Svinval and Svnapot extensions |
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2022-10-21 | Monk Chiang | RISC-V: Add type attribute for atomic instructions. |
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2020-11-14 | Monk Chiang | PR target/97682 - Fix to reuse t1 register between... 2020-11-13 Monk Chiang <monk.chiang@sifive.com> 2020-11-13 Monk Chiang <monk.chiang@sifive.com> |
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