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| 2019-07-01 | Anup Patel | RISC-V: Fix memory reservation in setup_bootmem() Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Loys Ollivier | riscv: defconfig: enable SOC_SIFIVE [paul.walmsley@sifive.com: updated to apply] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Loys Ollivier | riscv: select SiFive platform drivers with SOC_SIFIVE Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Loys Ollivier | arch: riscv: add config option for building SiFive... Cc: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Andy Lutomirski | riscv: Remove gate area stubs Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Paul Walmsley | MAINTAINERS: change the arch/riscv git tree to the... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Paul Walmsley | MAINTAINERS: don't automatically patches involving... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Anup Patel | RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERS Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-26 | ShihPo Hung | riscv: mm: Fix code comment Cc: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-26 | Paul Walmsley | dt-bindings: clock: sifive: add MIT license as an option... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-26 | Paul Walmsley | dt-bindings: riscv: resolve 'make dt_binding_check... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-26 | Yash Shah | riscv: dts: Re-organize the DT nodes Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-26 | Atish Patra | RISC-V: defconfig: enable MMC & SPI for RISC-V [paul.walmsley@sifive.com: mention the DEVTMPFS_MOUNT... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-17 | Rolf Eike Beer | riscv: remove unused barrier defines [paul.walmsley@sifive.com: stripped spurious mbox header... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-17 | ShihPo Hung | riscv: mm: synchronize MMU after pte change [paul.walmsley@sifive.com: reversed tab->whitespace conversion, Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-17 | Paul Walmsley | riscv: dts: add initial board data for the SiFive HiFive... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-17 | Paul Walmsley | riscv: dts: add initial support for the SiFive FU540... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-17 | Paul Walmsley | dt-bindings: riscv: convert cpu binding to json-schema Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-17 | Paul Walmsley | dt-bindings: riscv: sifive: add YAML documentation... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-17 | Paul Walmsley | arch: riscv: add support for building DTB files from... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-11 | Nick Hu | riscv: Fix udelay in RV32. [paul.walmsley@sifive.com: fixed minor spelling error] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-11 | Andreas Schwab | riscv: export pm_power_off again Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-11 | Kevin Hilman | RISC-V: defconfig: enable clocks, serial console Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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