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acpi: Add support for SSDT generation
2020-07-14 Pragnesh Patelmmc_spi: generate R1b response for erase and stop transmissi...
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-07-14 Pragnesh Patelmmc: mmc_spi: Generate R1 response for erase block...
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-07-14 Pragnesh Patelmmc: mmc_spi: Read R2 response for send status command...
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-07-14 Pragnesh Patelmmc: read ssr for SD spi
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-07-14 Pragnesh Patelmmc: mmc_spi: generate R1 response for different mmc...
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-07-14 Pragnesh Patelmmc: mmc_spi: correct the while condition
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-07-09 Pragnesh Patelmtd: spi-nor: Enable QE bit for ISSI flash in case...
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-07-03 Pragnesh Patelriscv: sifive: fu540: enable all cache ways from U...
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Pateldoc: sifive: fu540: Add description for OpenSBI generic...
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelconfigs: fu540: Add config options for U-Boot SPL
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelriscv: sifive: fu540: add SPL configuration
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelriscv: cpu: fu540: Add support for cpu fu540
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelriscv: dts: sifive: Sync hifive-unleashed-a00 dts from...
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelriscv: sifive: dts: fu540: set ethernet clock rate
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelclk: sifive: fu540-prci: Release ethernet clock reset
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelclk: sifive: fu540-prci: Add ddr clock initialization
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelclk: sifive: fu540-prci: Add clock enable and disable ops
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelriscv: sifive: dts: fu540: add U-Boot dmc node
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelsifive: dts: fu540: Add DDR controller and phy register...
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelsifive: fu540: add ddr driver
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelriscv: sifive: dts: fu540: Add board -u-boot.dtsi files
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patellib: Makefile: build crc7.c when CONFIG_MMC_SPI
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelriscv: Add _image_binary_end for SPL
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelriscv: sifive: fu540: Use OTP DM driver for serial...
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-06-04 Pragnesh Patelmisc: add driver for the SiFive otp controller
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-05-26 Pragnesh Patelsifive: fix palmer's email address
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-05-21 Pragnesh Patelefi_loader: Remove unnecessary debug
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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2020-04-23 Pragnesh Patelriscv: ax25: cache: Remove SPL_RISCV_MMODE config check
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
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