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fpga: intel_sdm_mb: Add watchdog reset
2020-10-09 Chee Hong Angfpga: intel_sdm_mb: Add watchdog reset
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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2020-10-09 Chee Hong Angfpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM...
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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2020-10-09 Chee Hong Angarm: socfpga: Use DM watchdog timer
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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2020-10-09 Chee Hong Angarm: socfpga: soc64: Show reset state in SPL
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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2020-10-09 Chee Hong Angarm: socfpga: soc64: Add SDM triggered warm reset bit...
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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2020-10-09 Chee Hong Angsysreset: socfpga: agilex: Enable sysreset support
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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2020-10-09 Chee Hong Angsysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver...
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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2020-10-09 Chin Liang Seeconfigs: socfpga: soc64: Avoid SPL enter infinite loop...
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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2020-10-09 Chee Hong Angarm: socfpga: soc64: Initialize timer in SPL only
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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2020-10-09 Chee Hong Angarm: socfpga: soc64: Remove PHY interface setup from...
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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2020-10-09 Chee Hong Angclk: agilex: Additional membus writes for HPS PLL
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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2020-10-09 Chee Hong Angclk: agilex: Handle clock configuration differently...
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2020-10-09 Ley Foon Tanclk: agilex: Add clock enable support
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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2020-10-09 Ley Foon Tanclk: agilex: Add NAND clock support
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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2020-09-03 Chee Hong Angarm: socfpga: soc64: Check FPGA Config status register...
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
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2020-06-26 Ley Foon Tanarm: socfpga: misc_s10: Fix EMAC register address calculation
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
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