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riscv: stack: Fixup independent irq stack for CONFIG_FRAME_POINTER=n
2023-08-16
Guo Ren
riscv: stack: Fixup independent irq stack for CONFIG_FRAME_P...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-16
Nam Cao
riscv: correct riscv_insn_is_c_jr() and riscv_insn_is_c_jalr()
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-16
Celeste Liu
riscv: entry: set a0 = -ENOSYS only when syscall != -1
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-10
Alexandre Ghiti
riscv: Implement flush_cache_vmap()
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-10
Alexandre Ghiti
riscv: Do not allow vmap pud mappings for 3-level page...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-08
Nick Desaulniers
riscv: mm: fix 2 instances of -Wmissing-variable-declarations
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-08
Andrea Parri
riscv,mmio: Fix readX()-to-delay() ordering
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-08
Samuel Holland
riscv: Fix CPU feature detection with SMP disabled
Reported-by: Palmer Dabbelt <
palmer@rivosinc.com
>
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-04
Alexandre Ghiti
riscv: Start of DRAM should at least be aligned on...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-04
Palmer Dabbelt
Merge patch series "RISC-V: Fix a few kexec_file_load...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-04
Torsten Duwe
riscv/kexec: load initrd high in available memory
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-04
Torsten Duwe
riscv/kexec: handle R_RISCV_CALL_PLT relocation type
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-02
Song Shuai
Documentation: kdump: Add va_kernel_pa_offset for RISCV64
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-02
Song Shuai
riscv: Export va_kernel_pa_offset in vmcoreinfo
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-02
Sunil V L
RISC-V: ACPI: Fix acpi_os_ioremap to return iomem address
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-02
Alexandre Ghiti
selftests: riscv: Fix compilation error with vstate_exec_nol...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-08-02
John Hubbard
selftests/riscv: fix potential build failure during...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-12
Palmer Dabbelt
RISC-V: Don't include Zicsr or Zifencei in I from ACPI
...kernel.org/r/20230711224600.10879-1-
palmer@rivosinc.com
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-12
Jisheng Zhang
riscv: mm: fix truncation warning on RV32
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-12
Eric Lin
perf: RISC-V: Remove PERF_HES_STOPPED flag checking...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-11
Palmer Dabbelt
Documentation: RISC-V: hwprobe: Fix a formatting error
...kernel.org/r/20230710193329.2742-1-
palmer@rivosinc.com
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-06
Palmer Dabbelt
Merge patch series "riscv: some CMO alternative related...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-06
Jisheng Zhang
riscv: mm: mark noncoherent_supported as __ro_after_init
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-06
Jisheng Zhang
riscv: mm: mark CBO relate initialization funcs as...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-06
Jisheng Zhang
riscv: errata: thead: only set cbom size & noncoherent...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-06
Samuel Holland
riscv: Select HAVE_ARCH_USERFAULTFD_MINOR
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
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2023-07-06
Palmer Dabbelt
RISC-V: Document the ISA string parsing rules for ACPI
...kernel.org/r/20230629031705.15575-1-
palmer@rivosinc.com
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-05
Marc Zyngier
risc-v: Fix order of IPI enablement vs RCU startup
Cc: Palmer Dabbelt <
palmer@rivosinc.com
>
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-05
John Hubbard
mm: riscv: fix an unsafe pte read in huge_pte_alloc()
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-05
Conor Dooley
dt-bindings: riscv: deprecate riscv,isa
Reviewed-by: Palmer Dabbelt <
palmer@rivosinc.com
>
Acked-by: Palmer Dabbelt <
palmer@rivosinc.com
>
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-04
Conor Dooley
RISC-V: drop error print from riscv_hartid_to_cpuid()
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-04
Björn Töpel
riscv: Discard vector state on syscalls
Suggested-by: Palmer Dabbelt <
palmer@rivosinc.com
>
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-04
Woody Zhang
riscv: move memblock_allow_resize() after linear mapping...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-04
Song Shuai
riscv: Enable ARCH_SUSPEND_POSSIBLE for s2idle
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-04
Ben Dooks
riscv: vdso: include vdso/vsyscall.h for vdso_data
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-01
Andy Chiu
selftests: Test RISC-V Vector's first-use handler
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-01
Andy Chiu
riscv: vector: clear V-reg in the first-use trap
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-01
Andy Chiu
riscv: vector: only enable interrupts in the first...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-01
Palmer Dabbelt
Merge patch series "riscv: enable HAVE_LD_DEAD_CODE_DATA_ELI...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-01
Palmer Dabbelt
RISC-V: Fix up some vector state related build failures
...kernel.org/r/20230619172101.18692-1-
palmer@rivosinc.com
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-07-01
Palmer Dabbelt
RISC-V: Document that V registers are clobbered on...
...kernel.org/r/20230619190142.26498-1-
palmer@rivosinc.com
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-25
Nick Desaulniers
riscv: disable HAVE_LD_DEAD_CODE_DATA_ELIMINATION for LLD
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-25
Zhangjin Wu
riscv: enable HAVE_LD_DEAD_CODE_DATA_ELIMINATION
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-25
Jisheng Zhang
vmlinux.lds.h: use correct .init.data.* section name
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-25
Jisheng Zhang
riscv: vmlinux-xip.lds.S: remove .alternative section
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-25
Jisheng Zhang
riscv: move options to keep entries sorted
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-23
Palmer Dabbelt
Merge patch series "dt-bindings: riscv: cpus: switch...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-23
Song Shuai
riscv: hibernate: remove WARN_ON in save_processor_state
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-23
Palmer Dabbelt
Merge patch series "riscv: Add independent irq/softirq...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-23
Palmer Dabbelt
Merge patch series "ISA string parser cleanups"
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-22
Conor Dooley
dt-bindings: riscv: cpus: switch to unevaluatedProperties...
Acked-by: Palmer Dabbelt <
palmer@rivosinc.com
>
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-22
Conor Dooley
dt-bindings: riscv: cpus: add a ref the common cpu...
Acked-by: Palmer Dabbelt <
palmer@rivosinc.com
>
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-22
Guo Ren
riscv: stack: Add config of thread stack size
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-22
Guo Ren
riscv: stack: Support HAVE_SOFTIRQ_ON_OWN_STACK
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-22
Guo Ren
riscv: stack: Support HAVE_IRQ_EXIT_ON_IRQ_STACK
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-21
Conor Dooley
RISC-V: always report presence of extensions formerly...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-21
Conor Dooley
dt-bindings: riscv: explicitly mention assumption of...
Suggested-by: Palmer Dabbelt <
palmer@rivosinc.com
>
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-21
Conor Dooley
RISC-V: remove decrement/increment dance in ISA string...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-21
Conor Dooley
RISC-V: rework comments in ISA string parser
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-21
Conor Dooley
RISC-V: validate riscv,isa at boot, not during ISA...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-21
Conor Dooley
RISC-V: split early & late of_node to hartid mapping
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-21
Conor Dooley
RISC-V: simplify register width check in ISA string...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-20
Viacheslav Mitrofanov
perf: RISC-V: Limit the number of counters returned...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-20
Fangrui Song
riscv: replace deprecated scall with ecall
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-20
Tiezhu Yang
riscv: uprobes: Restore thread.bad_cause
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-20
Jisheng Zhang
riscv: mm: try VMA lock-based page fault handling first
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-20
Björn Töpel
riscv: mm: Pre-allocate PGD entries for vmalloc/modules...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-19
Palmer Dabbelt
Merge patch series "RISC-V: Export Zba, Zbb to usermode...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-19
Evan Green
RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-19
Evan Green
RISC-V: Track ISA extensions per hart
Reviewed-by: Palmer Dabbelt <
palmer@rivosinc.com
>
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-19
Evan Green
RISC-V: Add Zba, Zbs extension probing
Reviewed-by: Palmer Dabbelt <
palmer@rivosinc.com
>
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-19
Krzysztof Kozlowski
dt-bindings: riscv: cpus: drop unneeded quotes
Acked-by: Palmer Dabbelt <
palmer@rivosinc.com
>
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-19
Sunil V L
RISC-V/perf: Use standard interface to get INTC domain
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-19
Sunil V L
RISC-V: ACPI : Fix for usage of pointers in different...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-19
Song Shuai
riscv: hibernation: Remove duplicate call of suspend_restore...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-19
Song Shuai
riscv: hibernation: Replace jalr with jr before suspend_rest...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-14
Conor Dooley
Documentation: RISC-V: patch-acceptance: mention patchwork...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-14
Jisheng Zhang
riscv: mm: stub extable related functions/macros for...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-14
Ben Dooks
riscv: say disabling zicbom if no or bad riscv,cbom...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Ruan Jinjie
riscv: fix kprobe __user string arg print fault issue
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Palmer Dabbelt
Merge patch series "riscv: Add vector ISA support"
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Andy Chiu
selftests: add .gitignore file for RISC-V hwprobe
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Andy Chiu
selftests: Test RISC-V Vector prctl interface
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Andy Chiu
riscv: Add documentation for Vector
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Guo Ren
riscv: Enable Vector code to be built
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Andy Chiu
riscv: detect assembler support for .option arch
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Andy Chiu
riscv: Add sysctl to set the default vector rule for...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Andy Chiu
riscv: Add prctl controls for userspace vector management
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Andy Chiu
riscv: hwcap: change ELF_HWCAP to a function
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Vincent Chen
riscv: KVM: Add vector lazy save/restore support
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Vincent Chen
riscv: kvm: Add V extension to KVM ISA
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Greentime Hu
riscv: prevent stack corruption by reserving task_pt_regs...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Andy Chiu
riscv: signal: validate altstack to reflect Vector
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Vincent Chen
riscv: signal: Report signal frame size to userspace...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Greentime Hu
riscv: signal: Add sigcontext save/restore for vector
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Andy Chiu
riscv: signal: check fp-reserved words unconditionally
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Greentime Hu
riscv: Add ptrace vector support
Reviewed-by: Palmer Dabbelt <
palmer@rivosinc.com
>
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Andy Chiu
riscv: Allocate user's vector context in the first...
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Greentime Hu
riscv: Add task switch support for vector
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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2023-06-08
Greentime Hu
riscv: Introduce struct/helpers to save/restore per...
Reviewed-by: Palmer Dabbelt <
palmer@rivosinc.com
>
Signed-off-by: Palmer Dabbelt <
palmer@rivosinc.com
>
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