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clk: meson: clk-pll: remove od parameters
2018-09-26
Jerome Brunet
clk: meson: clk-pll: remove od parameters
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-09-26
Jerome Brunet
clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-09-26
Jerome Brunet
clk: meson: clk-pll: add enable bit
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-07-09
Jerome Brunet
clk: meson: add gen_clk
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-07-09
Jerome Brunet
clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-07-09
Yixun Lan
clk: meson-axg: add clocks required by pcie driver
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-07-09
Jerome Brunet
clk: meson: remove unused clk-audio-divider driver
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-07-09
Jerome Brunet
clk: meson: stop rate propagation for audio clocks
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-07-09
Jerome Brunet
clk: meson: axg: add the audio clock controller driver
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-07-09
Jerome Brunet
clk: meson: add axg audio sclk divider driver
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-07-09
Jerome Brunet
Merge remote-tracking branch 'clk/clk-core-duty-cycle...
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2018-07-09
Jerome Brunet
clk: meson: add triple phase clock driver
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-07-09
Jerome Brunet
clk: meson: add clk-phase clock driver
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-07-09
Jerome Brunet
Merge branch 'next/dt' into next/drivers
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2018-07-09
Jerome Brunet
clk: meson: clean-up meson clock configuration
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-07-09
Jerome Brunet
clk: meson: remove obsolete register access
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-07-09
Jerome Brunet
clk: meson: expose GEN_CLK clkid
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-07-03
Yixun Lan
clk: meson-axg: add pcie and mipi clock bindings
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-06-22
Jerome Brunet
dt-bindings: clock: add meson axg audio clock controller...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-06-21
Jerome Brunet
clk: meson: audio-divider is one based
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-06-19
Neil Armstrong
clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-05-21
Jerome Brunet
clk: meson: axg: let mpll clocks round closest
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-05-21
Jerome Brunet
clk: meson: mpll: add round closest support
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-05-21
Martin Blumenstingl
clk: meson: meson8b: mark fclk_div2 gate clocks as...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-05-18
Jerome Brunet
clk: meson: use SPDX license identifiers consistently
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-05-15
Yixun Lan
clk: meson: drop CLK_SET_RATE_PARENT flag
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-05-15
Qiufang Dai
clk: meson-axg: Add AO Clock and Reset controller driver
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-05-15
Yixun Lan
clk: meson: aoclk: refactor common code into dedicated...
Suggested-by:
Jerome Brunet
<jbrunet@baylibre.com>
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-05-15
Jerome Brunet
Merge branch 'next/bindings' into next/drivers
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2018-05-15
Yixun Lan
clk: meson: migrate to devm_of_clk_add_hw_provider API
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-05-15
Maxime Jourdan
clk: meson: gxbb: add the video decoder clocks
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-05-15
Martin Blumenstingl
clk: meson: meson8b: add support for the NAND clocks
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-05-15
Yixun Lan
dt-bindings: clock: reset: Add AXG AO Clock and Reset...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-05-15
Yixun Lan
dt-bindings: clock: axg-aoclkc: New binding for Meson...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-04-25
Maxime Jourdan
clk: meson: gxbb: expose VDEC_1 and VDEC_HEVC clocks
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-04-25
Martin Blumenstingl
dt-bindings: clock: meson8b: export the NAND clock
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-04-25
Martin Blumenstingl
clk: meson: meson8b: fix meson8b_cpu_clk parent clock...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-04-25
Martin Blumenstingl
clk: meson: meson8b: fix meson8b_fclk_div3_div clock...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-04-25
Yixun Lan
clk: meson: drop meson_aoclk_gate_regmap_ops
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-02-12
Jerome Brunet
clk: meson: add axg misc bit to the mpll driver
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-02-12
Yixun Lan
clk: meson: axg: fix the od shift of the sys_pll
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-02-12
Jerome Brunet
clk: meson: axg: add the fractional part of the fixed_pll
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-02-12
Jerome Brunet
clk: meson: gxbb: add the fractional part of the fixed_pll
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-02-12
Jerome Brunet
clk: meson: fix rate calculation of plls with a fractional...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-02-12
Jerome Brunet
clk: meson: add the gxl hdmi pll
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-02-12
Jerome Brunet
clk: meson: add od3 to the pll driver
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-02-12
Jerome Brunet
clk: meson: use the frac parameter width instead of...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-02-12
Jerome Brunet
clk: meson: remove unnecessary rounding in the pll...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-02-12
Jerome Brunet
clk: meson: remove useless pll rate params tables
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2018-02-12
Jerome Brunet
clk: meson: check pll rate param table before using it
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-12-23
Martin Blumenstingl
clk: meson: mpll: use 64-bit maths in params_from_rate
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-12-14
Qiufang Dai
clk: meson-axg: add clock controller drivers
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-12-14
Jerome Brunet
Merge branch 'next/dt' into next/drivers
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2017-12-14
Qiufang Dai
clk: meson-axg: add clocks dt-bindings required header
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-12-14
Yixun Lan
dt-bindings: clock: add compatible variant for the...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-12-14
Yixun Lan
clk: meson: make the spinlock naming more specific
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-12-08
Jerome Brunet
clk: meson: gxbb: remove IGNORE_UNUSED from mmc clocks
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-11-27
Yixun Lan
clk: meson: gxbb: fix wrong clock for SARADC/SANA
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-06-16
Jerome Brunet
clk: meson: gxbb: add all clk81 parents
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-06-16
Jerome Brunet
Merge branch 'next/headers' into next/drivers
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2017-06-12
Martin Blumenstingl
clk: meson: meson8b: add compatibles for Meson8 and...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-06-12
Martin Blumenstingl
clk: meson8b: export the ethernet gate clock
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-06-12
Martin Blumenstingl
clk: meson8b: export the USB clocks
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-06-12
Martin Blumenstingl
clk: meson8b: export the gate clock for the HW random...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-06-12
Martin Blumenstingl
clk: meson8b: export the SDIO clock
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-06-12
Martin Blumenstingl
clk: meson8b: export the SAR ADC clocks
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-05-29
Neil Armstrong
clk: meson-gxbb: Add EE 32K Clock for CEC
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-05-29
Martin Blumenstingl
clk: meson: gxbb: remove the "cpu_clk" from the GXBB...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-05-29
Martin Blumenstingl
clk: meson-gxbb: un-export the CPU clock
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-05-29
Helmut Klein
clk: meson-gxbb: expose UART clocks
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-05-29
Neil Armstrong
clk: meson-gxbb: expose SPICC gate
Acked-by:
Jerome Brunet
<jbrunet@baylibre.com>
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-05-29
Jerome Brunet
clk: meson-gxbb: expose spdif master clock
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-05-29
Jerome Brunet
clk: meson-gxbb: expose i2s master clock
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-05-29
Jerome Brunet
clk: meson-gxbb: expose spdif clock gates
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-04-07
Martin Blumenstingl
clk: meson: mpll: use 64bit math in rate_from_params
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-04-07
Martin Blumenstingl
clk: meson: mpll: fix division by zero in rate_from_params
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-04-07
Jerome Brunet
clk: meson: gxbb: add cts_i958 clock
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-04-07
Jerome Brunet
clk: meson: gxbb: add cts_mclk_i958
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-04-07
Jerome Brunet
clk: meson: gxbb: add cts_amclk
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-04-07
Jerome Brunet
clk: meson: add audio clock divider support
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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2017-04-07
Jerome Brunet
clk: meson: gxbb: protect against holes in the onecell_data...
Signed-off-by:
Jerome Brunet
<jbrunet@baylibre.com>
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