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clk: versal: Fix watchdog clock issue
2020-02-28
Rajan Vaja
versal: drivers: clk: Fix invalid clock name queries
Signed-off-by:
Rajan Vaja
<rajan.vaja@xilinx.com>
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2019-10-24
Rajan Vaja
dt-bindings: clock: zynqmp: Add clk header
Signed-off-by:
Rajan Vaja
<rajan.vaja@xilinx.com>
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2019-10-08
Rajan Vaja
zynqmp: firmware: Add Xilinx ZynqMP firmware driver
Signed-off-by:
Rajan Vaja
<rajan.vaja@xilinx.com>
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2018-09-29
Rajan Vaja
dm: test: Add "/firmware" node scan test
Signed-off-by:
Rajan Vaja
<rajan.vaja@xilinx.com>
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2018-09-29
Rajan Vaja
firmware: Add FIRMWARE config prompt string
Signed-off-by:
Rajan Vaja
<rajan.vaja@xilinx.com>
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2018-09-18
Rajan Vaja
dm: core: Scan "/firmware" node by default
Signed-off-by:
Rajan Vaja
<rajan.vaja@xilinx.com>
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2018-09-18
Rajan Vaja
dm: core: Move "/clock" node scan into function
Signed-off-by:
Rajan Vaja
<rajan.vaja@xilinx.com>
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2018-05-31
Rajan Vaja
arm64: zynqmp: Add TTC clocks
Signed-off-by:
Rajan Vaja
<rajan.vaja@xilinx.com>
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2018-05-31
Rajan Vaja
soc: zynqmp: Update required API version to 1.0
Signed-off-by:
Rajan Vaja
<rajanv@xilinx.com>
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