2023-12-08 |
Rohan Garg | intel/compiler: infer the number of operands using... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-10-24 |
Rohan Garg | anv: selectively enable FCV optimization for DG2 Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-10-24 |
Rohan Garg | anv: turn off non zero fast clears for CCS_E Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-10-24 |
Rohan Garg | anv: cleanup includes Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-10-17 |
Rohan Garg | anv: fix debug string for PC flush Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-10-11 |
Rohan Garg | anv: enable FCV for Gen12.5 Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-10-11 |
Rohan Garg | anv: ensure that FCV_CCS_E fast clears are properly... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-10-11 |
Rohan Garg | intel/genxml: fix 3DSTATE_3D_MODE length to align with... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-09-21 |
Rohan Garg | intel/compiler: Adjust barrier emission for Xe2+ Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-09-21 |
Rohan Garg | intel/compiler: Adjust fence message lengths for new... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-09-21 |
Rohan Garg | intel/compiler: Adjust CS payload registers for new... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-09-19 |
Rohan Garg | anv: define clear color localy within can_fast_clear_color_att Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-09-12 |
Rohan Garg | intel/genxml: update PIPE_CONTROL instruction for dg2 Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-09-06 |
Rohan Garg | iris: migrate preemption streamwout wa to WA infra Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-09-03 |
Rohan Garg | blorp: drop undefined macro Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-09-03 |
Rohan Garg | crocus: fix GFX_VERx10 macro Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-09-03 |
Rohan Garg | crocus: add a __gen_get_batch_address declaration Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-09-03 |
Rohan Garg | anv: use the lineage number for WA Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-09-03 |
Rohan Garg | iris: use the correct WA macros and lineage numbers Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-09-03 |
Rohan Garg | anv: drop dead ifdef Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-09-01 |
Rohan Garg | anv: use the pre defined _3DPRIMITIVE_DIRECT macro Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-08-18 |
Rohan Garg | anv: emitting 3DSTATE_PRIMITIVE_REPLICATION is required... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-07-31 |
Rohan Garg | anv: partially revert 2e8b1f6d Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-07-27 |
Rohan Garg | iris: allow for a unsynchronized device reset query Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-07-27 |
Rohan Garg | iris: track reset signalling instead of replacing the... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-07-21 |
Rohan Garg | anv: drop CFE state validation checks Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-07-21 |
Rohan Garg | anv,iris: program the maximum number of threads on... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-07-20 |
Rohan Garg | anv: use the correct GFX_VERx10 macro for WA Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-07-20 |
Rohan Garg | anv: use the WA infrastructure where possible when... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-07-18 |
Rohan Garg | intel/genxml: set a default value for "Pixel Position... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-07-17 |
Rohan Garg | intel/perf: add perf query support for Intel Raptorlake Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-07-17 |
Rohan Garg | iris: fix iris for WA 16013000631 Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-07-14 |
Rohan Garg | iris: migrate WA 14016118574 to use the WA framework Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-07-14 |
Rohan Garg | iris: migrate WA 14013910100 to use the WA framework Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-06-30 |
Rohan Garg | anv: retry batchbuffer submission with i915 Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-06-30 |
Rohan Garg | intel/compiler: reuse previously computed bitsize Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-06-30 |
Rohan Garg | intel/compiler: construct masks instead of using magic... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-06-29 |
Rohan Garg | anv: move WA 1607854226 to use the WA infrastructure Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-06-12 |
Rohan Garg | anv: split ANV_PIPE_RENDER_TARGET_BUFFER_WRITES for... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-31 |
Rohan Garg | hasvk: enable single texel alignment Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-31 |
Rohan Garg | anv: fix incorrect asserts when combining CPS and per... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-29 |
Rohan Garg | anv: limit non zero fast clear check to GFX12_CCS_E Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-29 |
Rohan Garg | anv: set aux usage to GFX12_CCS_E if a platform needs... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-29 |
Rohan Garg | isl: add helper to check if aux usage is CCS_E Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-29 |
Rohan Garg | anv: enable single texel alignment Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-25 |
Rohan Garg | util: move pot functions to use existing macros Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-25 |
Rohan Garg | util: revert back to ALIGN since it moved to util Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-25 |
Rohan Garg | util: migrate alignment functions and macros to use... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-25 |
Rohan Garg | util: fix ROUND_DOWN_TO alignment type Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-25 |
Rohan Garg | freedreno: set alignment to next POT Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-25 |
Rohan Garg | ac/surface: make sure alignment is a POT Signed-off-by: Rohan Garg <rohan@garg.io>
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2023-05-25 |
Rohan Garg | iris: correctly set alignment to next power of two... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-18 |
Rohan Garg | anv: drop duplicate checks when setting the compressed bit Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-18 |
Rohan Garg | intel: infer scalar'ness locally for brw_vectorize_lower_mem... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-18 |
Rohan Garg | intel: update comments about non-existent function... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-18 |
Rohan Garg | intel: drop unused is_scalar function parameter in... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-18 |
Rohan Garg | intel: infer scalar'ness locally for brw_postprocess_nir Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-17 |
Rohan Garg | anv: drop duplicated nir_opt_dce passes Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-17 |
Rohan Garg | anv: use the common vulkan runtime to do the heavy... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-09 |
Rohan Garg | iris: use the workaround framework for WA 14013111325 Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-09 |
Rohan Garg | hasvk: drop dead code Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-05-09 |
Rohan Garg | anv: use the workaround framework for WA 14013111325 Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-04-06 |
Rohan Garg | anv,blorp,iris: Set PreferredSLMAllocationSize on gfx125+ Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-04-06 |
Rohan Garg | intel/genxml: Add the preferred slm size enum for gen125 Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-03-22 |
Rohan Garg | anv,hasvk: cleanup unused enum
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2023-03-15 |
Rohan Garg | anv: break out of the loop when the first color attachment... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-02-14 |
Rohan Garg | anv/blorp: use existing function to convert the op... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-02-14 |
Rohan Garg | isl: fix some documentation Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-02-14 |
Rohan Garg | anv: reuse the VK_IMAGE_ASPECT_PLANES_BITS_ANV macro Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-02-14 |
Rohan Garg | anv: drop unused headers
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2023-01-20 |
Rohan Garg | iris: Don't flush the render cache for a compute batch Signed-off-by: Rohan Garg's avatarRohan Garg <rohan.garg...
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2023-01-06 |
Rohan Garg | anv,hasvk: move the null check into the function call... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-01-06 |
Rohan Garg | anv: Drop useless FIXME Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-01-06 |
Rohan Garg | anv,hasvk: drop unused function Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-01-06 |
Rohan Garg | anv,hasvk: migrate to ROUND_DOWN_TO from util Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-01-06 |
Rohan Garg | anv,hasvk: migrate to u_minify from util Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-01-06 |
Rohan Garg | anv: migrate anv_minify to use u_minify Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-01-06 |
Rohan Garg | anv,hasvk: migrate to align64 from util Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-01-06 |
Rohan Garg | anv,hasvk: migrate align32 to the right functions from... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-01-06 |
Rohan Garg | anv,hasvk: Use the inbuilt macro from src/util for... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2023-01-06 |
Rohan Garg | anv: constify variables and use early returns Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2022-12-20 |
Rohan Garg | anv: Ensure we clear ANV_PIPE_PSS_STALL_SYNC_BIT on... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2022-12-15 |
Rohan Garg | anv: Refactor anv_pipeline to use the anv_pipeline_type Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2022-10-17 |
Rohan Garg | anv: Enable 16 bit float ops on devices that have a LSC Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2022-10-17 |
Rohan Garg | intel/compiler: Support 16 bit float ops Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2022-10-11 |
Rohan Garg | anv, iris: Disable pre fetching the binding table entries... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2022-04-13 |
Rohan Garg | iris: set a default EDSC flag Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2022-03-30 |
Rohan Garg | anv: Drop dead code in anv_UpdateDescriptorSets Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2022-02-11 |
Rohan Garg | anv: Handle VK_DESCRIPTOR_POOL_CREATE_HOST_ONLY_BIT_VALVE... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2022-02-09 |
Rohan Garg | anv: Refactor descriptor copy Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2022-01-24 |
Rohan Garg | docs: Update features and new_features for anv Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2022-01-24 |
Rohan Garg | anv: Enable VK_VALVE_mutable_descriptor_type Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2022-01-18 |
Rohan Garg | ci/piglit: Start vtest server if driver is set to virpipe Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
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2022-01-18 |
Rohan Garg | ci: Do not remove wget Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
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2022-01-18 |
Rohan Garg | ci: Move common variables out into a separate file Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
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2022-01-18 |
Rohan Garg | ci: Do not remove libgbm-dev Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
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2022-01-07 |
Rohan Garg | intel/fs: OpImageQueryLod does not support arrayed... Signed-off-by: Rohan Garg <rohan.garg@intel.com>
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2021-09-09 |
Rohan Garg | ci: Use FDO_DISTRIBUTION_TAG where possible Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
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2021-08-30 |
Rohan Garg | ci: Fix a minor issue in prepare-artifacts.sh script Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
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2021-07-29 |
Rohan Garg | i965: Write a custom allocator for the intel memobj... Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
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