projects / platform / kernel / linux-rpi.git / search
| 2022-10-21 | Andrew Jones | RISC-V: Fix compilation without RISCV_ISA_ZICBOM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Jisheng Zhang | riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Jisheng Zhang | RISC-V: KVM: Use generic guest entry infrastructure Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Jisheng Zhang | RISC-V: KVM: Record number of signal exits as a vCPU... Signed-off-by: Anup Patel <anup@brainfault.org |
commit | commitdiff | tree |
| 2022-10-02 | Xiu Jianfeng | RISC-V: KVM: add __init annotation to riscv_kvm_init() Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Andrew Jones | RISC-V: KVM: Expose Zicbom to the guest Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Andrew Jones | RISC-V: KVM: Provide UAPI for Zicbom block size Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Andrew Jones | RISC-V: KVM: Make ISA ext mappings explicit Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Mayuresh Chitale | RISC-V: KVM: Allow Guest use Zihintpause extension Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Anup Patel | RISC-V: KVM: Allow Guest use Svinval extension Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Anup Patel | RISC-V: KVM: Use Svinval for local TLB maintenance... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Mayuresh Chitale | RISC-V: Probe Svinval extension form ISA string Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Anup Patel | RISC-V: KVM: Change the SBI specification version to... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Andrew Jones | riscv: KVM: Apply insn-def to hlv encodings Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Andrew Jones | riscv: KVM: Apply insn-def to hfence encodings Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Andrew Jones | riscv: Introduce support for defining instructions Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-10-02 | Andrew Jones | riscv: Add X register names to gpr-nums Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-08-19 | Conor Dooley | riscv: kvm: move extern sbi_ext declarations to a header Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-08-19 | Conor Dooley | riscv: kvm: vcpu_timer: fix unused variable warnings Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-07-29 | Anup Patel | RISC-V: KVM: Add support for Svpbmt inside Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-07-29 | Anup Patel | RISC-V: KVM: Use PAGE_KERNEL_IO in kvm_riscv_gstage_ioremap() Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-07-29 | Anup Patel | RISC-V: KVM: Add G-stage ioremap() and iounmap() functions Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-07-29 | Anup Patel | KVM: Add gfp_custom flag in struct kvm_mmu_memory_cache Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-07-29 | Anup Patel | RISC-V: KVM: Add extensible CSR emulation framework Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-07-29 | Anup Patel | RISC-V: KVM: Add extensible system instruction emulation... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-07-29 | Anup Patel | RISC-V: KVM: Factor-out instruction emulation into... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-07-29 | Nikolay Borisov | RISC-V: KVM: move preempt_disable() call in kvm_arch_vcpu_io... Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-07-29 | Nikolay Borisov | RISC-V: KVM: Make kvm_riscv_guest_timer_init a void... Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-07-29 | Zhang Jiaming | RISC-V: KVM: Fix variable spelling mistake Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-07-29 | Atish Patra | RISC-V: KVM: Improve ISA extension by using a bitmap Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-07-11 | Anup Patel | RISC-V: KVM: Fix SRCU deadlock caused by kvm_riscv_check_vcp... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-07-11 | Alexandre Ghiti | riscv: Fix missing PAGE_PFN_MASK Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-06-09 | Lukas Bulwahn | MAINTAINERS: Limit KVM RISC-V entry to existing selftests Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-06-09 | Julia Lawall | RISC-V: KVM: fix typos in comments Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-05-20 | Anup Patel | MAINTAINERS: Update KVM RISC-V entry to cover selftests... Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-05-20 | Atish Patra | RISC-V: KVM: Introduce ISA extension register Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-05-20 | Anup Patel | RISC-V: KVM: Cleanup stale TLB entries when host CPU... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-05-20 | Anup Patel | RISC-V: KVM: Add remote HFENCE functions based on VCPU... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-05-20 | Anup Patel | RISC-V: KVM: Reduce KVM_MAX_VCPUS value Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-05-20 | Anup Patel | RISC-V: KVM: Introduce range based local HFENCE functions Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-05-20 | Anup Patel | RISC-V: KVM: Treat SBI HFENCE calls as NOPs Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-05-20 | Anup Patel | RISC-V: KVM: Add Sv57x4 mode support for G-stage Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-05-20 | Anup Patel | RISC-V: KVM: Use G-stage name for hypervisor page table Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-05-20 | Jiapeng Chong | KVM: selftests: riscv: Remove unneeded semicolon Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-05-20 | Anup Patel | KVM: selftests: riscv: Improve unexpected guest trap... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-04-20 | Atish Patra | RISC-V: KVM: Restrict the extensions that can be disabled Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-04-20 | Atish Patra | RISC-V: KVM: Remove 's' & 'u' as valid ISA extension Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-04-09 | Heiko Stuebner | RISC-V: KVM: include missing hwcap.h into vcpu_fp Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-04-09 | Anup Patel | KVM: selftests: riscv: Fix alignment of the guest_hang... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-04-09 | Anup Patel | KVM: selftests: riscv: Set PTE A and D bits in VS-stage... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-04-09 | Anup Patel | RISC-V: KVM: Don't clear hgatp CSR in kvm_arch_vcpu_put() Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-03-11 | Anup Patel | RISC-V: KVM: Implement SBI HSM suspend call Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-03-11 | Anup Patel | RISC-V: KVM: Add common kvm_riscv_vcpu_wfi() function Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-03-11 | Anup Patel | RISC-V: Add SBI HSM suspend related defines Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-03-11 | Anup Patel | RISC-V: KVM: Implement SBI v0.3 SRST extension Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-03-11 | Anup Patel | RISC-V: KVM: Add common kvm_riscv_vcpu_sbi_system_reset... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-03-11 | Anup Patel | RISC-V: KVM: Upgrade SBI spec version to v0.3 Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-03-11 | Vincent Chen | RISC-V: KVM: Refine __kvm_riscv_switch_to() implementation Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-03-11 | Guo Ren | KVM: compat: riscv: Prevent KVM_COMPAT from being selected Cc: Anup Patel <anup@brainfault.org> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-03-11 | Yang Li | RISC-V: KVM: remove unneeded semicolon Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-02-02 | Anup Patel | RISC-V: KVM: Fix SBI implementation version Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-02-02 | Mayuresh Chitale | RISC-V: KVM: make CY, TM, and IR counters accessible... Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-02-02 | Mark Rutland | kvm/riscv: rework guest entry logic Cc: Anup Patel <anup@brainfault.org> Tested-by: Anup Patel <anup@brainfault.org> Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-01-06 | Anup Patel | MAINTAINERS: Update Anup's email address Signed-off-by: Anup Patel <anup@brainfault.org> |
commit | commitdiff | tree |
| 2022-01-06 | Vincent Chen | KVM: RISC-V: Avoid spurious virtual interrupts after... Reviewed-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2022-01-06 | Anup Patel | KVM: selftests: Add initial support for RISC-V 64-bit Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2022-01-06 | Anup Patel | KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2022-01-06 | Anup Patel | RISC-V: KVM: Add VM capability to allow userspace get... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2022-01-06 | Anup Patel | RISC-V: KVM: Forward SBI experimental and vendor extensions Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2022-01-06 | Jisheng Zhang | RISC-V: KVM: make kvm_riscv_vcpu_fp_clean() static Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2022-01-06 | Atish Patra | MAINTAINERS: Update Atish's email address Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2022-01-06 | Atish Patra | RISC-V: KVM: Add SBI HSM extension in KVM Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2022-01-06 | Atish Patra | RISC-V: KVM: Add v0.1 replacement SBI extensions defined... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2022-01-06 | Atish Patra | RISC-V: KVM: Add SBI v0.2 base extension Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2022-01-06 | Atish Patra | RISC-V: KVM: Reorganize SBI code by moving SBI v0.1... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2022-01-06 | Atish Patra | RISC-V: KVM: Mark the existing SBI implementation as... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2022-01-06 | Sean Christopherson | KVM: RISC-V: Use common KVM implementation of MMU memory... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-11-22 | Anup Patel | RISC-V: KVM: Fix incorrect KVM_MAX_VCPUS value Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-11-22 | Sean Christopherson | KVM: RISC-V: Unmap stage2 mapping when deleting/moving... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-11-01 | Bixuan Cui | RISC-V: KVM: fix boolreturn.cocci warnings Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-11-01 | ran jianping | RISC-V: KVM: remove unneeded semicolon Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Anup Patel | RISC-V: KVM: Add MAINTAINERS entry Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Anup Patel | RISC-V: KVM: Document RISC-V specific parts of KVM API Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Atish Patra | RISC-V: KVM: Add SBI v0.1 support Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Atish Patra | RISC-V: KVM: Implement ONE REG interface for FP registers Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Atish Patra | RISC-V: KVM: FP lazy save/restore Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Atish Patra | RISC-V: KVM: Add timer functionality Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Anup Patel | RISC-V: KVM: Implement MMU notifiers Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Anup Patel | RISC-V: KVM: Implement stage2 page table programming Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Anup Patel | RISC-V: KVM: Implement VMID allocator Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Anup Patel | RISC-V: KVM: Handle WFI exits for VCPU Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Anup Patel | RISC-V: KVM: Handle MMIO exits for VCPU Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Anup Patel | RISC-V: KVM: Implement VCPU world-switch Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Anup Patel | RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Anup Patel | RISC-V: KVM: Implement VCPU interrupts and requests... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Anup Patel | RISC-V: KVM: Implement VCPU create, init and destroy... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2021-10-04 | Anup Patel | RISC-V: Add initial skeletal KVM support Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2019-02-21 | Anup Patel | RISC-V: Free-up initrd in free_initrd_mem() Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2019-02-21 | Anup Patel | RISC-V: Implement compile-time fixed mappings Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| 2019-02-21 | Anup Patel | RISC-V: Move setup_vm() to mm/init.c Signed-off-by: Anup Patel <anup.patel@wdc.com> |
commit | commitdiff | tree |
| next | |||