projects / platform / kernel / linux-rpi.git / search
| 2023-11-20 | Anup Patel | RISC-V: Don't fail in riscv_of_parent_hartid() for... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-11-20 | Anup Patel | irqchip/sifive-plic: Fix syscore registration for multi... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-10-07 | Anup Patel | irqchip/riscv-intc: Mark all INTC nodes as initialized Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-09-21 | Anup Patel | KVM: riscv: selftests: Selectively filter-out AIA registers Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-09-21 | Anup Patel | KVM: riscv: selftests: Fix ISA_EXT register handling... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-09-21 | Anup Patel | RISC-V: KVM: Fix riscv_vcpu_get_isa_ext_single() for... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-09-21 | Anup Patel | RISC-V: KVM: Fix KVM_GET_REG_LIST API for ISA_EXT registers Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-08-08 | Anup Patel | RISC-V: KVM: Sort ISA extensions alphabetically in... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-08-08 | Anup Patel | RISC-V: KVM: Allow Zicntr, Zicsr, Zifencei, and Zihpm... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-08-08 | Anup Patel | RISC-V: KVM: Allow Zba and Zbs extensions for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-08-08 | Anup Patel | RISC-V: KVM: Extend ONE_REG to enable/disable multiple... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-08-08 | Anup Patel | RISC-V: KVM: Factor-out ONE_REG related code to its... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-20 | Anup Patel | RISC-V: KVM: Allow Svnapot extension for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-19 | Anup Patel | RISC-V: KVM: Expose IMSIC registers as attributes of... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-19 | Anup Patel | RISC-V: KVM: Add in-kernel virtualization of AIA IMSIC Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Expose APLIC registers as attributes of... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Add in-kernel emulation of AIA APLIC Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Implement device interface for AIA irqchip Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Skeletal in-kernel AIA irqchip support Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Set kvm_riscv_aia_nr_hgei to zero Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Add APLIC related defines Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Add IMSIC related defines Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-06-18 | Anup Patel | RISC-V: KVM: Implement guest external interrupt line... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Virtualize per-HART AIA CSRs Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Use bitmap for irqs_pending and irqs_pending_mask Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Add ONE_REG interface for AIA CSRs Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Implement subtype for CSR ONE_REG interface Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Initial skeletal support for AIA Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Drop the _MASK suffix from hgatp.VMID... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: Detect AIA CSRs from ISA string Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: Add AIA related CSR defines Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Allow Zbb extension for Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-21 | Anup Patel | RISC-V: KVM: Add ONE_REG interface to enable/disable... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-04-08 | Anup Patel | irqchip/riscv-intc: Add empty irq_eoi() for chained... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-04-08 | Anup Patel | RISC-V: Use IPIs for remote icache flush when possible Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-04-08 | Anup Patel | RISC-V: Use IPIs for remote TLB flush when possible Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-04-08 | Anup Patel | RISC-V: Allow marking IPIs as suitable for remote FENCEs Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-04-08 | Anup Patel | RISC-V: Treat IPIs as normal Linux IRQs Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-04-08 | Anup Patel | irqchip/riscv-intc: Allow drivers to directly discover... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-04-08 | Anup Patel | RISC-V: Clear SIP bit only when using SBI IPI operations Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-02-13 | Anup Patel | clocksource/drivers/timer-riscv: Set CLOCK_EVT_FEAT_C3STOP... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-02-13 | Anup Patel | dt-bindings: timer: Add bindings for the RISC-V timer... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-02-07 | Anup Patel | RISC-V: KVM: Fix privilege mode setting in kvm_riscv_vcpu_tr... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2023-02-05 | Anup Patel | genirq: Add mechanism to multiplex a single HW IPI Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-12-08 | Anup Patel | RISC-V: Enable PMEM drivers Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-12-08 | Anup Patel | RISC-V: Implement arch specific PMEM APIs Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-12-08 | Anup Patel | RISC-V: Fix MEMREMAP_WB for systems with Svpbmt Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-12-07 | Anup Patel | RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-12-07 | Anup Patel | RISC-V: KVM: Save mvendorid, marchid, and mimpid when... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-12-07 | Anup Patel | RISC-V: Export sbi_get_mvendorid() and friends Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-12-07 | Anup Patel | RISC-V: KVM: Move sbi related struct and functions... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-12-07 | Anup Patel | RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-12-07 | Anup Patel | RISC-V: KVM: Remove redundant includes of asm/csr.h Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-12-07 | Anup Patel | RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-12-07 | Anup Patel | RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_con... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-12-07 | Anup Patel | RISC-V: KVM: Exit run-loop immediately if xfer_to_guest... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-10-21 | Anup Patel | RISC-V: KVM: Fix kvm_riscv_vcpu_timer_pending() for... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-10-04 | Anup Patel | RISC-V: Increase range and default value of NR_CPUS Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-10-04 | Anup Patel | RISC-V: Add mvendorid, marchid, and mimpid to /proc... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-10-02 | Anup Patel | RISC-V: KVM: Allow Guest use Svinval extension Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-10-02 | Anup Patel | RISC-V: KVM: Use Svinval for local TLB maintenance... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-10-02 | Anup Patel | RISC-V: KVM: Change the SBI specification version to... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-09-23 | Anup Patel | cpuidle: riscv-sbi: Fix CPU_PM_CPU_IDLE_ENTER_xyz(... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-07-29 | Anup Patel | RISC-V: KVM: Add support for Svpbmt inside Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-07-29 | Anup Patel | RISC-V: KVM: Use PAGE_KERNEL_IO in kvm_riscv_gstage_ioremap() Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-07-29 | Anup Patel | RISC-V: KVM: Add G-stage ioremap() and iounmap() functions Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-07-29 | Anup Patel | KVM: Add gfp_custom flag in struct kvm_mmu_memory_cache Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-07-29 | Anup Patel | RISC-V: KVM: Add extensible CSR emulation framework Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-07-29 | Anup Patel | RISC-V: KVM: Add extensible system instruction emulation... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-07-29 | Anup Patel | RISC-V: KVM: Factor-out instruction emulation into... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-07-11 | Anup Patel | RISC-V: KVM: Fix SRCU deadlock caused by kvm_riscv_check_vcp... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | MAINTAINERS: Update KVM RISC-V entry to cover selftests... Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | RISC-V: KVM: Cleanup stale TLB entries when host CPU... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | RISC-V: KVM: Add remote HFENCE functions based on VCPU... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | RISC-V: KVM: Reduce KVM_MAX_VCPUS value Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | RISC-V: KVM: Introduce range based local HFENCE functions Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | RISC-V: KVM: Treat SBI HFENCE calls as NOPs Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | RISC-V: KVM: Add Sv57x4 mode support for G-stage Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | RISC-V: KVM: Use G-stage name for hypervisor page table Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | KVM: selftests: riscv: Improve unexpected guest trap... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-04-21 | Anup Patel | RISC-V: mm: Fix set_satp_mode() for platform not having... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-04-09 | Anup Patel | KVM: selftests: riscv: Fix alignment of the guest_hang... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-04-09 | Anup Patel | KVM: selftests: riscv: Set PTE A and D bits in VS-stage... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-04-09 | Anup Patel | RISC-V: KVM: Don't clear hgatp CSR in kvm_arch_vcpu_put() Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-31 | Anup Patel | RISC-V: Enable profiling by default Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-11 | Anup Patel | RISC-V: KVM: Implement SBI HSM suspend call Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-11 | Anup Patel | RISC-V: KVM: Add common kvm_riscv_vcpu_wfi() function Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-11 | Anup Patel | RISC-V: Add SBI HSM suspend related defines Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-11 | Anup Patel | RISC-V: KVM: Implement SBI v0.3 SRST extension Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-11 | Anup Patel | RISC-V: KVM: Add common kvm_riscv_vcpu_sbi_system_reset... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-11 | Anup Patel | RISC-V: KVM: Upgrade SBI spec version to v0.3 Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-10 | Anup Patel | RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-10 | Anup Patel | dt-bindings: Add common bindings for ARM and RISC-V... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-10 | Anup Patel | cpuidle: Add RISC-V SBI CPU idle driver Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-10 | Anup Patel | cpuidle: Factor-out power domain related code from... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-10 | Anup Patel | RISC-V: Add SBI HSM suspend related defines Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-10 | Anup Patel | RISC-V: Add arch functions for non-retentive suspend... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-10 | Anup Patel | RISC-V: Rename relocate() and make it global Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-10 | Anup Patel | RISC-V: Enable CPU_IDLE drivers Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@vetanamicro.com> |
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| 2022-02-02 | Anup Patel | RISC-V: KVM: Fix SBI implementation version Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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