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| 2022-01-27 | Robert Hancock | net: axienet: fix number of TX ring slots for available... Signed-off-by: Robert Hancock <robert.hancock@calian.com> |
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| 2022-01-27 | Robert Hancock | net: axienet: Fix TX ring slot available check Signed-off-by: Robert Hancock <robert.hancock@calian.com> |
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| 2022-01-27 | Robert Hancock | net: axienet: limit minimum TX ring size Signed-off-by: Robert Hancock <robert.hancock@calian.com> |
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| 2022-01-27 | Robert Hancock | net: axienet: add missing memory barriers Signed-off-by: Robert Hancock <robert.hancock@calian.com> |
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| 2022-01-27 | Robert Hancock | net: axienet: reset core on initialization prior to... Signed-off-by: Robert Hancock <robert.hancock@calian.com> |
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| 2022-01-27 | Robert Hancock | net: axienet: Wait for PhyRstCmplt after core reset Signed-off-by: Robert Hancock <robert.hancock@calian.com> |
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| 2022-01-27 | Robert Hancock | net: axienet: increase reset timeout Signed-off-by: Robert Hancock <robert.hancock@calian.com> |
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| 2022-01-27 | Robert Hancock | clk: si5341: Fix clock HW provider cleanup Signed-off-by: Robert Hancock <robert.hancock@calian.com> ...r/20220112203816.1784610-1-robert.hancock@calian.com |
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| 2021-07-14 | Robert Hancock | clk: si5341: Update initialization magic Signed-off-by: Robert Hancock <robert.hancock@calian.com> ...r/20210325192643.2190069-6-robert.hancock@calian.com |
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| 2021-07-14 | Robert Hancock | clk: si5341: Check for input clock presence and PLL... Signed-off-by: Robert Hancock <robert.hancock@calian.com> ...r/20210325192643.2190069-5-robert.hancock@calian.com |
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| 2021-07-14 | Robert Hancock | clk: si5341: Avoid divide errors due to bogus register... Signed-off-by: Robert Hancock <robert.hancock@calian.com> ...r/20210325192643.2190069-4-robert.hancock@calian.com |
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| 2021-07-14 | Robert Hancock | clk: si5341: Wait for DEVICE_READY on startup Signed-off-by: Robert Hancock <robert.hancock@calian.com> ...r/20210325192643.2190069-3-robert.hancock@calian.com |
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| 2021-03-30 | Robert Hancock | net: phy: broadcom: Set proper 1000BaseX/SGMII interface... Signed-off-by: Robert Hancock <robert.hancock@calian.com> |
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| 2021-03-30 | Robert Hancock | net: axienet: Fix probe error cleanup Signed-off-by: Robert Hancock <robert.hancock@calian.com> |
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| 2021-03-30 | Robert Hancock | net: axienet: Properly handle PCS/PMA PHY for 1000BaseX... Signed-off-by: Robert Hancock <robert.hancock@calian.com> ...r/20201028171429.1699922-1-robert.hancock@calian.com |
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| 2021-03-04 | Robert Hancock | net: axienet: Handle deferred probe on clock properly Signed-off-by: Robert Hancock <robert.hancock@calian.com> |
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| 2020-11-04 | Robert Hancock | hwmon: (pmbus) Add mutex locking for sysfs reads Signed-off-by: Robert Hancock <robert.hancock@calian.com> ...r/20201103193315.3011800-1-robert.hancock@calian.com |
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