projects / platform / kernel / linux-starfive.git / search
| 2019-09-05 | Christoph Hellwig | riscv: cleanup send_ipi_mask Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-09-05 | Christoph Hellwig | riscv: refactor the IPI code Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-09-05 | Mao Han | riscv: Add support for libdw Cc: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-09-05 | Mao Han | riscv: Add support for perf registers sampling Cc: Paul Walmsley <paul.walmsley@sifive.com> [paul.walmsley@sifive.com: minor patch description fix] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-09-04 | Mao Han | riscv: Add perf callchain support Cc: Paul Walmsley <paul.walmsley@sifive.com> [paul.walmsley@sifive.com: fixed some 'checkpatch.pl ... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-31 | Masahiro Yamada | riscv: add arch/riscv/Kbuild Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-30 | Logan Gunthorpe | RISC-V: Implement sparsemem [paul.walmsley@sifive.com: updated to apply; minor commit... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-30 | Bin Meng | riscv: Using CSR numbers to access CSRs Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-30 | Paul Walmsley | Merge tag 'common/for-v5.4-rc1/cpu-topology' into for... |
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| 2019-08-28 | Anup Patel | RISC-V: Fix FIXMAP area corruption on RV32 systems Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-14 | Vincent Chen | riscv: Make __fstate_clean() work correctly. [paul.walmsley@sifive.com: expanded "Fixes" commit ID] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-14 | Vincent Chen | riscv: Correct the initialized flow of FP register [paul.walmsley@sifive.com: fixed brace alignment issue... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-14 | Alistair Francis | riscv: defconfig: Update the defconfig Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-14 | Alistair Francis | riscv: rv32_defconfig: Update the defconfig Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-13 | Paul Walmsley | riscv: fix flush_tlb_range() end address for flush_tlb_page() Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-08 | Paul Walmsley | dt-bindings: riscv: fix the schema compatible string... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-08 | Paul Walmsley | dt-bindings: riscv: remove obsolete cpus.txt Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-08 | Palmer Dabbelt | RISC-V: Remove udivdi3 Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-08 | Paul Walmsley | riscv: delay: use do_div() instead of __udivdi3() Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-08 | Atish Patra | dt-bindings: Update the riscv,isa string description Suggested-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-08-06 | Atish Patra | RISC-V: Remove per cpu clocksource Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-31 | Paul Walmsley | riscv: defconfig: align RV64 defconfig to the output... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-31 | Paul Walmsley | riscv: dts: fu540-c000: drop "timebase-frequency" Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-31 | Mao Han | riscv: Fix perf record without libelf support Cc: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-22 | Yash Shah | riscv: dts: Add DT node for SiFive FU540 Ethernet controller... [paul.walmsley@sifive.com: changed "phy1" to "phy0" at... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-22 | Wesley Terpstra | riscv: include generic support for MSI irqdomains [paul.walmsley@sifive.com: split initial patch into one... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-22 | Palmer Dabbelt | MAINTAINERS: Add Paul as a RISC-V maintainer Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-22 | Sudeep Holla | MAINTAINERS: Add an entry for generic architecture... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-22 | Sudeep Holla | base: arch_topology: update Kconfig help description Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-22 | Atish Patra | RISC-V: Parse cpu topology during boot. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-22 | Atish Patra | arm: Use common cpu_topology structure and functions. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-22 | Atish Patra | cpu-topology: Move cpu topology code to common code. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-22 | Atish Patra | dt-binding: cpu-topology: Move cpu-map to a common... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-22 | Sudeep Holla | Documentation: DT: arm: add support for sockets defining... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-19 | Paul Walmsley | riscv: enable sys_clone3 syscall for rv64 Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-18 | Paul Walmsley | riscv: fix build break after macro-to-function conversion... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-11 | Atish Patra | RISC-V: Add an Image header that boot loader can parse. [paul.walmsley@sifive.com: fixed whitespace in boot-image... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-09 | Anup Patel | RISC-V: Setup initial page tables in two stages [paul.walmsley@sifive.com: updated to apply; fixed a checkpatch... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-04 | Christoph Hellwig | riscv: remove free_initrd_mem Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-04 | Yash Shah | riscv: ccache: Remove unused variable Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-03 | Alexandre Ghiti | riscv: Introduce huge page support for 32/64bit kernel Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-03 | Alexandre Ghiti | x86, arm64: Move ARCH_WANT_HUGE_PMD_SHARE config in... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Anup Patel | RISC-V: Fix memory reservation in setup_bootmem() Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Loys Ollivier | riscv: defconfig: enable SOC_SIFIVE [paul.walmsley@sifive.com: updated to apply] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Loys Ollivier | riscv: select SiFive platform drivers with SOC_SIFIVE Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Loys Ollivier | arch: riscv: add config option for building SiFive... Cc: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Andy Lutomirski | riscv: Remove gate area stubs Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Paul Walmsley | MAINTAINERS: change the arch/riscv git tree to the... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Paul Walmsley | MAINTAINERS: don't automatically patches involving... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-07-01 | Anup Patel | RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERS Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-26 | ShihPo Hung | riscv: mm: Fix code comment Cc: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-26 | Paul Walmsley | dt-bindings: clock: sifive: add MIT license as an option... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-26 | Paul Walmsley | dt-bindings: riscv: resolve 'make dt_binding_check... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-26 | Yash Shah | riscv: dts: Re-organize the DT nodes Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-26 | Atish Patra | RISC-V: defconfig: enable MMC & SPI for RISC-V [paul.walmsley@sifive.com: mention the DEVTMPFS_MOUNT... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-17 | Rolf Eike Beer | riscv: remove unused barrier defines [paul.walmsley@sifive.com: stripped spurious mbox header... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-17 | ShihPo Hung | riscv: mm: synchronize MMU after pte change [paul.walmsley@sifive.com: reversed tab->whitespace conversion, Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-17 | Paul Walmsley | riscv: dts: add initial board data for the SiFive HiFive... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-17 | Paul Walmsley | riscv: dts: add initial support for the SiFive FU540... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-17 | Paul Walmsley | dt-bindings: riscv: convert cpu binding to json-schema Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-17 | Paul Walmsley | dt-bindings: riscv: sifive: add YAML documentation... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-17 | Paul Walmsley | arch: riscv: add support for building DTB files from... Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-11 | Nick Hu | riscv: Fix udelay in RV32. [paul.walmsley@sifive.com: fixed minor spelling error] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-11 | Andreas Schwab | riscv: export pm_power_off again Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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| 2019-06-11 | Kevin Hilman | RISC-V: defconfig: enable clocks, serial console Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> |
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