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MAINTAINERS: Change to my personal email address
2019-10-30
Palmer Dabbelt
MAINTAINERS: Change to my personal email address
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2019-10-01
Palmer Dabbelt
RISC-V: Clear load reservations while restoring hart...
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2019-09-14
Palmer Dabbelt
Documentation: Add "earlycon=sbi" to the admin guide
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2019-08-08
Palmer Dabbelt
RISC-V: Remove udivdi3
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2019-07-22
Palmer Dabbelt
MAINTAINERS: Add Paul as a RISC-V maintainer
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2019-06-26
Palmer Dabbelt
net: macb: Kconfig: Rename Atmel to Cadence
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2019-06-26
Palmer Dabbelt
net: macb: Kconfig: Make MACB depend on COMMON_CLK
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2019-05-17
Palmer Dabbelt
RISC-V: Avoid using invalid intermediate translations
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2019-04-30
Palmer Dabbelt
KVM: PPC: Book3S HV: smb->smp comment fixup
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2019-03-04
Palmer Dabbelt
RISC-V: Fixmap support and MM cleanups
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2019-02-11
Palmer Dabbelt
Revert "RISC-V: Make BSS section as the last section...
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2019-01-23
Palmer Dabbelt
RISC-V: defconfig: Add CRYPTO_DEV_VIRTIO=y
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2019-01-23
Palmer Dabbelt
RISC-V: defconfig: Move CONFIG_PCI{,E_XILINX}
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2019-01-07
Palmer Dabbelt
Fix a handful of audit-related issue
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2018-12-21
Palmer Dabbelt
RISC-V: Move from EARLY_PRINTK to SBI earlycon
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2018-10-31
Palmer Dabbelt
lib: Remove umoddi3 and udivmoddi4
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-31
Palmer Dabbelt
Move EM_RISCV into elf-em.h
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-31
Palmer Dabbelt
Revert "lib: Add umoddi3 and udivmoddi4 of GCC library...
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-31
Palmer Dabbelt
Revert "RISC-V: Select GENERIC_LIB_UMODDI3 on RV32"
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-23
Palmer Dabbelt
RISC-V: SMP cleanup and new features
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-23
Palmer Dabbelt
RISC-V: Fix some RV32 bugs and build failures
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-23
Palmer Dabbelt
riscv: Add support to no-FPU systems
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-23
Palmer Dabbelt
RISC-V: Mask out the F extension on systems without D
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-23
Palmer Dabbelt
RISC-V: Don't set cacheinfo.{physical_line_partition...
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-23
Palmer Dabbelt
RISC-V: Use mmgrab()
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-23
Palmer Dabbelt
RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-23
Palmer Dabbelt
RISC-V: Rename riscv_of_processor_hart to riscv_of_processor...
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-23
Palmer Dabbelt
RISC-V: Provide a cleaner raw_smp_processor_id()
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-23
Palmer Dabbelt
RISC-V: Comment on the TLB flush in smp_callin()
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-23
Palmer Dabbelt
RISC-V: Filter ISA and MMU values in cpuinfo
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-10-23
Palmer Dabbelt
RISC-V: Don't set cacheinfo.{physical_line_partition...
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-08-28
Palmer Dabbelt
RISC-V: Use a less ugly workaround for unused variable...
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-08-28
Palmer Dabbelt
dt-bindings: riscv,cpu-intc: Cleanups from a missed...
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
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2018-08-20
Palmer Dabbelt
RISC-V: Fix sys_riscv_flush_icache
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2018-08-20
Palmer Dabbelt
RISC-V: Don't use a global include guard for uapi/asm...
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-08-20
Palmer Dabbelt
RISC-V: Define sys_riscv_flush_icache when SMP=n
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-08-13
Palmer Dabbelt
RISC-V: Add early printk support via the SBI console
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-08-13
Palmer Dabbelt
RISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building...
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-08-03
Palmer Dabbelt
genirq/irqchip: Remove MULTI_IRQ_HANDLER as it's now...
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
...kernel.org/r/20180622170126.6308-6-
palmer@sifive.com
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2018-08-03
Palmer Dabbelt
openrisc: Use the new GENERIC_IRQ_MULTI_HANDLER
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
...kernel.org/r/20180622170126.6308-5-
palmer@sifive.com
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2018-08-03
Palmer Dabbelt
arm64: Use the new GENERIC_IRQ_MULTI_HANDLER
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
...kernel.org/r/20180622170126.6308-4-
palmer@sifive.com
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2018-08-03
Palmer Dabbelt
ARM: Convert to GENERIC_IRQ_MULTI_HANDLER
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
...kernel.org/r/20180622170126.6308-3-
palmer@sifive.com
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2018-08-03
Palmer Dabbelt
irqchip: Port the ARM IRQ drivers to GENERIC_IRQ_MULTI_HANDLER
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
...kernel.org/r/20180622170126.6308-2-
palmer@sifive.com
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2018-07-17
Palmer Dabbelt
MAINTAINERS: Add Daniel Lustig as an LKMM reviewer
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-07-04
Palmer Dabbelt
RISC-V: Fix the rv32i kernel build
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2018-07-04
Palmer Dabbelt
RISC-V: Don't include irq-riscv-intc.h
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-06-11
Palmer Dabbelt
RISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfig
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-06-11
Palmer Dabbelt
RISC-V: Make our port sparse-clean
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2018-06-11
Palmer Dabbelt
MAINTAINERS: RISC-V Updates
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-06-04
Palmer Dabbelt
RISC-V: Preliminary Perf Support
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-06-04
Palmer Dabbelt
MAINTAINERS: Update Albert's email, he's back at Berkeley
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-06-04
Palmer Dabbelt
MAINTAINERS: Add myself as a maintainer for SiFive...
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-04-23
Palmer Dabbelt
Add notrace to lib/ucmpdi2.c
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-04-04
Palmer Dabbelt
openrisc: Set CONFIG_MULTI_IRQ_HANDLER
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
...kernel.org/r/20180404043130.31277-3-
palmer@sifive.com
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2018-04-04
Palmer Dabbelt
arm64: Set CONFIG_MULTI_IRQ_HANDLER
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
...kernel.org/r/20180404043130.31277-2-
palmer@sifive.com
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2018-04-04
Palmer Dabbelt
genirq: Make GENERIC_IRQ_MULTI_HANDLER depend on !MULTI_IRQ_...
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
...kernel.org/r/20180404043130.31277-4-
palmer@sifive.com
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2018-04-03
Palmer Dabbelt
RISC-V: Rename CONFIG_CMDLINE_OVERRIDE to CONFIG_CMDLINE_FORCE
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-04-03
Palmer Dabbelt
RISC-V: Fixes to module loading
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2018-04-03
Palmer Dabbelt
RISC-V: Assorted memory model fixes
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2018-04-03
Palmer Dabbelt
RISC-V: Add dynamic ftrace support for RISC-V platforms
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2018-03-14
Palmer Dabbelt
RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
...kernel.org/r/20180307235731.22627-3-
palmer@sifive.com
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2018-03-14
Palmer Dabbelt
genirq: Add CONFIG_GENERIC_IRQ_MULTI_HANDLER
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
...kernel.org/r/20180307235731.22627-2-
palmer@sifive.com
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2018-03-09
Palmer Dabbelt
tty: New RISC-V SBI console driver
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-02-20
Palmer Dabbelt
RISC-V: kconfig cleanups
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2018-01-31
Palmer Dabbelt
RISC-V: Remove mem_end command line processing
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-01-31
Palmer Dabbelt
audit: Avoid build failures on systems without renameat
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2018-01-26
Palmer Dabbelt
Update the RISC-V MAINTAINERS file
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2017-12-11
Palmer Dabbelt
RISC-V: Remove unused CONFIG_HVC_RISCV_SBI code
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2017-12-11
Palmer Dabbelt
RISC-V: Resurrect smp_mb__after_spinlock()
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2017-12-01
Palmer Dabbelt
RISC-V: Fixes for clean allmodconfig build
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2017-12-01
Palmer Dabbelt
move libgcc.h to include/linux
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2017-12-01
Palmer Dabbelt
RISC-V: __io_writes should respect the length argument
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2017-12-01
Palmer Dabbelt
RISC-V: User-Visible Changes
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2017-12-01
Palmer Dabbelt
RISC-V Atomic Cleanups
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2017-12-01
Palmer Dabbelt
RISC-V: __io_writes should respect the length argument
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2017-11-30
Palmer Dabbelt
RISC-V: Clean up an unused include
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2017-11-28
Palmer Dabbelt
RISC-V: remove spin_unlock_wait()
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2017-11-28
Palmer Dabbelt
RISC-V: `sfence.vma` orderes the instruction cache
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2017-11-28
Palmer Dabbelt
RISC-V: Add READ_ONCE in arch_spin_is_locked()
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2017-11-28
Palmer Dabbelt
RISC-V: __test_and_op_bit_ord should be strongly ordered
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2017-11-28
Palmer Dabbelt
RISC-V: Remove smb_mb__{before,after}_spinlock()
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2017-11-28
Palmer Dabbelt
RISC-V: Remove __smp_bp__{before,after}_atomic
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2017-11-28
Palmer Dabbelt
RISC-V: Comment on why {,cmp}xchg is ordered how it is
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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2017-11-27
Palmer Dabbelt
RISC-V: Remove __vdso_cmpxchg{32,64} symbol versions
Signed-off-by: Palmer Dabbelt <
palmer@sifive.com
>
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