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| 2023-11-20 | Anup Patel | RISC-V: Don't fail in riscv_of_parent_hartid() for... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2023-11-08 | Anup Patel | irqchip/riscv-intc: Mark all INTC nodes as initialized Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-12-31 | Anup Patel | RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_con... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-12-31 | Anup Patel | RISC-V: Fix MEMREMAP_WB for systems with Svpbmt Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-10-21 | Anup Patel | RISC-V: KVM: Fix kvm_riscv_vcpu_timer_pending() for... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-10-04 | Anup Patel | RISC-V: Increase range and default value of NR_CPUS Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-10-04 | Anup Patel | RISC-V: Add mvendorid, marchid, and mimpid to /proc... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-10-02 | Anup Patel | RISC-V: KVM: Allow Guest use Svinval extension Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-10-02 | Anup Patel | RISC-V: KVM: Use Svinval for local TLB maintenance... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-10-02 | Anup Patel | RISC-V: KVM: Change the SBI specification version to... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-09-23 | Anup Patel | cpuidle: riscv-sbi: Fix CPU_PM_CPU_IDLE_ENTER_xyz(... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-07-29 | Anup Patel | RISC-V: KVM: Add support for Svpbmt inside Guest/VM Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-07-29 | Anup Patel | RISC-V: KVM: Use PAGE_KERNEL_IO in kvm_riscv_gstage_ioremap() Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-07-29 | Anup Patel | RISC-V: KVM: Add G-stage ioremap() and iounmap() functions Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-07-29 | Anup Patel | KVM: Add gfp_custom flag in struct kvm_mmu_memory_cache Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-07-29 | Anup Patel | RISC-V: KVM: Add extensible CSR emulation framework Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-07-29 | Anup Patel | RISC-V: KVM: Add extensible system instruction emulation... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-07-29 | Anup Patel | RISC-V: KVM: Factor-out instruction emulation into... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-07-11 | Anup Patel | RISC-V: KVM: Fix SRCU deadlock caused by kvm_riscv_check_vcp... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | MAINTAINERS: Update KVM RISC-V entry to cover selftests... Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | RISC-V: KVM: Cleanup stale TLB entries when host CPU... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | RISC-V: KVM: Add remote HFENCE functions based on VCPU... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | RISC-V: KVM: Reduce KVM_MAX_VCPUS value Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | RISC-V: KVM: Introduce range based local HFENCE functions Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | RISC-V: KVM: Treat SBI HFENCE calls as NOPs Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | RISC-V: KVM: Add Sv57x4 mode support for G-stage Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | RISC-V: KVM: Use G-stage name for hypervisor page table Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-05-20 | Anup Patel | KVM: selftests: riscv: Improve unexpected guest trap... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-04-21 | Anup Patel | RISC-V: mm: Fix set_satp_mode() for platform not having... Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-04-09 | Anup Patel | KVM: selftests: riscv: Fix alignment of the guest_hang... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-04-09 | Anup Patel | KVM: selftests: riscv: Set PTE A and D bits in VS-stage... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-04-09 | Anup Patel | RISC-V: KVM: Don't clear hgatp CSR in kvm_arch_vcpu_put() Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-31 | Anup Patel | RISC-V: Enable profiling by default Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-11 | Anup Patel | RISC-V: KVM: Implement SBI HSM suspend call Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-11 | Anup Patel | RISC-V: KVM: Add common kvm_riscv_vcpu_wfi() function Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-11 | Anup Patel | RISC-V: Add SBI HSM suspend related defines Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-11 | Anup Patel | RISC-V: KVM: Implement SBI v0.3 SRST extension Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-11 | Anup Patel | RISC-V: KVM: Add common kvm_riscv_vcpu_sbi_system_reset... Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-11 | Anup Patel | RISC-V: KVM: Upgrade SBI spec version to v0.3 Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-03-10 | Anup Patel | RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-10 | Anup Patel | dt-bindings: Add common bindings for ARM and RISC-V... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-10 | Anup Patel | cpuidle: Add RISC-V SBI CPU idle driver Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-10 | Anup Patel | cpuidle: Factor-out power domain related code from... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-10 | Anup Patel | RISC-V: Add SBI HSM suspend related defines Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-10 | Anup Patel | RISC-V: Add arch functions for non-retentive suspend... Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-10 | Anup Patel | RISC-V: Rename relocate() and make it global Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> |
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| 2022-03-10 | Anup Patel | RISC-V: Enable CPU_IDLE drivers Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <apatel@vetanamicro.com> |
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| 2022-02-02 | Anup Patel | RISC-V: KVM: Fix SBI implementation version Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-01-11 | Anup Patel | RISC-V: Use SBI SRST extension when available Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2022-01-06 | Anup Patel | MAINTAINERS: Update Anup's email address Signed-off-by: Anup Patel <anup@brainfault.org> |
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| 2022-01-06 | Anup Patel | KVM: selftests: Add initial support for RISC-V 64-bit Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2022-01-06 | Anup Patel | KVM: selftests: Add EXTRA_CFLAGS in top-level Makefile Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2022-01-06 | Anup Patel | RISC-V: KVM: Add VM capability to allow userspace get... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2022-01-06 | Anup Patel | RISC-V: KVM: Forward SBI experimental and vendor extensions Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-11-22 | Anup Patel | RISC-V: KVM: Fix incorrect KVM_MAX_VCPUS value Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-11-19 | Anup Patel | RISC-V: Enable KVM in RV64 and RV32 defconfigs as a... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-31 | Anup Patel | RISC-V: KVM: Fix GPA passed to __kvm_riscv_hfence_gvma_xyz... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-31 | Anup Patel | RISC-V: KVM: Factor-out FP virtualization into separate... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-04 | Anup Patel | RISC-V: KVM: Add MAINTAINERS entry Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-04 | Anup Patel | RISC-V: KVM: Document RISC-V specific parts of KVM API Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-04 | Anup Patel | RISC-V: KVM: Implement MMU notifiers Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-04 | Anup Patel | RISC-V: KVM: Implement stage2 page table programming Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-04 | Anup Patel | RISC-V: KVM: Implement VMID allocator Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-04 | Anup Patel | RISC-V: KVM: Handle WFI exits for VCPU Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-04 | Anup Patel | RISC-V: KVM: Handle MMIO exits for VCPU Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-04 | Anup Patel | RISC-V: KVM: Implement VCPU world-switch Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-04 | Anup Patel | RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-04 | Anup Patel | RISC-V: KVM: Implement VCPU interrupts and requests... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-04 | Anup Patel | RISC-V: KVM: Implement VCPU create, init and destroy... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-04 | Anup Patel | RISC-V: Add initial skeletal KVM support Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-10-04 | Anup Patel | RISC-V: Add hypervisor extension related CSR defines Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-05-01 | Anup Patel | RISC-V: Fix error code returned by riscv_hartid_to_cpuid() Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-03-30 | Anup Patel | RISC-V: Don't print SBI version for all detected extensions Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-02-27 | Anup Patel | RISC-V: Enable CPU Hotplug in defconfigs Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2021-02-19 | Anup Patel | RISC-V: Implement ASID allocator Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-11-25 | Anup Patel | RISC-V: Add missing jump label initialization Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-11-06 | Anup Patel | RISC-V: Use non-PGD mappings for early DTB access Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-10-02 | Anup Patel | RISC-V: Move DT mapping outof fixmap Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-09-30 | Anup Patel | RISC-V: Check clint_time_val before use Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-08-20 | Anup Patel | dt-bindings: timer: Add CLINT bindings Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-08-20 | Anup Patel | RISC-V: Remove CLINT related code from timer and arch Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-08-20 | Anup Patel | clocksource/drivers: Add CLINT timer driver Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-08-20 | Anup Patel | RISC-V: Add mechanism to provide custom IPI operations Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-06-10 | Anup Patel | RISC-V: Don't mark init section as non-executable Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-06-10 | Anup Patel | RISC-V: Force select RISCV_INTC for CONFIG_RISCV Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-06-10 | Anup Patel | RISC-V: Remove do_IRQ() function Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-06-10 | Anup Patel | clocksource/drivers/timer-riscv: Use per-CPU timer... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-06-10 | Anup Patel | irqchip: RISC-V per-HART local interrupt controller... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-06-10 | Anup Patel | RISC-V: Rename and move plic_find_hart_id() to arch... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-06-10 | Anup Patel | RISC-V: self-contained IPI handling routine Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-05-25 | Anup Patel | irqchip/sifive-plic: Improve boot prints for multiple... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-05-25 | Anup Patel | irqchip/sifive-plic: Setup cpuhp once after boot CPU... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-05-25 | Anup Patel | irqchip/sifive-plic: Set default irq affinity in plic_irqdom... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-05-04 | Anup Patel | RISC-V: Remove N-extension related defines Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-05-04 | Anup Patel | RISC-V: Add bitmap reprensenting ISA features common... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-05-04 | Anup Patel | RISC-V: Export riscv_cpuid_to_hartid_mask() API Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-03-26 | Anup Patel | RISC-V: Only select essential drivers for SOC_VIRT... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-03-05 | Anup Patel | RISC-V: Select Goldfish RTC driver for QEMU virt machine Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-03-05 | Anup Patel | RISC-V: Select SYSCON Reboot and Poweroff for QEMU... Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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| 2020-03-05 | Anup Patel | RISC-V: Enable QEMU virt machine support in defconfigs Signed-off-by: Anup Patel <anup.patel@wdc.com> |
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