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mm/vmstat.c: convert to use DEFINE_SEQ_ATTRIBUTE macro
2020-06-04
Zong Li
arm64: mm: use ARCH_HAS_DEBUG_WX instead of arch defined
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-06-04
Zong Li
x86: mm: use ARCH_HAS_DEBUG_WX instead of arch defined
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-06-04
Zong Li
riscv: support DEBUG_WX
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-06-04
Zong Li
mm: add DEBUG_WX support
...reword text, per Will Deacon &
Zong Li
]
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-05-04
Zong Li
riscv: force __cpu_up_ variables to put in data section
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-03-26
Zong Li
riscv: Use macro definition instead of magic number
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-03-26
Zong Li
riscv: Add support to dump the kernel page tables
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-03-26
Zong Li
riscv: patch code by fixmap mapping
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-03-26
Zong Li
riscv: introduce interfaces to patch kernel code
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-03-26
Zong Li
riscv: add macro to get instruction length
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-03-26
Zong Li
riscv: add STRICT_KERNEL_RWX support
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-03-26
Zong Li
riscv: add alignment for text, rodata and data sections
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-03-26
Zong Li
riscv: move exception table immediately after RO_DATA
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-03-26
Zong Li
riscv: add ARCH_SUPPORTS_DEBUG_PAGEALLOC support
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-03-26
Zong Li
riscv: add ARCH_HAS_SET_DIRECT_MAP support
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-03-26
Zong Li
riscv: add ARCH_HAS_SET_MEMORY support
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-03-03
Zong Li
riscv: force hart_lottery to put in .sdata section
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-02-24
Zong Li
riscv: adjust the indent
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-02-24
Zong Li
riscv: allocate a complete page size for each page...
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-01-23
Zong Li
riscv: mm: add support for CONFIG_DEBUG_VIRTUAL
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-01-05
Zong Li
clocksource: riscv: add notrace to riscv_sched_clock
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-01-03
Zong Li
riscv: ftrace: correct the condition logic in function...
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-01-03
Zong Li
riscv: gcov: enable gcov for RISC-V
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2020-01-03
Zong Li
riscv: mm: use __pa_symbol for kernel symbols
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2019-11-12
Zong Li
riscv: clean up the macro format in each header file
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2019-11-12
Zong Li
riscv: Use PMD_SIZE to replace PTE_PARENT_SIZE
Signed-off-by:
Zong Li
<zong.li@sifive.com>
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2019-01-07
Zong Li
RISC-V: Support MODULE_SECTIONS mechanism on RV32
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-11-06
Zong Li
nds32: Fill all TLB entries with kernel image mapping
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-11-06
Zong Li
nds32: Remove the redundant assignment
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-10-23
Zong Li
RISC-V: Select GENERIC_LIB_UMODDI3 on RV32
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-10-23
Zong Li
lib: Add umoddi3 and udivmoddi4 of GCC library routines
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-10-23
Zong Li
RISC-V: Use swiotlb on RV64 only
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-10-23
Zong Li
RISC-V: Build tishift only on 64-bit
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-09-04
Zong Li
nds32: Add macro definition for offset of lp register...
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-09-04
Zong Li
nds32: Remove the deprecated ABI implementation
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-09-04
Zong Li
nds32/stack: Get real return address by using ftrace_graph_r...
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-09-04
Zong Li
nds32/ftrace: Support dynamic function graph tracer
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-09-04
Zong Li
nds32/ftrace: Support dynamic function tracer
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-09-04
Zong Li
nds32/ftrace: Add RECORD_MCOUNT support
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-09-04
Zong Li
nds32/ftrace: Support static function graph tracer
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-09-04
Zong Li
nds32/ftrace: Support static function tracer
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-09-04
Zong Li
nds32: Extract the checking and getting pointer to...
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-09-04
Zong Li
nds32: Clean up the coding style
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-09-04
Zong Li
nds32: Fix get_user/put_user macro expand pointer problem
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-09-04
Zong Li
nds32: Fix empty call trace
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-08-13
Zong Li
net: Change the layout of structure trace_event_raw_fib_tabl...
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-08-13
Zong Li
RISC-V: Add the directive for alignment of stvec's...
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-07-04
Zong Li
RISC-V: Change variable type for 32-bit compatible
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-07-04
Zong Li
RISC-V: Add definiion of extract symbol's index and...
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-07-04
Zong Li
RISC-V: Select GENERIC_UCMPDI2 on RV32I
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-07-04
Zong Li
RISC-V: Add conditional macro for zone of DMA32
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-04-03
Zong Li
RISC-V: Add definition of relocation types
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-04-03
Zong Li
RISC-V: Enable module support in defconfig
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-04-03
Zong Li
RISC-V: Support SUB32 relocation type in kernel module
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-04-03
Zong Li
RISC-V: Support ADD32 relocation type in kernel module
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-04-03
Zong Li
RISC-V: Support ALIGN relocation type in kernel module
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-04-03
Zong Li
RISC-V: Support RVC_BRANCH/JUMP relocation type in...
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-04-03
Zong Li
RISC-V: Support HI20/LO12_I/LO12_S relocation type...
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-04-03
Zong Li
RISC-V: Support CALL relocation type in kernel module
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-04-03
Zong Li
RISC-V: Support GOT_HI20/CALL_PLT relocation type in...
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-04-03
Zong Li
RISC-V: Add section of GOT.PLT for kernel module
Signed-off-by:
Zong Li
<zong@andestech.com>
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2018-04-03
Zong Li
RISC-V: Add sections of PLT and GOT for kernel module
Signed-off-by:
Zong Li
<zong@andestech.com>
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