From 7e10d91d96d4b9b51f4b43b8105a4a7ee04c157a Mon Sep 17 00:00:00 2001 From: Som Qin Date: Wed, 30 Aug 2023 14:10:50 +0800 Subject: [PATCH 01/16] Medis:wave5: Remove inexistent including File sifive_l2_cache.h is inexistent in sdk 6.1 version. Signed-off-by: Som Qin [sw0312.kim: cherry-pick the commit ed137a80cd88 from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_6.1.y_devel - Change sifive cache flush function name properly] Signed-off-by: Seung-Woo Kim Change-Id: Id9d63d72fab1ab0ddeecdb46aeaa19cb0045ed36 --- drivers/media/platform/chips-media/wave5/wave5-vdi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vdi.c b/drivers/media/platform/chips-media/wave5/wave5-vdi.c index 4a0e4b8..9301dd2 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vdi.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vdi.c @@ -10,11 +10,11 @@ #include "wave5-vpu.h" #include "wave5-regdefine.h" #include + #ifdef CONFIG_SIFIVE_FLUSH -#include +extern void sifive_flush64_range(unsigned long start, unsigned long len); #endif - #define VDI_SYSTEM_ENDIAN VDI_LITTLE_ENDIAN #define VDI_128BIT_BUS_SYSTEM_ENDIAN VDI_128BIT_LITTLE_ENDIAN -- 2.7.4 From fdab41d2cec76e75fc65dbddb31ee32e022c8078 Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Thu, 8 Jun 2023 16:01:33 +0800 Subject: [PATCH 02/16] riscv: dts: starfive: jh7110: Add vpu/jpu nodes Add vpu/jpu nodes for jh7110 SOC Signed-off-by: Samin Guo [sw0312.kim: port the commit e2d1cdfe5ff5 from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_6.1.y_devel - Port upstream jh7110 clk and sys-reset controller macro name] Signed-off-by: Seung-Woo Kim Change-Id: Iae673d805d9549ba96f3c08ee93ea69148f68e1e --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 64 ++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index b3fa383..c66f130 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -996,6 +996,70 @@ status = "disabled"; }; + jpu: jpu@13090000 { + compatible = "starfive,jpu"; + reg = <0x0 0x13090000 0x0 0x300>; + interrupts = <14>; + clocks = <&syscrg JH7110_SYSCLK_CODAJ12_AXI>, + <&syscrg JH7110_SYSCLK_CODAJ12_CORE>, + <&syscrg JH7110_SYSCLK_CODAJ12_APB>, + <&syscrg JH7110_SYSCLK_NOC_BUS_VDEC_AXI>; + clock-names = "axi_clk", "core_clk", + "apb_clk", "noc_bus"; + resets = <&syscrg JH7110_SYSRST_CODAJ12_AXI>, + <&syscrg JH7110_SYSRST_CODAJ12_CORE>, + <&syscrg JH7110_SYSRST_CODAJ12_APB>; + reset-names = "rst_axi", "rst_core", "rst_apb"; + power-domains = <&pwrc JH7110_PD_VDEC>; + status = "disabled"; + }; + + vpu_dec: vpu_dec@130A0000 { + compatible = "starfive,vdec"; + reg = <0x0 0x130A0000 0x0 0x10000>; + interrupts = <13>; + clocks = <&syscrg JH7110_SYSCLK_WAVE511_AXI>, + <&syscrg JH7110_SYSCLK_WAVE511_BPU>, + <&syscrg JH7110_SYSCLK_WAVE511_VCE>, + <&syscrg JH7110_SYSCLK_WAVE511_APB>, + <&syscrg JH7110_SYSCLK_NOC_BUS_VDEC_AXI>; + clock-names = "axi_clk", "bpu_clk", "vce_clk", + "apb_clk", "noc_bus"; + resets = <&syscrg JH7110_SYSRST_WAVE511_AXI>, + <&syscrg JH7110_SYSRST_WAVE511_BPU>, + <&syscrg JH7110_SYSRST_WAVE511_VCE>, + <&syscrg JH7110_SYSRST_WAVE511_APB>, + <&syscrg JH7110_SYSRST_AXIMEM0_AXI>; + reset-names = "rst_axi", "rst_bpu", "rst_vce", + "rst_apb", "rst_sram"; + starfive,vdec_noc_ctrl; + power-domains = <&pwrc JH7110_PD_VDEC>; + status = "disabled"; + }; + + vpu_enc: vpu_enc@130B0000 { + compatible = "starfive,venc"; + reg = <0x0 0x130B0000 0x0 0x10000>; + interrupts = <15>; + clocks = <&syscrg JH7110_SYSCLK_VENC_AXI>, + <&syscrg JH7110_SYSCLK_WAVE420L_BPU>, + <&syscrg JH7110_SYSCLK_WAVE420L_VCE>, + <&syscrg JH7110_SYSCLK_WAVE420L_APB>, + <&syscrg JH7110_SYSCLK_NOC_BUS_VENC_AXI>; + clock-names = "axi_clk", "bpu_clk", "vce_clk", + "apb_clk", "noc_bus"; + resets = <&syscrg JH7110_SYSRST_WAVE420L_AXI>, + <&syscrg JH7110_SYSRST_WAVE420L_BPU>, + <&syscrg JH7110_SYSRST_WAVE420L_VCE>, + <&syscrg JH7110_SYSRST_WAVE420L_APB>, + <&syscrg JH7110_SYSRST_AXIMEM1_AXI>; + reset-names = "rst_axi", "rst_bpu", "rst_vce", + "rst_apb", "rst_sram"; + starfive,venc_noc_ctrl; + power-domains = <&pwrc JH7110_PD_VENC>; + status = "disabled"; + }; + dma: dma-controller@16050000 { compatible = "starfive,jh7110-axi-dma"; reg = <0x0 0x16050000 0x0 0x10000>; -- 2.7.4 From a0668cbec05e6403fd028c9bfe813e66a9edff68 Mon Sep 17 00:00:00 2001 From: Samin Guo Date: Wed, 23 Aug 2023 10:43:54 +0800 Subject: [PATCH 03/16] riscv: dts: starfive: jh7110: add dma-coherent for vpu/jpu Use DMA-Coherent to avoid DIRECT_REMAP when allocating DMA buffers Signed-off-by: Samin Guo [sw0312.kim: cherry-pick the commit dfb44f0122ba from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_6.1.y_devel] Signed-off-by: Seung-Woo Kim Change-Id: Ia0d3955010e963c0fb635e10081c1a2ab31155d4 --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index c66f130..d24ed3b 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -998,6 +998,7 @@ jpu: jpu@13090000 { compatible = "starfive,jpu"; + dma-coherent; reg = <0x0 0x13090000 0x0 0x300>; interrupts = <14>; clocks = <&syscrg JH7110_SYSCLK_CODAJ12_AXI>, @@ -1016,6 +1017,7 @@ vpu_dec: vpu_dec@130A0000 { compatible = "starfive,vdec"; + dma-coherent; reg = <0x0 0x130A0000 0x0 0x10000>; interrupts = <13>; clocks = <&syscrg JH7110_SYSCLK_WAVE511_AXI>, @@ -1039,6 +1041,7 @@ vpu_enc: vpu_enc@130B0000 { compatible = "starfive,venc"; + dma-coherent; reg = <0x0 0x130B0000 0x0 0x10000>; interrupts = <15>; clocks = <&syscrg JH7110_SYSCLK_VENC_AXI>, -- 2.7.4 From c2bb0d4501e1e8cd0fd998d0bebca93c5541770f Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Thu, 5 Oct 2023 16:23:01 +0900 Subject: [PATCH 04/16] RISCV: dts: starfive: enable jpg, vpu_dec and vpu_enc nodes in visionfive-2 To support video codec, wave vpu, enable related jpg, vpu_dec and vpu_enc nodes in visionfive-2. NOTE: Only wave511 vpu_dec is supported with wave video codec driver because visionfive-2 vpu_enc wave420 is different from currently supported wave521 by the driver. Change-Id: Icdd828ce35c98eee9a90a82c69c13614e53bb970 Signed-off-by: Seung-Woo Kim --- .../boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 3968ed7..c9a2854 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -177,6 +177,18 @@ status = "okay"; }; +&jpu { + status = "okay"; +}; + +&vpu_dec { + status = "okay"; +}; + +&vpu_enc { + status = "okay"; +}; + &i2c0 { clock-frequency = <100000>; i2c-sda-hold-time-ns = <300>; -- 2.7.4 From 4d11a7f1a19685d3e3fc8144f89e0f90d847c3e2 Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Thu, 5 Oct 2023 16:25:42 +0900 Subject: [PATCH 05/16] RISCV: config: enable wave511 video codec driver as module Enable wave511 video codec driver as module and also enable all depending configs. Change-Id: I0aeb0dfc0a844a3cc17c5054df61454c3f88e5fb Signed-off-by: Seung-Woo Kim --- arch/riscv/configs/tizen_visionfive2_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig index 75b2978..64c8e23 100644 --- a/arch/riscv/configs/tizen_visionfive2_defconfig +++ b/arch/riscv/configs/tizen_visionfive2_defconfig @@ -286,10 +286,14 @@ CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_SUPPORT_FILTER=y # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_GSPCA=m CONFIG_USB_GSPCA_ZC3XX=m CONFIG_USB_VIDEO_CLASS=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_WAVE_VPU=m CONFIG_DRM_I2C_CH7006=m CONFIG_DRM_I2C_SIL164=m CONFIG_DRM_VERISILICON=y -- 2.7.4 From 08f25a8ce13ded477f699bb5018b3cfa08180da5 Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Fri, 6 Oct 2023 16:00:09 +0900 Subject: [PATCH 06/16] clk: starfive: jh7110-sys: Set vdec_main and vdec_jpg as CLK_IGNORE_UNUSED To support video codec, set vdec_main and vdec_jpg clocks as CLK_IGNORE_UNUSED. Change-Id: I7df722cc20956d4cff68f856d0c7bf8c73fa36e7 Ref: https://github.com/starfive-tech/linux/blob/JH7110_VisionFive2_6.1.y_devel/drivers/clk/starfive/clk-starfive-jh7110-sys.c Signed-off-by: Seung-Woo Kim --- drivers/clk/starfive/clk-starfive-jh7110-sys.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c index adeca21..f69db175 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -139,8 +139,8 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = { JH71X0_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT), JH71X0_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT), JH71X0_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", 0, JH7110_SYSCLK_JPEGC_AXI), - JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", 0, JH7110_SYSCLK_VDEC_AXI), + JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", CLK_IGNORE_UNUSED, JH7110_SYSCLK_JPEGC_AXI), + JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", CLK_IGNORE_UNUSED, JH7110_SYSCLK_VDEC_AXI), JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0, JH7110_SYSCLK_VDEC_AXI), /* venc */ JH71X0__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT), -- 2.7.4 From d42faaa3ee0d046412273060995294f73b077fc6 Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Fri, 6 Oct 2023 19:04:06 +0900 Subject: [PATCH 07/16] media: chips-media: wave511: Fix null deference in wave5_vpu_dec_clr_disp_flag() If wave5_vpu_dec_open() is not called before calling wave5_vpu_dec_clr_disp_flag(), there is null deference. Fix the null deference by checking codec_info. Change-Id: I1a4d9a75681df293e1f67dd4338c6f770d789223 Signed-off-by: Seung-Woo Kim --- drivers/media/platform/chips-media/wave5/wave5-vpuapi.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c index 5a0078a..4e38a4d 100644 --- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c +++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c @@ -625,10 +625,14 @@ err_out: int wave5_vpu_dec_clr_disp_flag(struct vpu_instance *inst, int index) { - struct dec_info *p_dec_info = &inst->codec_info->dec_info; + struct dec_info *p_dec_info; int ret = 0; struct vpu_device *vpu_dev = inst->dev; + if (!inst->codec_info) + return -EINVAL; + + p_dec_info = &inst->codec_info->dec_info; if (index >= p_dec_info->num_of_display_fbs) return -EINVAL; -- 2.7.4 From abb9c7cd8f51d92d4c5d7d9fec95bcea46f991f3 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=C5=81ukasz=20Stelmach?= Date: Fri, 20 Oct 2023 14:03:05 +0200 Subject: [PATCH 08/16] RISCV: config: Enable configurations relevant to F2FS MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Enable configurations relevant to F2FS. Tizen is using F2FS filesystem on Headed image. Change-Id: Ifb1eef43a774fd6f1424dc3eb14261d80cf850bb Signed-off-by: Łukasz Stelmach --- arch/riscv/configs/tizen_qemu_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/tizen_qemu_defconfig b/arch/riscv/configs/tizen_qemu_defconfig index adc85d9..2881287 100644 --- a/arch/riscv/configs/tizen_qemu_defconfig +++ b/arch/riscv/configs/tizen_qemu_defconfig @@ -97,6 +97,8 @@ CONFIG_RPMSG_VIRTIO=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y -- 2.7.4 From c8391ef4f10941e746e415e5a3c70aeaf2860936 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=C5=81ukasz=20Stelmach?= Date: Fri, 20 Oct 2023 14:26:02 +0200 Subject: [PATCH 09/16] RISCV: configs: enable FUSE_FS configuration MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Enable CONFIG_FUSE_FS configs and other missed configs. Change-Id: I83c54355c8e7ad2ea95aadcab9bd6adad988d7eb Signed-off-by: Łukasz Stelmach --- arch/riscv/configs/tizen_qemu_defconfig | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/riscv/configs/tizen_qemu_defconfig b/arch/riscv/configs/tizen_qemu_defconfig index 2881287..bfa8edc 100644 --- a/arch/riscv/configs/tizen_qemu_defconfig +++ b/arch/riscv/configs/tizen_qemu_defconfig @@ -50,6 +50,9 @@ CONFIG_SCSI_VIRTIO=y CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=m CONFIG_NETDEVICES=y CONFIG_VIRTIO_NET=y CONFIG_MACB=y @@ -63,6 +66,8 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_HVC_RISCV_SBI=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y @@ -73,8 +78,8 @@ CONFIG_GPIO_SIFIVE=y # CONFIG_PTP_1588_CLOCK is not set CONFIG_POWER_RESET=y CONFIG_DRM=y -CONFIG_DRM_RADEON=y CONFIG_DRM_VIRTIO_GPU=y +CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -97,9 +102,13 @@ CONFIG_RPMSG_VIRTIO=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y +CONFIG_BTRFS_FS=y +CONFIG_BTRFS_FS_POSIX_ACL=y CONFIG_F2FS_FS=y CONFIG_F2FS_FS_SECURITY=y +CONFIG_FANOTIFY=y CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y -- 2.7.4 From 19a4d57769ed1845277f6ee35fe53f1ddbe380a0 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Wed, 8 Nov 2023 13:20:41 +0900 Subject: [PATCH 10/16] RISCV: dts: starfive: Add spidev node Add spidev driver node. This spi and spi_dev node was applied to the mainline. Refer to the patch below and apply it only to the spi_dev node. [https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi?h=v6.6&id=74fb20c8f05df7a7ea5c98ca85a713758e0e59f6] Change-Id: I05309739997f8bfbed61595e6fbc7e03e8944363 Signed-off-by: William Qiu Signed-off-by: Hoegeun Kwon --- arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index c9a2854..1a71179 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -266,6 +266,16 @@ status = "okay"; }; +&spi0 { + spi_dev0: spi@0 { + compatible = "rohm,dh2228fv"; + pl022,com-mode = <1>; + spi-max-frequency = <10000000>; + reg = <0>; + status = "okay"; + }; +}; + &pcie0 { pinctrl-names = "default"; reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; -- 2.7.4 From da9b3fb6016fee7010883c8a05626d60350c1cae Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Wed, 8 Nov 2023 13:22:52 +0900 Subject: [PATCH 11/16] RISCV: config: Enable spidev driver Enable SPIDEV driver. Change-Id: Ie5a938b7cda311350cb8b0a8f19e46b3c6384863 Signed-off-by: Hoegeun Kwon --- arch/riscv/configs/tizen_visionfive2_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig index 64c8e23..bf1ac17 100644 --- a/arch/riscv/configs/tizen_visionfive2_defconfig +++ b/arch/riscv/configs/tizen_visionfive2_defconfig @@ -274,6 +274,7 @@ CONFIG_SPI_MEM=y CONFIG_SPI_CADENCE_QUADSPI=y CONFIG_SPI_PL022_STARFIVE=y CONFIG_SPI_SIFIVE=y +CONFIG_SPI_SPIDEV=y # CONFIG_PTP_1588_CLOCK is not set CONFIG_GPIO_SIFIVE=y CONFIG_POWER_RESET_GPIO_RESTART=y -- 2.7.4 From fc37c58ab3ed881e91e60063ddf2621fa9b9ef4b Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Wed, 8 Nov 2023 13:32:06 +0900 Subject: [PATCH 12/16] RISCV: dts: starfive: Add eeprom node Add atmel eeprom driver node. Apply the eeprom node by referring to the Vendor branch. [https://github.com/starfive-tech/linux/blob/22e0315434b13cdde93ded101b567d5d1c4d5a2e/arch/riscv/boot/dts/starfive/jh7110-visionfive-v2.dtsi#L504] Change-Id: I830acf5a0b6a226a4822dd00a278aea6aee827d5 Signed-off-by: Hoegeun Kwon --- arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 1a71179..b109da9 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -218,6 +218,12 @@ pinctrl-0 = <&i2c5_pins>; status = "okay"; + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; + axp15060: pmic@36 { compatible = "x-powers,axp15060"; reg = <0x36>; -- 2.7.4 From bdf5931a13b2990cbd92d8a9c0c957d16591ba6f Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Wed, 8 Nov 2023 13:34:00 +0900 Subject: [PATCH 13/16] RISCV: config: Enable eeprom at24 Enable eeprom at24 driver. Change-Id: I3485a08f72ee1b20147a98c33440a27c4978bf02 Signed-off-by: Hoegeun Kwon --- arch/riscv/configs/tizen_visionfive2_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig index bf1ac17..875eeb5e 100644 --- a/arch/riscv/configs/tizen_visionfive2_defconfig +++ b/arch/riscv/configs/tizen_visionfive2_defconfig @@ -211,6 +211,7 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=32768 CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_NVME=m +CONFIG_EEPROM_AT24=y CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y CONFIG_SCSI_VIRTIO=y -- 2.7.4 From 7a5856d3bf3b896f9830cd55622dc3e4b6241939 Mon Sep 17 00:00:00 2001 From: "shanlong.li" Date: Thu, 8 Jun 2023 00:07:15 -0700 Subject: [PATCH 14/16] driver:mailbox: add mailbox driver add mailbox driver Signed-off-by: shanlong.li [hoegeun.kwon: cherry-pick the commit a070a8d2467d from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_6.1.y_devel] Signed-off-by: Hoegeun Kwon Change-Id: Iedb770bbdc8ec148c1b7eebf48df3b0e273063f6 --- drivers/mailbox/Kconfig | 13 + drivers/mailbox/Makefile | 4 + drivers/mailbox/starfive_mailbox-test.c | 407 ++++++++++++++++++++++++++++++++ drivers/mailbox/starfive_mailbox.c | 347 +++++++++++++++++++++++++++ 4 files changed, 771 insertions(+) create mode 100644 drivers/mailbox/starfive_mailbox-test.c create mode 100644 drivers/mailbox/starfive_mailbox.c diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 05d6fae..e272ece 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -294,4 +294,17 @@ config QCOM_IPCC acts as an interrupt controller for receiving interrupts from clients. Say Y here if you want to build this driver. +config STARFIVE_MBOX + tristate "Platform Starfive Mailbox" + depends on OF + help + Say Y here if you want to build a platform specific variant RISCV + controller driver. + +config STARFIVE_MBOX_TEST + tristate "Starfive Mailbox Test Client" + depends on OF + depends on HAS_IOMEM + help + Test client to help with testing new Controller driver implementations. endif diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index fc93761..f5ff98b 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -62,3 +62,7 @@ obj-$(CONFIG_SPRD_MBOX) += sprd-mailbox.o obj-$(CONFIG_QCOM_IPCC) += qcom-ipcc.o obj-$(CONFIG_APPLE_MAILBOX) += apple-mailbox.o + +obj-$(CONFIG_STARFIVE_MBOX) += starfive_mailbox.o + +obj-$(CONFIG_STARFIVE_MBOX_TEST) += starfive_mailbox-test.o diff --git a/drivers/mailbox/starfive_mailbox-test.c b/drivers/mailbox/starfive_mailbox-test.c new file mode 100644 index 0000000..4da8664 --- /dev/null +++ b/drivers/mailbox/starfive_mailbox-test.c @@ -0,0 +1,407 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2015 ST Microelectronics + * + * Author: Lee Jones + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define MBOX_MAX_SIG_LEN 8 +#define MBOX_MAX_MSG_LEN 16 +#define MBOX_BYTES_PER_LINE 16 +#define MBOX_HEXDUMP_LINE_LEN ((MBOX_BYTES_PER_LINE * 4) + 2) +#define MBOX_HEXDUMP_MAX_LEN (MBOX_HEXDUMP_LINE_LEN * (MBOX_MAX_MSG_LEN / MBOX_BYTES_PER_LINE)) + +static bool mbox_data_ready; + +struct mbox_test_device { + struct device *dev; + void __iomem *tx_mmio; + void __iomem *rx_mmio; + struct mbox_chan *tx_channel; + struct mbox_chan *rx_channel; + char *rx_buffer; + char *signal; + char *message; + spinlock_t lock; + wait_queue_head_t waitq; + struct fasync_struct *async_queue; + struct dentry *root_debugfs_dir; +}; + +static ssize_t mbox_test_signal_write(struct file *filp, + const char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct mbox_test_device *tdev = filp->private_data; + + if (!tdev->tx_channel) { + dev_err(tdev->dev, "Channel cannot do Tx\n"); + return -EINVAL; + } + + if (count > MBOX_MAX_SIG_LEN) { + dev_err(tdev->dev, + "Signal length %zd greater than max allowed %d\n", + count, MBOX_MAX_SIG_LEN); + return -EINVAL; + } + + /* Only allocate memory if we need to */ + if (!tdev->signal) { + tdev->signal = kzalloc(MBOX_MAX_SIG_LEN, GFP_KERNEL); + if (!tdev->signal) + return -ENOMEM; + } + + if (copy_from_user(tdev->signal, userbuf, count)) { + kfree(tdev->signal); + tdev->signal = NULL; + return -EFAULT; + } + + return count; +} + +static const struct file_operations mbox_test_signal_ops = { + .write = mbox_test_signal_write, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static int mbox_test_message_fasync(int fd, struct file *filp, int on) +{ + struct mbox_test_device *tdev = filp->private_data; + + return fasync_helper(fd, filp, on, &tdev->async_queue); +} + +static ssize_t mbox_test_message_write(struct file *filp, + const char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct mbox_test_device *tdev = filp->private_data; + void *data; + int ret; + + if (!tdev->tx_channel) { + dev_err(tdev->dev, "Channel cannot do Tx\n"); + return -EINVAL; + } + + if (count > MBOX_MAX_MSG_LEN) { + dev_err(tdev->dev, + "Message length %zd greater than max allowed %d\n", + count, MBOX_MAX_MSG_LEN); + return -EINVAL; + } + + tdev->message = kzalloc(MBOX_MAX_MSG_LEN, GFP_KERNEL); + if (!tdev->message) + return -ENOMEM; + + ret = copy_from_user(tdev->message, userbuf, count); + if (ret) { + ret = -EFAULT; + goto out; + } + + if (tdev->tx_mmio && tdev->signal) { + print_hex_dump_bytes("Client: Sending: Signal: ", DUMP_PREFIX_ADDRESS, + tdev->signal, MBOX_MAX_SIG_LEN); + + data = tdev->signal; + } else + data = tdev->message; + + print_hex_dump_bytes("Client: Sending: Message: ", DUMP_PREFIX_ADDRESS, + tdev->message, MBOX_MAX_MSG_LEN); + + ret = mbox_send_message(tdev->tx_channel, data); + mbox_chan_txdone(tdev->tx_channel, ret); + if (ret < 0) + dev_err(tdev->dev, "Failed to send message via mailbox\n"); + +out: + kfree(tdev->signal); + kfree(tdev->message); + tdev->signal = NULL; + + return ret < 0 ? ret : count; +} + +static bool mbox_test_message_data_ready(struct mbox_test_device *tdev) +{ + bool data_ready; + unsigned long flags; + + spin_lock_irqsave(&tdev->lock, flags); + data_ready = mbox_data_ready; + spin_unlock_irqrestore(&tdev->lock, flags); + + return data_ready; +} + +static ssize_t mbox_test_message_read(struct file *filp, char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct mbox_test_device *tdev = filp->private_data; + unsigned long flags; + char *touser, *ptr; + int ret; + + touser = kzalloc(MBOX_HEXDUMP_MAX_LEN + 1, GFP_KERNEL); + if (!touser) + return -ENOMEM; + + if (!tdev->rx_channel) { + ret = snprintf(touser, 20, "\n"); + ret = simple_read_from_buffer(userbuf, count, ppos, + touser, ret); + goto kfree_err; + } + + do { + if (mbox_test_message_data_ready(tdev)) + break; + + if (filp->f_flags & O_NONBLOCK) { + ret = -EAGAIN; + goto waitq_err; + } + + if (signal_pending(current)) { + ret = -ERESTARTSYS; + goto waitq_err; + } + schedule(); + + } while (1); + + spin_lock_irqsave(&tdev->lock, flags); + + ptr = tdev->rx_buffer; + + mbox_data_ready = false; + + spin_unlock_irqrestore(&tdev->lock, flags); + if (copy_to_user((void __user *)userbuf, ptr, 4)) + ret = -EFAULT; + +waitq_err: + __set_current_state(TASK_RUNNING); +kfree_err: + kfree(touser); + return ret; +} + +static __poll_t +mbox_test_message_poll(struct file *filp, struct poll_table_struct *wait) +{ + struct mbox_test_device *tdev = filp->private_data; + + poll_wait(filp, &tdev->waitq, wait); + + if (mbox_test_message_data_ready(tdev)) + return EPOLLIN | EPOLLRDNORM; + return 0; +} + +static const struct file_operations mbox_test_message_ops = { + .write = mbox_test_message_write, + .read = mbox_test_message_read, + .fasync = mbox_test_message_fasync, + .poll = mbox_test_message_poll, + .open = simple_open, + .llseek = generic_file_llseek, +}; + +static int mbox_test_add_debugfs(struct platform_device *pdev, + struct mbox_test_device *tdev) +{ + if (!debugfs_initialized()) + return 0; + + tdev->root_debugfs_dir = debugfs_create_dir(dev_name(&pdev->dev), NULL); + if (!tdev->root_debugfs_dir) { + dev_err(&pdev->dev, "Failed to create Mailbox debugfs\n"); + return -EINVAL; + } + + debugfs_create_file("message", 0600, tdev->root_debugfs_dir, + tdev, &mbox_test_message_ops); + + debugfs_create_file("signal", 0200, tdev->root_debugfs_dir, + tdev, &mbox_test_signal_ops); + + return 0; +} + +static void mbox_test_receive_message(struct mbox_client *client, void *message) +{ + struct mbox_test_device *tdev = dev_get_drvdata(client->dev); + unsigned long flags; + + spin_lock_irqsave(&tdev->lock, flags); + if (tdev->rx_mmio) { + memcpy_fromio(tdev->rx_buffer, tdev->rx_mmio, MBOX_MAX_MSG_LEN); + print_hex_dump_bytes("Client: Received [MMIO]: ", DUMP_PREFIX_ADDRESS, + tdev->rx_buffer, MBOX_MAX_MSG_LEN); + } else if (message) { + print_hex_dump_bytes("Client: Received [API]: ", DUMP_PREFIX_ADDRESS, + message, MBOX_MAX_MSG_LEN); + memcpy(tdev->rx_buffer, message, MBOX_MAX_MSG_LEN); + } + mbox_data_ready = true; + spin_unlock_irqrestore(&tdev->lock, flags); +} + +static void mbox_test_prepare_message(struct mbox_client *client, void *message) +{ + struct mbox_test_device *tdev = dev_get_drvdata(client->dev); + + if (tdev->tx_mmio) { + if (tdev->signal) + memcpy_toio(tdev->tx_mmio, tdev->message, MBOX_MAX_MSG_LEN); + else + memcpy_toio(tdev->tx_mmio, message, MBOX_MAX_MSG_LEN); + } +} + +static struct mbox_chan * +mbox_test_request_channel(struct platform_device *pdev, const char *name) +{ + struct mbox_client *client; + struct mbox_chan *channel; + + client = devm_kzalloc(&pdev->dev, sizeof(*client), GFP_KERNEL); + if (!client) + return ERR_PTR(-ENOMEM); + + client->dev = &pdev->dev; + client->rx_callback = mbox_test_receive_message; + client->tx_prepare = mbox_test_prepare_message; + client->tx_block = false; + client->knows_txdone = false; + client->tx_tout = 500; + + channel = mbox_request_channel_byname(client, name); + if (IS_ERR(channel)) { + dev_warn(&pdev->dev, "Failed to request %s channel\n", name); + return NULL; + } + + return channel; +} + +static int mbox_test_probe(struct platform_device *pdev) +{ + struct mbox_test_device *tdev; + struct resource *res; + resource_size_t size; + int ret; + + tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL); + if (!tdev) + return -ENOMEM; + + /* It's okay for MMIO to be NULL */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + tdev->tx_mmio = devm_ioremap_resource(&pdev->dev, res); + if (PTR_ERR(tdev->tx_mmio) == -EBUSY) { + /* if reserved area in SRAM, try just ioremap */ + size = resource_size(res); + tdev->tx_mmio = devm_ioremap(&pdev->dev, res->start, size); + } else if (IS_ERR(tdev->tx_mmio)) { + tdev->tx_mmio = NULL; + } + + /* If specified, second reg entry is Rx MMIO */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + tdev->rx_mmio = devm_ioremap_resource(&pdev->dev, res); + if (PTR_ERR(tdev->rx_mmio) == -EBUSY) { + size = resource_size(res); + tdev->rx_mmio = devm_ioremap(&pdev->dev, res->start, size); + } else if (IS_ERR(tdev->rx_mmio)) { + tdev->rx_mmio = tdev->tx_mmio; + } + + tdev->tx_channel = mbox_test_request_channel(pdev, "tx"); + tdev->rx_channel = mbox_test_request_channel(pdev, "rx"); + + if (!tdev->tx_channel && !tdev->rx_channel) + return -EPROBE_DEFER; + + /* If Rx is not specified but has Rx MMIO, then Rx = Tx */ + if (!tdev->rx_channel && (tdev->rx_mmio != tdev->tx_mmio)) + tdev->rx_channel = tdev->tx_channel; + + tdev->dev = &pdev->dev; + platform_set_drvdata(pdev, tdev); + + spin_lock_init(&tdev->lock); + + if (tdev->rx_channel) { + tdev->rx_buffer = devm_kzalloc(&pdev->dev, + MBOX_MAX_MSG_LEN, GFP_KERNEL); + if (!tdev->rx_buffer) + return -ENOMEM; + } + + ret = mbox_test_add_debugfs(pdev, tdev); + if (ret) + return ret; + + dev_info(&pdev->dev, "Successfully registered\n"); + + return 0; +} + +static int mbox_test_remove(struct platform_device *pdev) +{ + struct mbox_test_device *tdev = platform_get_drvdata(pdev); + + debugfs_remove_recursive(tdev->root_debugfs_dir); + + if (tdev->tx_channel) + mbox_free_channel(tdev->tx_channel); + if (tdev->rx_channel) + mbox_free_channel(tdev->rx_channel); + + return 0; +} + +static const struct of_device_id mbox_test_match[] = { + { .compatible = "starfive,mailbox-test" }, + {}, +}; +MODULE_DEVICE_TABLE(of, mbox_test_match); + +static struct platform_driver mbox_test_driver = { + .driver = { + .name = "mailbox_test", + .of_match_table = mbox_test_match, + }, + .probe = mbox_test_probe, + .remove = mbox_test_remove, +}; +module_platform_driver(mbox_test_driver); + +MODULE_DESCRIPTION("Generic Mailbox Testing Facility"); +MODULE_AUTHOR("Lee Jones + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mailbox.h" + +#define MBOX_CHAN_MAX 4 + +#define MBOX_BASE(mbox, ch) ((mbox)->base + ((ch) * 0x10)) +#define MBOX_IRQ_REG 0x00 +#define MBOX_SET_REG 0x04 +#define MBOX_CLR_REG 0x08 +#define MBOX_CMD_REG 0x0c +#define MBC_PEND_SMRY 0x100 + +typedef enum { + MAILBOX_CORE_U7 = 0, + MAILBOX_CORE_HIFI4, + MAILBOX_CORE_E2, + MAILBOX_CORE_RSVD0, + MAILBOX_CORE_NUM, +} mailbox_core_t; + +struct mailbox_irq_name_c{ + int id; + char name[16]; +}; + +static const struct mailbox_irq_name_c irq_peer_name[MBOX_CHAN_MAX] = { + {MAILBOX_CORE_U7, "u74_core"}, + {MAILBOX_CORE_HIFI4, "hifi4_core"}, + {MAILBOX_CORE_E2, "e24_core"}, + {MAILBOX_CORE_RSVD0, "" }, +}; + +/** + * starfive mailbox channel information + * + * A channel can be used for TX or RX, it can trigger remote + * processor interrupt to notify remote processor and can receive + * interrupt if has incoming message. + * + * @dst_irq: Interrupt vector for remote processor + * @core_id: id for remote processor + */ +struct starfive_chan_info { + unsigned int dst_irq; + mailbox_core_t core_id; +}; + +/** + * starfive mailbox controller data + * + * Mailbox controller includes 4 channels and can allocate + * channel for message transferring. + * + * @dev: Device to which it is attached + * @base: Base address of the register mapping region + * @chan: Representation of channels in mailbox controller + * @mchan: Representation of channel info + * @controller: Representation of a communication channel controller + */ +struct starfive_mbox { + struct device *dev; + void __iomem *base; + struct mbox_chan chan[MBOX_CHAN_MAX]; + struct starfive_chan_info mchan[MBOX_CHAN_MAX]; + struct mbox_controller controller; + struct clk *clk; + struct reset_control *rst_rresetn; +}; + +static struct starfive_mbox *to_starfive_mbox(struct mbox_controller *mbox) +{ + return container_of(mbox, struct starfive_mbox, controller); +} + +static struct mbox_chan * +starfive_of_mbox_index_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *sp) +{ + struct starfive_mbox *sbox; + + int ind = sp->args[0]; + int core_id = sp->args[1]; + + if (ind >= mbox->num_chans || core_id >= MAILBOX_CORE_NUM) + return ERR_PTR(-EINVAL); + + sbox = to_starfive_mbox(mbox); + + sbox->mchan[ind].core_id = core_id; + + return &mbox->chans[ind]; +} + +static irqreturn_t starfive_rx_irq_handler(int irq, void *p) +{ + struct mbox_chan *chan = p; + unsigned long ch = (unsigned long)chan->con_priv; + struct starfive_mbox *mbox = to_starfive_mbox(chan->mbox); + void __iomem *base = MBOX_BASE(mbox, ch); + u32 val; + + val = readl(base + MBOX_CMD_REG); + if (!val) + return IRQ_NONE; + + mbox_chan_received_data(chan, (void *)&val); + writel(val, base + MBOX_CLR_REG); + return IRQ_HANDLED; +} + +static int starfive_mbox_check_state(struct mbox_chan *chan) +{ + unsigned long ch = (unsigned long)chan->con_priv; + struct starfive_mbox *mbox = to_starfive_mbox(chan->mbox); + unsigned long irq_flag = IRQF_SHARED; + long ret = 0; + + pm_runtime_get_sync(mbox->dev); + /* MAILBOX should be with IRQF_NO_SUSPEND set */ + if (!mbox->dev->pm_domain) + irq_flag |= IRQF_NO_SUSPEND; + + /* Mailbox is idle so directly bail out */ + if (readl(mbox->base + MBC_PEND_SMRY) & BIT(ch)) + return -EBUSY; + + if (mbox->mchan[ch].dst_irq > 0) { + dev_dbg(mbox->dev, "%s: host IRQ = %d, ch:%ld", __func__, mbox->mchan[ch].dst_irq, ch); + ret = devm_request_irq(mbox->dev, mbox->mchan[ch].dst_irq, starfive_rx_irq_handler, + irq_flag, irq_peer_name[ch].name, chan); + if (ret < 0) + dev_err(mbox->dev, "request_irq %d failed\n", mbox->mchan[ch].dst_irq); + } + + return ret; +} + +static int starfive_mbox_startup(struct mbox_chan *chan) +{ + return starfive_mbox_check_state(chan); +} + +static void starfive_mbox_shutdown(struct mbox_chan *chan) +{ + struct starfive_mbox *mbox = to_starfive_mbox(chan->mbox); + unsigned long ch = (unsigned long)chan->con_priv; + void __iomem *base = MBOX_BASE(mbox, ch); + + writel(0x0, base + MBOX_IRQ_REG); + writel(0x0, base + MBOX_CLR_REG); + + if (mbox->mchan[ch].dst_irq > 0) + devm_free_irq(mbox->dev, mbox->mchan[ch].dst_irq, chan); + pm_runtime_put_sync(mbox->dev); +} + +static int starfive_mbox_send_data(struct mbox_chan *chan, void *msg) +{ + unsigned long ch = (unsigned long)chan->con_priv; + struct starfive_mbox *mbox = to_starfive_mbox(chan->mbox); + struct starfive_chan_info *mchan = &mbox->mchan[ch]; + void __iomem *base = MBOX_BASE(mbox, ch); + u32 *buf = msg; + + /* Ensure channel is released */ + if (readl(mbox->base + MBC_PEND_SMRY) & BIT(ch)) { + pr_debug("%s:%d. busy\n", __func__, __LINE__); + return -EBUSY; + } + + /* Clear mask for destination interrupt */ + writel(BIT(mchan->core_id), base + MBOX_IRQ_REG); + + /* Fill message data */ + writel(*buf, base + MBOX_SET_REG); + return 0; +} + +static struct mbox_chan_ops starfive_mbox_ops = { + .startup = starfive_mbox_startup, + .send_data = starfive_mbox_send_data, + .shutdown = starfive_mbox_shutdown, +}; + +static const struct of_device_id starfive_mbox_of_match[] = { + { .compatible = "starfive,mail_box",}, + {}, +}; + +MODULE_DEVICE_TABLE(of, starfive_mbox_of_match); + +void starfive_mailbox_init(struct starfive_mbox *mbox) +{ + mbox->clk = devm_clk_get_optional(mbox->dev, "clk_apb"); + if (IS_ERR(mbox->clk)) { + dev_err(mbox->dev, "failed to get mailbox\n"); + return; + } + + mbox->rst_rresetn = devm_reset_control_get_exclusive(mbox->dev, "mbx_rre"); + if (IS_ERR(mbox->rst_rresetn)) { + dev_err(mbox->dev, "failed to get mailbox reset\n"); + return; + } + + clk_prepare_enable(mbox->clk); + reset_control_deassert(mbox->rst_rresetn); +} + +static int starfive_mbox_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct starfive_mbox *mbox; + struct mbox_chan *chan; + struct resource *res; + unsigned long ch; + int err; + + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mbox->base = devm_ioremap_resource(dev, res); + mbox->dev = dev; + + if (IS_ERR(mbox->base)) + return PTR_ERR(mbox->base); + + starfive_mailbox_init(mbox); + + mbox->controller.dev = dev; + mbox->controller.chans = mbox->chan; + mbox->controller.num_chans = MBOX_CHAN_MAX; + mbox->controller.ops = &starfive_mbox_ops; + mbox->controller.of_xlate = starfive_of_mbox_index_xlate; + mbox->controller.txdone_irq = true; + mbox->controller.txdone_poll = false; + + /* Initialize mailbox channel data */ + chan = mbox->chan; + for (ch = 0; ch < MBOX_CHAN_MAX; ch++) { + mbox->mchan[ch].dst_irq = 0; + mbox->mchan[ch].core_id = (mailbox_core_t)ch; + chan[ch].con_priv = (void *)ch; + } + mbox->mchan[MAILBOX_CORE_HIFI4].dst_irq = platform_get_irq(pdev, 0); + mbox->mchan[MAILBOX_CORE_E2].dst_irq = platform_get_irq(pdev, 1); + + err = mbox_controller_register(&mbox->controller); + if (err) { + dev_err(dev, "Failed to register mailbox %d\n", err); + return err; + } + + platform_set_drvdata(pdev, mbox); + dev_info(dev, "Mailbox enabled\n"); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + return 0; +} + +static int starfive_mbox_remove(struct platform_device *pdev) +{ + struct starfive_mbox *mbox = platform_get_drvdata(pdev); + + mbox_controller_unregister(&mbox->controller); + devm_clk_put(mbox->dev, mbox->clk); + pm_runtime_disable(mbox->dev); + + return 0; +} + +static int __maybe_unused starfive_mbox_suspend(struct device *dev) +{ + struct starfive_mbox *mbox = dev_get_drvdata(dev); + + clk_disable_unprepare(mbox->clk); + + return 0; +} + +static int __maybe_unused starfive_mbox_resume(struct device *dev) +{ + struct starfive_mbox *mbox = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(mbox->clk); + if (ret) + dev_err(dev, "failed to enable clock\n"); + + return ret; +} + +static const struct dev_pm_ops starfive_mbox_pm_ops = { + .suspend = starfive_mbox_suspend, + .resume = starfive_mbox_resume, + SET_RUNTIME_PM_OPS(starfive_mbox_suspend, starfive_mbox_resume, NULL) +}; +static struct platform_driver starfive_mbox_driver = { + .probe = starfive_mbox_probe, + .remove = starfive_mbox_remove, + .driver = { + .name = "mailbox", + .of_match_table = starfive_mbox_of_match, + .pm = &starfive_mbox_pm_ops, + }, +}; + +static int __init starfive_mbox_init(void) +{ + return platform_driver_register(&starfive_mbox_driver); +} +core_initcall(starfive_mbox_init); + +static void __exit starfive_mbox_exit(void) +{ + platform_driver_unregister(&starfive_mbox_driver); +} +module_exit(starfive_mbox_exit); + +MODULE_DESCRIPTION("StarFive Mailbox Controller driver"); +MODULE_AUTHOR("Shanlong Li "); +MODULE_LICENSE("GPL"); -- 2.7.4 From 9c161009d67386c581f94d8a90e4b8ef3a7da593 Mon Sep 17 00:00:00 2001 From: "shanlong.li" Date: Fri, 10 Nov 2023 15:43:01 +0900 Subject: [PATCH 15/16] RISCV: dts: starfive: jh7110: Add mailbox node Add mailbox driver node. Signed-off-by: shanlong.li [hoegeun.kwon: cherry-pick the commit 802f9261f654 from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_6.1.y_devel] Signed-off-by: Hoegeun Kwon Change-Id: I8a3cf94272404a94bdf2fef05ecfb399417914d1 --- .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 19 +++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index b109da9..0abea4b 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -614,3 +614,11 @@ pinctrl-0 = <&pwmdac0_pins>; status = "okay"; }; + +&mailbox_contrl0 { + status = "okay"; +}; + +&mailbox_client0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index d24ed3b..e55e5b8 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -303,6 +303,13 @@ ports = <&dc_out>; }; + mailbox_client0: mailbox_client { + compatible = "starfive,mailbox-test"; + mbox-names = "rx", "tx"; + mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>; + status = "disabled"; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -833,6 +840,18 @@ "ch2", "ch3"; }; + mailbox_contrl0: mailbox@13060000 { + compatible = "starfive,mail_box"; + reg = <0x0 0x13060000 0x0 0x0001000>; + clocks = <&syscrg JH7110_SYSCLK_MAILBOX_APB>; + clock-names = "clk_apb"; + resets = <&syscrg JH7110_SYSRST_MAILBOX_APB>; + reset-names = "mbx_rre"; + interrupts = <26 27>; + #mbox-cells = <2>; + status = "disabled"; + }; + wdog: watchdog@13070000 { compatible = "starfive,jh7110-wdt"; reg = <0x0 0x13070000 0x0 0x10000>; -- 2.7.4 From 0d0eff1e3bdb86e83dc74137e64ca03fb9403b58 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Fri, 10 Nov 2023 15:56:46 +0900 Subject: [PATCH 16/16] RISCV: config: Enable starfive mailbox Enable starfive mailbox driver. Change-Id: If6f44164c2261bd7d18387e617a522c3251564fa Signed-off-by: Hoegeun Kwon --- arch/riscv/configs/tizen_visionfive2_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig index 875eeb5e..2aea5b9 100644 --- a/arch/riscv/configs/tizen_visionfive2_defconfig +++ b/arch/riscv/configs/tizen_visionfive2_defconfig @@ -353,6 +353,9 @@ CONFIG_CLK_STARFIVE_JH7110_AON=y CONFIG_CLK_STARFIVE_JH7110_STG=y CONFIG_CLK_STARFIVE_JH7110_ISP=y CONFIG_CLK_STARFIVE_JH7110_VOUT=y +CONFIG_MAILBOX=y +CONFIG_STARFIVE_MBOX=m +CONFIG_STARFIVE_MBOX_TEST=m CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_CTRL=y CONFIG_RPMSG_VIRTIO=y -- 2.7.4