From cddbe6a44246e49b0e0f8c87d746c95fc53e07a5 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Mon, 17 Jul 2023 18:06:27 +0900 Subject: [PATCH 01/16] gpu: drm: img: Fix to check fence list instead of fence count In order to generate a reserve fences, we check to see if there is a fence list instead of fence count. Change-Id: Ibd45c154610221dd7bcd4de96570fc00066457c8 Signed-off-by: Hoegeun Kwon --- .../gpu/drm/img/img-rogue/services/server/env/linux/pvr_buffer_sync.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/img/img-rogue/services/server/env/linux/pvr_buffer_sync.c b/drivers/gpu/drm/img/img-rogue/services/server/env/linux/pvr_buffer_sync.c index ab99301..ab6a5b2 100644 --- a/drivers/gpu/drm/img/img-rogue/services/server/env/linux/pvr_buffer_sync.c +++ b/drivers/gpu/drm/img/img-rogue/services/server/env/linux/pvr_buffer_sync.c @@ -234,7 +234,7 @@ pvr_buffer_sync_check_fences_create(struct pvr_fence_context *fence_ctx, exclusive = !!(pmr_flags[i] & PVR_BUFFER_FLAG_WRITE); - if (!fence_count) { + if (!resv->fences) { err = dma_resv_reserve_fences(resv, 1); if (err) goto err_destroy_fences; -- 2.7.4 From e318dd5d3e8f38910b4a61749c58d9992e717e97 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Mon, 17 Jul 2023 16:38:34 +0900 Subject: [PATCH 02/16] drm/verisilicon: Add cache flush feature when dmabuf sync Add cache flush for gem memory. Cache flushing is done when the dmabuf sync ioctl is called. Change-Id: I8663a391b18bb10f69007bd631fec492c0e347b2 Signed-off-by: Hoegeun Kwon --- drivers/gpu/drm/verisilicon/vs_gem.c | 52 ++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/gpu/drm/verisilicon/vs_gem.c b/drivers/gpu/drm/verisilicon/vs_gem.c index a8d1556..1a3f018 100644 --- a/drivers/gpu/drm/verisilicon/vs_gem.c +++ b/drivers/gpu/drm/verisilicon/vs_gem.c @@ -10,6 +10,10 @@ #include "vs_drv.h" #include "vs_gem.h" +#ifdef CONFIG_SIFIVE_FLUSH +#include +#endif + static const struct drm_gem_object_funcs vs_gem_default_funcs; static int vs_gem_alloc_buf(struct vs_gem_object *vs_obj) @@ -220,6 +224,43 @@ static int vs_gem_mmap_obj(struct drm_gem_object *obj, return ret; } +static int vs_gem_prime_end_cpu_access(struct dma_buf *buf, + enum dma_data_direction direction) +{ +#ifdef CONFIG_SIFIVE_FLUSH + struct drm_gem_object *obj = buf->priv; + struct vs_gem_object *vs_obj = to_vs_gem_object(obj); + + starfive_flush_dcache(vs_obj->dma_addr, vs_obj->size); +#endif + + return 0; +} + +static struct dma_buf_ops vs_gem_prime_dmabuf_ops = { + .cache_sgt_mapping = true, + .attach = drm_gem_map_attach, + .detach = drm_gem_map_detach, + .map_dma_buf = drm_gem_map_dma_buf, + .unmap_dma_buf = drm_gem_unmap_dma_buf, + .release = drm_gem_dmabuf_release, + .mmap = drm_gem_dmabuf_mmap, + .vmap = drm_gem_dmabuf_vmap, + .vunmap = drm_gem_dmabuf_vunmap, + .end_cpu_access = vs_gem_prime_end_cpu_access, +}; + +static struct dma_buf *vs_gem_prime_export(struct drm_gem_object *obj, int flags) +{ + struct dma_buf *dmabuf; + + dmabuf = drm_gem_prime_export(obj, flags); + if (!IS_ERR(dmabuf)) + dmabuf->ops = &vs_gem_prime_dmabuf_ops; + + return dmabuf; +} + struct sg_table *vs_gem_prime_get_sg_table(struct drm_gem_object *obj) { struct vs_gem_object *vs_obj = to_vs_gem_object(obj); @@ -252,6 +293,7 @@ static const struct vm_operations_struct vs_vm_ops = { static const struct drm_gem_object_funcs vs_gem_default_funcs = { .free = vs_gem_free_object, + .export = vs_gem_prime_export, .get_sg_table = vs_gem_prime_get_sg_table, .vmap = vs_gem_prime_vmap, .vunmap = vs_gem_prime_vunmap, @@ -280,6 +322,16 @@ int vs_gem_dumb_create(struct drm_file *file, struct drm_gem_object *vs_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf) { + struct drm_gem_object *obj; + + if (dma_buf->ops == &vs_gem_prime_dmabuf_ops) { + obj = dma_buf->priv; + if (obj->dev == dev) { + drm_gem_object_get(obj); + return obj; + } + } + return drm_gem_prime_import_dev(dev, dma_buf, to_dma_dev(dev)); } -- 2.7.4 From 7c34e2ea4586e926c0458d4bbe524db68f907f04 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Wed, 19 Jul 2023 06:58:59 +0900 Subject: [PATCH 03/16] build: Change module image size from 32M to 20M Change module image size from 32M to 20M. In ks file, partitions size is using to 20M. If created to 30M, it will be failed on build system. So to check correct size, change module image size to 20M. Change-Id: I89cb828269e15f2162febacaf2f22386849b0f22 Signed-off-by: Jaehoon Chung --- build.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build.sh b/build.sh index f66d4f8..3239bec 100755 --- a/build.sh +++ b/build.sh @@ -1,7 +1,7 @@ #!/bin/bash MOD_DIR="usr/tmp_mod" MOD_IMG="usr/modules.img" -MOD_SIZE=32 +MOD_SIZE=20 NCPUS=`grep ^processor /proc/cpuinfo | wc -l` NCPUS=$(($NCPUS * 2)) -- 2.7.4 From f58ab0cbdac47f571bc403d9808e2aed3253e876 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Mon, 26 Jun 2023 13:15:12 +0900 Subject: [PATCH 04/16] packaging: Update stable version to 6.1.39 Update stable version to 6.1.39. Change-Id: I0092fc745e6e968afa777d0fb409fc1f20d5e840 Signed-off-by: Jaehoon Chung --- packaging/linux-qemu.spec | 2 +- packaging/linux-riscv.spec.in | 2 +- packaging/linux-visionfive2.spec | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/packaging/linux-qemu.spec b/packaging/linux-qemu.spec index 9c6a982..5533e19 100644 --- a/packaging/linux-qemu.spec +++ b/packaging/linux-qemu.spec @@ -10,7 +10,7 @@ Name: %{variant}-linux-kernel Summary: The Linux Kernel for RISC-V %{target_board} -Version: 6.1.21 +Version: 6.1.39 Release: 0 License: GPL-2.0 ExclusiveArch: riscv64 diff --git a/packaging/linux-riscv.spec.in b/packaging/linux-riscv.spec.in index 13659a4..ea5ba6d 100644 --- a/packaging/linux-riscv.spec.in +++ b/packaging/linux-riscv.spec.in @@ -8,7 +8,7 @@ Name: %{variant}-linux-kernel Summary: The Linux Kernel for RISC-V %{target_board} -Version: 6.1.21 +Version: 6.1.39 Release: 0 License: GPL-2.0 ExclusiveArch: riscv64 diff --git a/packaging/linux-visionfive2.spec b/packaging/linux-visionfive2.spec index b2b4734..8bdec4c 100644 --- a/packaging/linux-visionfive2.spec +++ b/packaging/linux-visionfive2.spec @@ -10,7 +10,7 @@ Name: %{variant}-linux-kernel Summary: The Linux Kernel for RISC-V %{target_board} -Version: 6.1.32 +Version: 6.1.39 Release: 0 License: GPL-2.0 ExclusiveArch: riscv64 -- 2.7.4 From 44053e1eb3a522409564a59bd43f757520d069aa Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Wed, 26 Jul 2023 06:32:45 +0900 Subject: [PATCH 05/16] Revert "riscv: fix riscv64 unrecognized opcode build error" Since using gcc13 to build Tizen RISCV, this patch doesn't need anymore. This reverts commit e6c19c8fe08eb4375c7f5da1d7004ae4c533d615. Change-Id: Iea9421a0c53ac3f9a9d9a8942dbf5a1521b91665 --- arch/riscv/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 4114bda..3cb876f 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -55,7 +55,6 @@ endif riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd -riscv-march-y := $(subst imafd,g,$(riscv-march-y)) riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC -- 2.7.4 From a16ffa31a98812de35a1bd8b9c3a19d18e794b26 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Wed, 26 Jul 2023 10:50:50 +0900 Subject: [PATCH 06/16] gpu: drm: verisilicon: Fix potential Null pointer dereference It can be the poential NULL pointer dereference. [ 3.749753] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000008 [ 3.750873] starfive display-subsystem: bound 29400000.dc8200 (ops 0xffffffff812c3bc8) [ 3.758534] Oops [#1] [ 3.758538] Modules linked in: [ 3.758547] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 6.1.39-riscv-visionfive2 #1 [ 3.758555] Hardware name: StarFive VisionFive 2 v1.3B (DT) [ 3.758560] epc : dc_isr+0x22/0x60 [ 3.766483] innohdmi-starfive 29590000.hdmi: inno hdmi bind begin [ 3.768725] ra : dc_isr+0x22/0x60 [ 3.768734] epc : ffffffff806db7ee ra : ffffffff806db7ee sp : ffffffff81a03bf0 [ 3.768741] gp : ffffffff81c6a158 tp : ffffffff81a17900 t0 : 0000000000046000 [ 3.771834] innohdmi-starfive 29590000.hdmi: supply hdmi_1p8 not found, using dummy regulator Change-Id: I4a7c1f656f1d45c2fc183f2c2976a11e0b2816c1 Signed-off-by: Jaehoon Chung --- drivers/gpu/drm/verisilicon/vs_dc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisilicon/vs_dc.c index 12c09da..7c7b72c 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.c +++ b/drivers/gpu/drm/verisilicon/vs_dc.c @@ -806,6 +806,9 @@ static irqreturn_t dc_isr(int irq, void *data) struct vs_dc_info *dc_info = dc->hw.info; u32 i, ret; + if (!dc_info) + return IRQ_HANDLED; + ret = dc_hw_get_interrupt(&dc->hw); for (i = 0; i < dc_info->panel_num; i++) -- 2.7.4 From f8496c893debead6b5a75912946f048ed8c952a2 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Wed, 26 Jul 2023 20:32:55 +0900 Subject: [PATCH 07/16] soc: sifive: ccache: Add delay after flush Problems with cache flush at resolutions exceeding FUD and with inno hdmi driver. It runs a cache flush and requires a delay. So add delay after cache flush. Change-Id: Id8b1398dcce04851577912e6c1dfd4a2b580a043 Signed-off-by: Hoegeun Kwon --- drivers/soc/sifive/sifive_ccache.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 79de317..73c39c3 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -9,6 +9,9 @@ #define pr_fmt(fmt) "CCACHE: " fmt #include +#ifdef CONFIG_STARFIVE_INNO_HDMI +#include +#endif #include #include #include @@ -159,6 +162,13 @@ void sifive_flush64_range(unsigned long start, unsigned long len) writeq(line, ccache_base + SIFIVE_FLUSH64); mb(); } +#ifdef CONFIG_STARFIVE_INNO_HDMI + /* + * Problems with cache flush at resolutions exceeding FUD. + * It runs a cache flush and requires a delay. + */ + udelay(700); +#endif } EXPORT_SYMBOL_GPL(sifive_flush64_range); #endif -- 2.7.4 From 6a96d47eac5e1531e95fe461f6db12bb67ba3516 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Tue, 1 Aug 2023 11:30:40 +0900 Subject: [PATCH 08/16] drm/verisilicon: vs_dc: Fix to disable interrupt on probe There is a case where interrupt enable is set in decon req before decon probe is completed. There is a problem that a kernel panic occurs if an interrupt is executed before the decon is bound. Disable interrupts before registering interrupts. Also, irq generated when the interrupt state is disabled is ignored. Change-Id: I8b3571b006031c28349e1647f2d9a5c508ca6235 Signed-off-by: Hoegeun Kwon --- drivers/gpu/drm/verisilicon/vs_dc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisilicon/vs_dc.c index 7c7b72c..0928846 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.c +++ b/drivers/gpu/drm/verisilicon/vs_dc.c @@ -810,6 +810,8 @@ static irqreturn_t dc_isr(int irq, void *data) return IRQ_HANDLED; ret = dc_hw_get_interrupt(&dc->hw); + if (!ret) + return IRQ_HANDLED; for (i = 0; i < dc_info->panel_num; i++) vs_crtc_handle_vblank(&dc->crtc[i]->base, dc_hw_check_underflow(&dc->hw)); @@ -1017,6 +1019,8 @@ static int dc_probe(struct platform_device *pdev) return ret; } + dc_hw_enable_interrupt(&dc->hw, 0); + irq = platform_get_irq(pdev, 0); ret = devm_request_irq(dev, irq, dc_isr, 0, dev_name(dev), dc); -- 2.7.4 From 318060a046ba65f7086477ffa799a23fb63dc005 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=C5=81ukasz=20Stelmach?= Date: Tue, 1 Aug 2023 15:03:49 +0200 Subject: [PATCH 09/16] RISCV: config: Enable RAM and NBD block devices MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Devices are supported on VisionFive2. Enable them on QEMU to use the same boot procedures on both targets. Change-Id: I210141b471d718fec4286a7bb516751226756f96 Signed-off-by: Łukasz Stelmach --- arch/riscv/configs/tizen_qemu_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/configs/tizen_qemu_defconfig b/arch/riscv/configs/tizen_qemu_defconfig index 3b66a9b..7877275 100644 --- a/arch/riscv/configs/tizen_qemu_defconfig +++ b/arch/riscv/configs/tizen_qemu_defconfig @@ -39,6 +39,9 @@ CONFIG_PCI_HOST_GENERIC=y CONFIG_PCIE_XILINX=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=32768 CONFIG_BLK_DEV_LOOP=y CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_SD=y -- 2.7.4 From 0f92872fada68d75f031a9851e5ed76749fe6828 Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Thu, 3 Aug 2023 11:00:55 +0900 Subject: [PATCH 10/16] RISCV: config: Enable MEDIA_SUPPORT_FILTER and enable only usb camera configs Enable MEDIA_SUPPORT_FILTER to filter out unnecessary media configs and enable only usb camera configs including gspca module. Change-Id: Idcd217d10821467562a53a57c3783897b4363d5f Signed-off-by: Seung-Woo Kim --- arch/riscv/configs/tizen_visionfive2_defconfig | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig index 32d7896..78c452e 100644 --- a/arch/riscv/configs/tizen_visionfive2_defconfig +++ b/arch/riscv/configs/tizen_visionfive2_defconfig @@ -280,10 +280,14 @@ CONFIG_WATCHDOG=y CONFIG_MFD_AXP20X_I2C=y CONFIG_REGULATOR=y CONFIG_REGULATOR_AXP20X=y -# CONFIG_MEDIA_CEC_SUPPORT is not set CONFIG_MEDIA_SUPPORT=y -CONFIG_VIDEO_DEV=m -# CONFIG_CXD2880_SPI_DRV is not set +CONFIG_MEDIA_SUPPORT_FILTER=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_VIDEO_CLASS=y CONFIG_DRM_I2C_CH7006=m CONFIG_DRM_I2C_SIL164=m CONFIG_DRM_VERISILICON=y -- 2.7.4 From e750d985a70a0ceab8166131c39a73b962f91fd6 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Tue, 8 Aug 2023 14:18:43 +0900 Subject: [PATCH 11/16] RISCV: dts: starfive: Fix the property of memory Current is getting the memory size from devicetree node. Until supporting eeprom, it needs to use the memory node. After applied this patch, Visionfive2 is showing 8GiB. Change-Id: Ic96c2a7d373b9fccee830f3e34bbd9a2d6a3d6c3 Signed-off-by: Jaehoon Chung --- arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index d81366a..1a8db60 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -32,7 +32,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x0 0x40000000 0x1 0x0>; + reg = <0x0 0x40000000 0x2 0x0>; }; thermal-zones { -- 2.7.4 From 93bbef15eb5096b416b130444f6383e353dbd00f Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Wed, 9 Aug 2023 11:17:00 +0900 Subject: [PATCH 12/16] RISCV: dts: starfive: Increase CMA range from 512MB to 768MB In UHD resolution, there are many cases where alloc fail due to lack of CMA capacity. Increase CMA range to prevent cma_alloc failed. Change-Id: I6b0c355b773b08d09381e738329b986113982768 Signed-off-by: Hoegeun Kwon --- arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 1a8db60..3968ed7 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -71,9 +71,9 @@ linux,cma { compatible = "shared-dma-pool"; reusable; - size = <0x0 0x20000000>; + size = <0x0 0x30000000>; alignment = <0x0 0x1000>; - alloc-ranges = <0x0 0x80000000 0x0 0x20000000>; + alloc-ranges = <0x0 0x80000000 0x0 0x30000000>; linux,cma-default; }; }; -- 2.7.4 From 3e0e031f1d54b3f7b792f9c48aeb3ee3a8ca60ce Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 18 Aug 2023 13:19:55 +0900 Subject: [PATCH 13/16] clk: starfive: jh7110-sys: Set PLL0 rate to 1.5GHz Set PLL0 rate to 1.5GHz. Change the parent of cpu_root clock and the divider of cpu_core before setting. This patch is taken from patch that was posted on mailing. Signed-off-by: Xingyu Wu Reviewed-by: Hal Feng Change-Id: Ib418a6321555c045effcb0580e0c91d80a7a2043 Signed-off-by: Jaehoon Chung --- drivers/clk/starfive/clk-starfive-jh7110-sys.c | 48 +++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c index ab82a49..adeca21 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -335,6 +335,7 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) { struct jh71x0_clk_priv *priv; unsigned int idx; + struct clk *pllclk; int ret; priv = devm_kzalloc(&pdev->dev, @@ -409,7 +410,52 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) if (ret) return ret; - return jh7110_reset_controller_register(priv, "reset-sys", 0); + ret = jh7110_reset_controller_register(priv, "reset-sys", 0); + if (ret) + return ret; + + /* + * Set PLL0 rate to 1.5GHz + * In order to not affect the cpu when the PLL0 rate is changing, + * we need to switch the parent of cpu_root clock to osc clock first, + * and then switch back after setting the PLL0 rate. + */ + pllclk = clk_get(priv->dev, "pll0_out"); + if (!IS_ERR(pllclk)) { + struct clk *osc = clk_get(&pdev->dev, "osc"); + struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk; + struct clk *cpu_core = priv->reg[JH7110_SYSCLK_CPU_CORE].hw.clk; + + if (IS_ERR(osc)) { + clk_put(pllclk); + return PTR_ERR(osc); + } + + /* + * CPU need voltage regulation by CPUfreq if set 1.5GHz. + * So in this driver, cpu_core need to be set the divider to be 2 first + * and will be 750M after setting parent. + */ + ret = clk_set_rate(cpu_core, clk_get_rate(cpu_core) / 2); + if (ret) + goto failed_set; + + ret = clk_set_parent(cpu_root, osc); + if (ret) + goto failed_set; + + ret = clk_set_rate(pllclk, 1500000000); + if (ret) + goto failed_set; + + ret = clk_set_parent(cpu_root, pllclk); + +failed_set: + clk_put(pllclk); + clk_put(osc); + } + + return ret; } static const struct of_device_id jh7110_syscrg_match[] = { -- 2.7.4 From 9ed5b31605b1c53aa59576929edcb4176e403a73 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Fri, 18 Aug 2023 13:31:42 +0900 Subject: [PATCH 14/16] RISCV: configs: Change a default cpufreq governor to SCHEDUTIL Change a default cpufreq governor from ondemand to schedutil. Change-Id: I4d681ddbb0926e40fee8433f5f2924478c56fd0e Signed-off-by: Jaehoon Chung --- arch/riscv/configs/tizen_visionfive2_defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig index 78c452e..03fcd8d 100644 --- a/arch/riscv/configs/tizen_visionfive2_defconfig +++ b/arch/riscv/configs/tizen_visionfive2_defconfig @@ -36,11 +36,11 @@ CONFIG_PM=y CONFIG_CPU_IDLE=y CONFIG_CPU_FREQ=y CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPUFREQ_DT=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=m -- 2.7.4 From 11a8468c73f2db0f1b5da367936c52c6d9bc700e Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Fri, 18 Aug 2023 15:34:10 +0900 Subject: [PATCH 15/16] usb: cdns3-starfive: Add extcon usb gadget state with always connected Add extcon usb gadget state and set usb gadget state as connected. The cdns3-starfive usb c port in visionfive2 board only has usb d-/d+ lines and vbus and ground lines are used for power supply. Because of the H/W limitation, it is not possible to detect usb c port connected state. In Tizen, deviced configures usb gadget functions only with the usb connected state, so, to support usb gadget functionality, the usb state should be set. Change-Id: I3e3a25a726c7205b3d9a5fd96d8557562bfda81f Signed-off-by: Seung-Woo Kim --- drivers/usb/cdns3/Kconfig | 11 +++++++++++ drivers/usb/cdns3/cdns3-starfive.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig index 0a514b5..b139e66df 100644 --- a/drivers/usb/cdns3/Kconfig +++ b/drivers/usb/cdns3/Kconfig @@ -131,3 +131,14 @@ config USB_CDNSP_HOST standard XHCI driver. endif + +if USB_CDNS3_STARFIVE + +config USB_CDNS3_STARFIVE_EXTCON + bool "Extcon USB state support on Cadence USB3 of Starfive SoC" + depends on EXTCON + help + Say Y here to enable external connector event of the StarFive SoC + platforms that contain Cadence USB3 controller core. + +endif diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c index a99f98f..55ae4ac 100644 --- a/drivers/usb/cdns3/cdns3-starfive.c +++ b/drivers/usb/cdns3/cdns3-starfive.c @@ -19,6 +19,9 @@ #include #include #include +#if IS_ENABLED(CONFIG_USB_CDNS3_STARFIVE_EXTCON) +#include +#endif #include "core.h" #define USB_STRAP_HOST BIT(17) @@ -55,6 +58,9 @@ struct cdns_starfive { u32 stg_offset_328; u32 stg_offset_500; bool usb2_only; +#if IS_ENABLED(CONFIG_USB_CDNS3_STARFIVE_EXTCON) + struct extcon_dev *edev; +#endif }; static int cdns_mode_init(struct platform_device *pdev, @@ -163,11 +169,21 @@ err_clk_init: return ret; } +#if IS_ENABLED(CONFIG_USB_CDNS3_STARFIVE_EXTCON) +static const unsigned int supported_cable[] = { + EXTCON_USB, + EXTCON_NONE, +}; +#endif + static int cdns_starfive_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *node = pdev->dev.of_node; struct cdns_starfive *data; +#if IS_ENABLED(CONFIG_USB_CDNS3_STARFIVE_EXTCON) + struct extcon_dev *edev; +#endif unsigned int args[4]; const char *dr_mode; int ret; @@ -180,6 +196,21 @@ static int cdns_starfive_probe(struct platform_device *pdev) data->dev = dev; +#if IS_ENABLED(CONFIG_USB_CDNS3_STARFIVE_EXTCON) + edev = devm_extcon_dev_allocate(dev, supported_cable); + if (IS_ERR(edev)) + return PTR_ERR(edev); + + ret = devm_extcon_dev_register(dev, edev); + if (ret) + return ret; + + /* Set starfive cdns3 usb always connected because of hw limitation */ + extcon_set_state_sync(edev, EXTCON_USB, true); + + data->edev = edev; +#endif + data->stg_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, "starfive,stg-syscon", 4, args); -- 2.7.4 From 3bfec121f53962e327b501b80b32213bbf3c22eb Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Fri, 18 Aug 2023 18:58:29 +0900 Subject: [PATCH 16/16] RISCV: config: tizen_visionfive2: Enable USB_CDNS3_STARFIVE_EXTCON Enable CONFIG_USB_CDNS3_STARFIVE_EXTCON to suuport usb gadget functionality from Tizen. Change-Id: I2b0cd4e6c34ec6a30d9d41100876ab27d5733de2 Signed-off-by: Seung-Woo Kim --- arch/riscv/configs/tizen_visionfive2_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig index 03fcd8d..af3f603 100644 --- a/arch/riscv/configs/tizen_visionfive2_defconfig +++ b/arch/riscv/configs/tizen_visionfive2_defconfig @@ -322,6 +322,7 @@ CONFIG_USB_CDNS3=y CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y CONFIG_USB_CDNS3_STARFIVE=y +CONFIG_USB_CDNS3_STARFIVE_EXTCON=y CONFIG_USB_GADGET=y CONFIG_USB_CONFIGFS=y CONFIG_USB_CONFIGFS_MASS_STORAGE=y -- 2.7.4