From 5b5b09f98a57b6536c35af52518461670d2aae55 Mon Sep 17 00:00:00 2001
From: Som Qin <som.qin@starfivetech.com>
Date: Fri, 25 Aug 2023 16:13:01 +0800
Subject: [PATCH 01/16] Media: Wave5: Fix plane size mismatch

Signed-off-by: Som Qin <som.qin@starfivetech.com>

[sw0312.kim: cherry-pick the commit b4e474a223e8 from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_6.1.y_devel]
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>

Change-Id: If69aaf750c83daf21b57c459f576ee2200f9c40e
---
 .../media/platform/chips-media/wave5/wave5-hw.c    |  24 +--
 .../platform/chips-media/wave5/wave5-vpu-dec.c     | 181 +++++----------------
 .../platform/chips-media/wave5/wave5-vpuapi.h      |   1 -
 3 files changed, 47 insertions(+), 159 deletions(-)

diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c
index 57bbc38..fdc5c7e 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-hw.c
+++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c
@@ -729,7 +729,6 @@ int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_b
 	struct vpu_buf vb_buf;
 	u32 color_format = 0;
 	u32 pixel_order = 1;
-	u32 scale_en = 0;
 	u32 bwb_flag = (map_type == LINEAR_FRAME_MAP) ? 1 : 0;
 
 	cbcr_interleave = inst->cbcr_interleave;
@@ -831,15 +830,7 @@ int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_b
 				p_dec_info->vb_fbc_c_tbl[i] = vb_buf;
 			}
 		}
-
-		if ((init_info->pic_width - init_info->pic_crop_rect.right != inst->display_fmt.width) ||
-			init_info->pic_height - init_info->pic_crop_rect.bottom != inst->display_fmt.height) {
-			pic_size = (inst->display_fmt.width << 16) | (inst->display_fmt.height);
-			scale_en = 1;
-		} else {
-			pic_size = (init_info->pic_width << 16) | (init_info->pic_height);
-			scale_en = 0;
-		}
+		pic_size = (init_info->pic_width << 16) | (init_info->pic_height);
 
 		// allocate task_buffer
 		vb_buf.size = (p_dec_info->vlc_buf_size * VLC_BUF_NUM) +
@@ -855,14 +846,7 @@ int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_b
 			      p_dec_info->vb_task.daddr);
 		vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_buf.size);
 	} else {
-		if ((init_info->pic_width - init_info->pic_crop_rect.right != inst->display_fmt.width) ||
-			init_info->pic_height - init_info->pic_crop_rect.bottom != inst->display_fmt.height) {
-			pic_size = (inst->display_fmt.width << 16) | (inst->display_fmt.height);
-			scale_en = 1;
-		} else {
-			pic_size = (init_info->pic_width << 16) | (init_info->pic_height);
-			scale_en = 0;
-		}
+		pic_size = (init_info->pic_width << 16) | (init_info->pic_height);
 	}
 	dev_dbg(inst->dev->dev, "set pic_size 0x%x\n", pic_size);
 	endian = wave5_vdi_convert_endian(inst->dev, fb_arr[0].endian);
@@ -872,15 +856,13 @@ int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst, struct frame_b
 	color_format = 0;
 
 	reg_val =
-		(scale_en << 29) |
 		(bwb_flag << 28) |
 		(pixel_order << 23) | /* PIXEL ORDER in 128bit. first pixel in low address */
 		(yuv_format << 20) |
 		(color_format << 19) |
 		(nv21 << 17) |
 		(cbcr_interleave << 16) |
-		(scale_en ? inst->display_fmt.width : fb_arr[0].stride);
-		//inst->display_fmt.width;
+		(fb_arr[0].stride);
 	dev_dbg(inst->dev->dev, "set W5_COMMON_PIC_INFO 0x%x\n",reg_val);
 	vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, reg_val);
 
diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
index 5d10f3c..481273d 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
+++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
@@ -234,46 +234,6 @@ static void wave5_update_pix_fmt(struct v4l2_pix_format_mplane *pix_mp, unsigned
 	}
 }
 
-static void wave5_update_pix_fmt_r8(struct v4l2_pix_format_mplane *pix_mp, unsigned int width,
-				 unsigned int height)
-{
-	switch (pix_mp->pixelformat) {
-	case V4L2_PIX_FMT_YUV420:
-	case V4L2_PIX_FMT_NV12:
-	case V4L2_PIX_FMT_NV21:
-		pix_mp->width = round_up(width, 32);
-		pix_mp->height = round_up(height, 8);
-		pix_mp->plane_fmt[0].bytesperline = round_up(width, 32);
-		pix_mp->plane_fmt[0].sizeimage = width * height * 3 / 2;
-		break;
-	case V4L2_PIX_FMT_YUV420M:
-		pix_mp->width = round_up(width, 32);
-		pix_mp->height = round_up(height, 8);
-		pix_mp->plane_fmt[0].bytesperline = round_up(width, 32);
-		pix_mp->plane_fmt[0].sizeimage = width * height;
-		pix_mp->plane_fmt[1].bytesperline = round_up(width, 32) / 2;
-		pix_mp->plane_fmt[1].sizeimage = width * height / 4;
-		pix_mp->plane_fmt[2].bytesperline = round_up(width, 32) / 2;
-		pix_mp->plane_fmt[2].sizeimage = width * height / 4;
-		break;
-	case V4L2_PIX_FMT_NV12M:
-	case V4L2_PIX_FMT_NV21M:
-		pix_mp->width = round_up(width, 32);
-		pix_mp->height = round_up(height, 8);
-		pix_mp->plane_fmt[0].bytesperline = round_up(width, 32);
-		pix_mp->plane_fmt[0].sizeimage = width * height;
-		pix_mp->plane_fmt[1].bytesperline = round_up(width, 32);
-		pix_mp->plane_fmt[1].sizeimage = width * height / 2;
-		break;
-	default:
-		pix_mp->width = width;
-		pix_mp->height = height;
-		pix_mp->plane_fmt[0].bytesperline = 0;
-		pix_mp->plane_fmt[0].sizeimage = width * height;
-		break;
-	}
-}
-
 static void wave5_vpu_dec_start_decode(struct vpu_instance *inst)
 {
 	struct dec_param pic_param;
@@ -301,7 +261,6 @@ static void wave5_vpu_dec_start_decode(struct vpu_instance *inst)
 
 		src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx);
 		inst->state = VPU_INST_STATE_STOP;
-		//printk("%d wave5 state = %d\n",__LINE__, inst->state);
 		v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
 	}
 }
@@ -312,7 +271,6 @@ static void wave5_vpu_dec_stop_decode(struct vpu_instance *inst)
 	int ret;
 
 	inst->state = VPU_INST_STATE_STOP;
-	//printk("%d wave5 state = %d\n",__LINE__, inst->state);
 
 	ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0);
 	if (ret) {
@@ -337,6 +295,7 @@ static void wave5_vpu_dec_finish_decode(struct vpu_instance *inst)
 	struct dec_output_info dec_output_info;
 	int ret;
 	u32 irq_status;
+	u32 stride, height;
 
 	if (kfifo_out(&inst->irq_status, &irq_status, sizeof(int)))
 		wave5_vpu_clear_interrupt_ex(inst, irq_status);
@@ -357,8 +316,9 @@ static void wave5_vpu_dec_finish_decode(struct vpu_instance *inst)
 				v4l2_m2m_dst_buf_remove_by_idx(inst->v4l2_fh.m2m_ctx,
 							       dec_output_info.index_frame_display);
 
-			int stride = inst->display_fmt.width;
-			int height  =inst->display_fmt.height;
+			stride = dec_output_info.disp_frame.stride;
+			height = dec_output_info.disp_pic_height -
+				dec_output_info.rc_display.bottom;
 			dev_dbg(inst->dev->dev, "%s %d disp_pic_height %u rc_display.bottom %u\n",
 				__func__, __LINE__, dec_output_info.disp_pic_height, dec_output_info.rc_display.bottom);
 			dev_dbg(inst->dev->dev, "%s %d stride %u height %u num %d\n", __func__, __LINE__, stride, height,inst->dst_fmt.num_planes);
@@ -425,7 +385,6 @@ static void wave5_vpu_dec_finish_decode(struct vpu_instance *inst)
 			v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
 
 			inst->eos = TRUE;
-			//pr_err("wave5 queue event type: %d id: %d\n",vpu_event_eos.type, vpu_event_eos.id);
 			v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_eos);
 
 			v4l2_m2m_job_finish(inst->v4l2_m2m_dev, inst->v4l2_fh.m2m_ctx);
@@ -498,7 +457,7 @@ static int wave5_vpu_dec_try_fmt_cap(struct file *file, void *fh, struct v4l2_fo
 	if (!vpu_fmt) {
 		f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat;
 		f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes;
-		wave5_update_pix_fmt_r8(&f->fmt.pix_mp, inst->dst_fmt.width, inst->dst_fmt.height);
+		wave5_update_pix_fmt(&f->fmt.pix_mp, inst->dst_fmt.width, inst->dst_fmt.height);
 	} else {
 		int width = clamp(f->fmt.pix_mp.width, vpu_fmt->min_width, vpu_fmt->max_width);
 		int height = clamp(f->fmt.pix_mp.height, vpu_fmt->min_height, vpu_fmt->max_height);
@@ -506,7 +465,7 @@ static int wave5_vpu_dec_try_fmt_cap(struct file *file, void *fh, struct v4l2_fo
 
 		f->fmt.pix_mp.pixelformat = vpu_fmt->v4l2_pix_fmt;
 		f->fmt.pix_mp.num_planes = info->mem_planes;
-		wave5_update_pix_fmt_r8(&f->fmt.pix_mp, width, height);
+		wave5_update_pix_fmt(&f->fmt.pix_mp, width, height);
 	}
 
 	f->fmt.pix_mp.flags = 0;
@@ -525,7 +484,6 @@ static int wave5_vpu_dec_s_fmt_cap(struct file *file, void *fh, struct v4l2_form
 {
 	struct vpu_instance *inst = wave5_to_vpu_inst(fh);
 	int i, ret;
-	unsigned int scalew, scaleh;
 
 	dev_dbg(inst->dev->dev,
 		"%s: fourcc: %u width: %u height: %u num_planes: %u colorspace: %u field: %u\n",
@@ -533,37 +491,26 @@ static int wave5_vpu_dec_s_fmt_cap(struct file *file, void *fh, struct v4l2_form
 		f->fmt.pix_mp.num_planes, f->fmt.pix_mp.colorspace, f->fmt.pix_mp.field);
 
 	ret = wave5_vpu_dec_try_fmt_cap(file, fh, f);
-
 	if (ret)
 		return ret;
 
-	scalew = inst->src_fmt.width / f->fmt.pix_mp.width;
-	scaleh = inst->src_fmt.height / f->fmt.pix_mp.height;
-
-	//if (scalew > 8 || scaleh > 8 || scalew < 1 || scaleh < 1) {
-	//	dev_err(inst->dev->dev,"Scaling should be 1 to 1/8 (down-scaling only)! Use input parameter. \n");
-	//	return -EINVAL;
-	//}
-
-	inst->display_fmt.width = f->fmt.pix_mp.width;
-	inst->display_fmt.height = f->fmt.pix_mp.height;
-	inst->display_fmt.pixelformat = f->fmt.pix_mp.pixelformat;
-	inst->display_fmt.field = f->fmt.pix_mp.field;
-	inst->display_fmt.flags = f->fmt.pix_mp.flags;
-	inst->display_fmt.num_planes = f->fmt.pix_mp.num_planes;
+	inst->dst_fmt.width = f->fmt.pix_mp.width;
+	inst->dst_fmt.height = f->fmt.pix_mp.height;
 	inst->dst_fmt.pixelformat = f->fmt.pix_mp.pixelformat;
+	inst->dst_fmt.field = f->fmt.pix_mp.field;
+	inst->dst_fmt.flags = f->fmt.pix_mp.flags;
 	inst->dst_fmt.num_planes = f->fmt.pix_mp.num_planes;
-	for (i = 0; i < inst->display_fmt.num_planes; i++) {
-		inst->display_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline;
-		inst->display_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage;
+	for (i = 0; i < inst->dst_fmt.num_planes; i++) {
+		inst->dst_fmt.plane_fmt[i].bytesperline = f->fmt.pix_mp.plane_fmt[i].bytesperline;
+		inst->dst_fmt.plane_fmt[i].sizeimage = f->fmt.pix_mp.plane_fmt[i].sizeimage;
 	}
 
-	if (inst->display_fmt.pixelformat == V4L2_PIX_FMT_NV12 ||
-	    inst->display_fmt.pixelformat == V4L2_PIX_FMT_NV12M) {
+	if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV12 ||
+	    inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV12M) {
 		inst->cbcr_interleave = true;
 		inst->nv21 = false;
-	} else if (inst->display_fmt.pixelformat == V4L2_PIX_FMT_NV21 ||
-		   inst->display_fmt.pixelformat == V4L2_PIX_FMT_NV21M) {
+	} else if (inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV21 ||
+		   inst->dst_fmt.pixelformat == V4L2_PIX_FMT_NV21M) {
 		inst->cbcr_interleave = true;
 		inst->nv21 = true;
 	} else {
@@ -579,15 +526,15 @@ static int wave5_vpu_dec_g_fmt_cap(struct file *file, void *fh, struct v4l2_form
 	struct vpu_instance *inst = wave5_to_vpu_inst(fh);
 	int i;
 
-	f->fmt.pix_mp.width = inst->display_fmt.width;
-	f->fmt.pix_mp.height = inst->display_fmt.height;
-	f->fmt.pix_mp.pixelformat = inst->display_fmt.pixelformat;
-	f->fmt.pix_mp.field = inst->display_fmt.field;
-	f->fmt.pix_mp.flags = inst->display_fmt.flags;
-	f->fmt.pix_mp.num_planes = inst->display_fmt.num_planes;
+	f->fmt.pix_mp.width = inst->dst_fmt.width;
+	f->fmt.pix_mp.height = inst->dst_fmt.height;
+	f->fmt.pix_mp.pixelformat = inst->dst_fmt.pixelformat;
+	f->fmt.pix_mp.field = inst->dst_fmt.field;
+	f->fmt.pix_mp.flags = inst->dst_fmt.flags;
+	f->fmt.pix_mp.num_planes = inst->dst_fmt.num_planes;
 	for (i = 0; i < f->fmt.pix_mp.num_planes; i++) {
-		f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->display_fmt.plane_fmt[i].bytesperline;
-		f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->display_fmt.plane_fmt[i].sizeimage;
+		f->fmt.pix_mp.plane_fmt[i].bytesperline = inst->dst_fmt.plane_fmt[i].bytesperline;
+		f->fmt.pix_mp.plane_fmt[i].sizeimage = inst->dst_fmt.plane_fmt[i].sizeimage;
 	}
 
 	f->fmt.pix_mp.colorspace = inst->colorspace;
@@ -660,7 +607,6 @@ static int wave5_vpu_dec_s_fmt_out(struct file *file, void *fh, struct v4l2_form
 		__func__, f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.width, f->fmt.pix_mp.height,
 		f->fmt.pix_mp.num_planes, f->fmt.pix_mp.field);
 
-
 	ret = wave5_vpu_dec_try_fmt_out(file, fh, f);
 	if (ret)
 		return ret;
@@ -682,9 +628,7 @@ static int wave5_vpu_dec_s_fmt_out(struct file *file, void *fh, struct v4l2_form
 	inst->quantization = f->fmt.pix_mp.quantization;
 	inst->xfer_func = f->fmt.pix_mp.xfer_func;
 
-
-	wave5_update_pix_fmt_r8(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height);
-	wave5_update_pix_fmt_r8(&inst->display_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height);
+	wave5_update_pix_fmt(&inst->dst_fmt, f->fmt.pix_mp.width, f->fmt.pix_mp.height);
 
 	return 0;
 }
@@ -764,7 +708,6 @@ static int wave5_vpu_dec_decoder_cmd(struct file *file, void *fh, struct v4l2_de
 		wave5_handle_bitstream_buffer(inst);
 		inst->ops->start_process(inst);
 		inst->state = VPU_INST_STATE_STOP;
-		//printk("%d wave5 state = %d\n",__LINE__, inst->state);
 
 		ret = wave5_vpu_dec_update_bitstream_buffer(inst, 0);
 		if (ret) {
@@ -865,7 +808,7 @@ static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buff
 {
 	struct vpu_instance *inst = vb2_get_drv_priv(q);
 	struct v4l2_pix_format_mplane inst_format =
-		(q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->display_fmt;
+		(q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ? inst->src_fmt : inst->dst_fmt;
 	unsigned int i;
 	int ret;
 
@@ -936,7 +879,6 @@ static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buff
 		}
 
 		inst->state = VPU_INST_STATE_OPEN;
-		//printk("wave5 state = %d\n",inst->state);
 
 		if (inst->thumbnail_mode)
 			wave5_vpu_dec_give_command(inst, ENABLE_DEC_THUMBNAIL_MODE, NULL);
@@ -1005,7 +947,6 @@ free_bitstream_vbuf:
 static int wave5_vpu_dec_start_streaming_open(struct vpu_instance *inst)
 {
 	struct dec_initial_info initial_info;
-	unsigned int scalew, scaleh;
 	int ret = 0;
 
 	memset(&initial_info, 0, sizeof(struct dec_initial_info));
@@ -1036,7 +977,6 @@ static int wave5_vpu_dec_start_streaming_open(struct vpu_instance *inst)
 			initial_info.profile, initial_info.min_frame_buffer_count);
 
 		inst->state = VPU_INST_STATE_INIT_SEQ;
-		//printk("wave5 state = %d\n",inst->state);
 		inst->min_dst_buf_count = initial_info.min_frame_buffer_count + 1;
 		inst->dst_buf_count = inst->min_dst_buf_count;
 
@@ -1050,29 +990,15 @@ static int wave5_vpu_dec_start_streaming_open(struct vpu_instance *inst)
 
 		if (initial_info.pic_width != inst->src_fmt.width ||
 		    initial_info.pic_height != inst->src_fmt.height) {
-			if (inst->std == W_AVC_DEC) {
-				wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width,
-							initial_info.pic_height);
-				wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width,
-							initial_info.pic_height);
-			} else { //HEVC
-				wave5_update_pix_fmt_r8(&inst->src_fmt, initial_info.pic_width,
-							initial_info.pic_height);
-				wave5_update_pix_fmt_r8(&inst->dst_fmt, initial_info.pic_width,
-							initial_info.pic_height);
-			}
+			wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width,
+					     initial_info.pic_height);
+			wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width,
+					     initial_info.pic_height);
 		}
+
 		inst->crop_rect.right = initial_info.pic_crop_rect.right;
 		inst->crop_rect.bottom = initial_info.pic_crop_rect.bottom;
 
-		scalew = inst->dst_fmt.width / inst->display_fmt.width;
-		scaleh = inst->dst_fmt.height / inst->display_fmt.height;
-
-		if (scalew > 8 || scaleh > 8 || scalew < 1 || scaleh < 1) {
-			wave5_update_pix_fmt(&inst->display_fmt, inst->dst_fmt.width,
-						inst->dst_fmt.height);
-		}
-
 		dev_dbg(inst->dev->dev, "wave5 queue event type: %d id: %d\n",vpu_event_src_ch.type, vpu_event_src_ch.id);
 		v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_src_ch);
 
@@ -1087,7 +1013,6 @@ static int wave5_vpu_dec_start_streaming_seek(struct vpu_instance *inst)
 	struct dec_initial_info initial_info;
 	struct dec_param pic_param;
 	struct dec_output_info dec_output_info;
-	unsigned int scalew, scaleh;
 	int ret = 0;
 	u32 fail_res = 0;
 
@@ -1099,7 +1024,6 @@ static int wave5_vpu_dec_start_streaming_seek(struct vpu_instance *inst)
 
 		src_buf = v4l2_m2m_src_buf_remove(inst->v4l2_fh.m2m_ctx);
 		inst->state = VPU_INST_STATE_STOP;
-		//printk("%d wave5 state = %d\n",__LINE__, inst->state);
 		v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
 		dev_dbg(inst->dev->dev, "%s: wave5_vpu_dec_start_one_frame\n", __func__);
 		return ret;
@@ -1142,29 +1066,15 @@ static int wave5_vpu_dec_start_streaming_seek(struct vpu_instance *inst)
 
 		if (initial_info.pic_width != inst->src_fmt.width ||
 		    initial_info.pic_height != inst->src_fmt.height) {
-			if (inst->std == W_AVC_DEC) {
-				wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width,
-							initial_info.pic_height);
-				wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width,
-							initial_info.pic_height);
-			} else { //HEVC
-				wave5_update_pix_fmt_r8(&inst->src_fmt, initial_info.pic_width,
-							initial_info.pic_height);
-				wave5_update_pix_fmt_r8(&inst->dst_fmt, initial_info.pic_width,
-							initial_info.pic_height);
-			}
+			wave5_update_pix_fmt(&inst->src_fmt, initial_info.pic_width,
+					     initial_info.pic_height);
+			wave5_update_pix_fmt(&inst->dst_fmt, initial_info.pic_width,
+					     initial_info.pic_height);
 		}
+
 		inst->crop_rect.right = initial_info.pic_crop_rect.right;
 		inst->crop_rect.bottom = initial_info.pic_crop_rect.bottom;
 
-		scalew = inst->dst_fmt.width / inst->display_fmt.width;
-		scaleh = inst->dst_fmt.height / inst->display_fmt.height;
-
-		if (scalew > 8 || scaleh > 8 || scalew < 1 || scaleh < 1) {
-			wave5_update_pix_fmt(&inst->display_fmt, inst->dst_fmt.width,
-						inst->dst_fmt.height);
-		}
-
 		v4l2_event_queue_fh(&inst->v4l2_fh, &vpu_event_src_ch);
 
 		wave5_handle_src_buffer(inst);
@@ -1206,22 +1116,22 @@ static void wave5_vpu_dec_buf_queue_dst(struct vb2_buffer *vb)
 		dma_addr_t buf_addr_y = 0, buf_addr_cb = 0, buf_addr_cr = 0;
 		u32 buf_size = 0;
 		u32 non_linear_num = inst->dst_buf_count;
-		u32 fb_stride = inst->display_fmt.width;
-		u32 luma_size = fb_stride * inst->display_fmt.height;
-		u32 chroma_size = (fb_stride / 2) * (inst->display_fmt.height / 2);
+		u32 fb_stride = inst->dst_fmt.width;
+		u32 luma_size = fb_stride * inst->dst_fmt.height;
+		u32 chroma_size = (fb_stride / 2) * (inst->dst_fmt.height / 2);
 
-		if (inst->display_fmt.num_planes == 1) {
+		if (inst->dst_fmt.num_planes == 1) {
 			buf_size = vb2_plane_size(&vbuf->vb2_buf, 0);
 			buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
 			buf_addr_cb = buf_addr_y + luma_size;
 			buf_addr_cr = buf_addr_cb + chroma_size;
-		} else if (inst->display_fmt.num_planes == 2) {
+		} else if (inst->dst_fmt.num_planes == 2) {
 			buf_size = vb2_plane_size(&vbuf->vb2_buf, 0) +
 				vb2_plane_size(&vbuf->vb2_buf, 1);
 			buf_addr_y = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
 			buf_addr_cb = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 1);
 			buf_addr_cr = buf_addr_cb + chroma_size;
-		} else if (inst->display_fmt.num_planes == 3) {
+		} else if (inst->dst_fmt.num_planes == 3) {
 			buf_size = vb2_plane_size(&vbuf->vb2_buf, 0) +
 				vb2_plane_size(&vbuf->vb2_buf, 1) +
 				vb2_plane_size(&vbuf->vb2_buf, 2);
@@ -1233,7 +1143,7 @@ static void wave5_vpu_dec_buf_queue_dst(struct vb2_buffer *vb)
 		inst->frame_buf[vb->index + non_linear_num].buf_cb = buf_addr_cb;
 		inst->frame_buf[vb->index + non_linear_num].buf_cr = buf_addr_cr;
 		inst->frame_buf[vb->index + non_linear_num].size = buf_size;
-		inst->frame_buf[vb->index + non_linear_num].width = inst->display_fmt.width;
+		inst->frame_buf[vb->index + non_linear_num].width = inst->src_fmt.width;
 		inst->frame_buf[vb->index + non_linear_num].stride = fb_stride;
 		inst->frame_buf[vb->index + non_linear_num].map_type = LINEAR_FRAME_MAP;
 		inst->frame_buf[vb->index + non_linear_num].update_fb_info = true;
@@ -1369,7 +1279,6 @@ static void wave5_vpu_dec_stop_streaming(struct vb2_queue *q)
 		if (inst->eos) {
 			inst->eos = FALSE;
 			inst->state = VPU_INST_STATE_INIT_SEQ;
-			//printk("wave5 state = %d\n",inst->state);
 		}
 		inst->queued_dst_buf_num = 0;
 	}
@@ -1422,7 +1331,6 @@ static void wave5_vpu_dec_device_run(void *priv)
 	inst->ops->start_process(inst);
 
 	inst->state = VPU_INST_STATE_PIC_RUN;
-	//printk("wave5 state = %d\n",inst->state);
 }
 
 static void wave5_vpu_dec_job_abort(void *priv)
@@ -1487,7 +1395,6 @@ static int wave5_vpu_open_dec(struct file *filp)
 	v4l2_ctrl_handler_setup(&inst->v4l2_ctrl_hdl);
 
 	wave5_set_default_format(&inst->src_fmt, &inst->dst_fmt);
-	memcpy((void *)&inst->display_fmt, (void *)&inst->dst_fmt, sizeof(struct v4l2_pix_format_mplane));
 	inst->colorspace = V4L2_COLORSPACE_REC709;
 	inst->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
 	inst->hsv_enc = 0;
diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
index dcd061b1..892eff2 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
+++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.h
@@ -1048,7 +1048,6 @@ struct vpu_instance {
 
 	struct v4l2_pix_format_mplane src_fmt;
 	struct v4l2_pix_format_mplane dst_fmt;
-	struct v4l2_pix_format_mplane display_fmt;
 	enum v4l2_colorspace colorspace;
 	enum v4l2_xfer_func xfer_func;
 	enum v4l2_ycbcr_encoding ycbcr_enc;
-- 
2.7.4


From 986cb19183306a5b443c8e892e38f03290840aa9 Mon Sep 17 00:00:00 2001
From: Som Qin <som.qin@starfivetech.com>
Date: Tue, 29 Aug 2023 10:18:47 +0800
Subject: [PATCH 02/16] Media:Wave5: Fix segment fault when finish buffer

Signed-off-by: Som Qin <som.qin@starfivetech.com>

[sw0312.kim: cherry-pick the commit 9aea96f91ea6 from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_6.1.y_devel]
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>

Change-Id: Ic2bf17247ed6ec08582d5b98b4e0be24d6a07ce0
---
 drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
index 481273d..fda9090 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
+++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
@@ -316,6 +316,11 @@ static void wave5_vpu_dec_finish_decode(struct vpu_instance *inst)
 				v4l2_m2m_dst_buf_remove_by_idx(inst->v4l2_fh.m2m_ctx,
 							       dec_output_info.index_frame_display);
 
+			if (!dst_buf) {
+				dev_dbg(inst->dev->dev,"find no dst_buf \n");
+				return;
+			}
+
 			stride = dec_output_info.disp_frame.stride;
 			height = dec_output_info.disp_pic_height -
 				dec_output_info.rc_display.bottom;
-- 
2.7.4


From 92812acdd0161d35a15f9829e441c60a1125e45b Mon Sep 17 00:00:00 2001
From: Som Qin <som.qin@starfivetech.com>
Date: Wed, 30 Aug 2023 09:23:21 +0800
Subject: [PATCH 03/16] Media:Wave5: Allocate more linear buffer to avoid block
 in gst-play

Signed-off-by: Som Qin <som.qin@starfivetech.com>

[sw0312.kim: cherry-pick the commit a95153b6cedf from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_6.1.y_devel]
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>

Change-Id: I526c47f67fa196e27d7e4ad5e685252e8a034989
---
 drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
index fda9090..e97b3b0 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
+++ b/drivers/media/platform/chips-media/wave5/wave5-vpu-dec.c
@@ -345,11 +345,7 @@ static void wave5_vpu_dec_finish_decode(struct vpu_instance *inst)
 						      ((stride / 2) * (height / 2)));
 			}
 
-			if (inst->timestamp) {
-				dst_buf->vb2_buf.timestamp = inst->timestamp;
-			} else {
-				dst_buf->vb2_buf.timestamp = inst->timestamp_cnt++ * inst->codec_info->dec_info.initial_info.ns_per_frame;
-			}
+			dst_buf->vb2_buf.timestamp = inst->timestamp_cnt++ * inst->codec_info->dec_info.initial_info.ns_per_frame;
 
 			dst_buf->field = V4L2_FIELD_NONE;
 			v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
@@ -897,6 +893,7 @@ static int wave5_vpu_dec_queue_setup(struct vb2_queue *q, unsigned int *num_buff
 		//if (*num_buffers > inst->min_dst_buf_count &&
 		//    *num_buffers < WAVE5_MAX_FBS)
 		//	inst->dst_buf_count = *num_buffers;
+		inst->dst_buf_count += 2;
 
 		*num_buffers = inst->dst_buf_count;
 		non_linear_num = inst->dst_buf_count;
-- 
2.7.4


From 4ae8c528a8443d42d0225b4019f55685f3d925a3 Mon Sep 17 00:00:00 2001
From: Som Qin <som.qin@starfivetech.com>
Date: Wed, 30 Aug 2023 14:10:50 +0800
Subject: [PATCH 04/16] Medis:wave5: Remove inexistent including

File sifive_l2_cache.h is inexistent in sdk 6.1 version.

Signed-off-by: Som Qin <som.qin@starfivetech.com>

[sw0312.kim: cherry-pick the commit ed137a80cd88 from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_6.1.y_devel
 - Change sifive cache flush function name properly]
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>

Change-Id: Id9d63d72fab1ab0ddeecdb46aeaa19cb0045ed36
---
 drivers/media/platform/chips-media/wave5/wave5-vdi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/chips-media/wave5/wave5-vdi.c b/drivers/media/platform/chips-media/wave5/wave5-vdi.c
index 4a0e4b8..9301dd2 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-vdi.c
+++ b/drivers/media/platform/chips-media/wave5/wave5-vdi.c
@@ -10,11 +10,11 @@
 #include "wave5-vpu.h"
 #include "wave5-regdefine.h"
 #include <linux/delay.h>
+
 #ifdef CONFIG_SIFIVE_FLUSH
-#include <soc/sifive/sifive_l2_cache.h>
+extern void sifive_flush64_range(unsigned long start, unsigned long len);
 #endif
 
-
 #define VDI_SYSTEM_ENDIAN		VDI_LITTLE_ENDIAN
 #define VDI_128BIT_BUS_SYSTEM_ENDIAN	VDI_128BIT_LITTLE_ENDIAN
 
-- 
2.7.4


From 14b3c5361aff26ff8360e137c2bc9f4b60513fdb Mon Sep 17 00:00:00 2001
From: Samin Guo <samin.guo@starfivetech.com>
Date: Thu, 8 Jun 2023 16:01:33 +0800
Subject: [PATCH 05/16] riscv: dts: starfive: jh7110: Add vpu/jpu nodes

Add vpu/jpu nodes for jh7110 SOC

Signed-off-by: Samin Guo <samin.guo@starfivetech.com>

[sw0312.kim: port the commit e2d1cdfe5ff5 from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_6.1.y_devel
 - Port upstream jh7110 clk and sys-reset controller macro name]
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>

Change-Id: Iae673d805d9549ba96f3c08ee93ea69148f68e1e
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 64 ++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 954e336..c8c4f0b 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -1070,6 +1070,70 @@
 			status = "disabled";
 		};
 
+		jpu: jpu@13090000 {
+			compatible = "starfive,jpu";
+			reg = <0x0 0x13090000 0x0 0x300>;
+			interrupts = <14>;
+			clocks = <&syscrg JH7110_SYSCLK_CODAJ12_AXI>,
+				 <&syscrg JH7110_SYSCLK_CODAJ12_CORE>,
+				 <&syscrg JH7110_SYSCLK_CODAJ12_APB>,
+				 <&syscrg JH7110_SYSCLK_NOC_BUS_VDEC_AXI>;
+			clock-names = "axi_clk", "core_clk",
+				      "apb_clk", "noc_bus";
+			resets = <&syscrg JH7110_SYSRST_CODAJ12_AXI>,
+				 <&syscrg JH7110_SYSRST_CODAJ12_CORE>,
+				 <&syscrg JH7110_SYSRST_CODAJ12_APB>;
+			reset-names = "rst_axi", "rst_core", "rst_apb";
+			power-domains = <&pwrc JH7110_PD_VDEC>;
+			status = "disabled";
+		};
+
+		vpu_dec: vpu_dec@130A0000 {
+			compatible = "starfive,vdec";
+			reg = <0x0 0x130A0000 0x0 0x10000>;
+			interrupts = <13>;
+			clocks = <&syscrg JH7110_SYSCLK_WAVE511_AXI>,
+				 <&syscrg JH7110_SYSCLK_WAVE511_BPU>,
+				 <&syscrg JH7110_SYSCLK_WAVE511_VCE>,
+				 <&syscrg JH7110_SYSCLK_WAVE511_APB>,
+				 <&syscrg JH7110_SYSCLK_NOC_BUS_VDEC_AXI>;
+			clock-names = "axi_clk", "bpu_clk", "vce_clk",
+				      "apb_clk", "noc_bus";
+			resets = <&syscrg JH7110_SYSRST_WAVE511_AXI>,
+				 <&syscrg JH7110_SYSRST_WAVE511_BPU>,
+				 <&syscrg JH7110_SYSRST_WAVE511_VCE>,
+				 <&syscrg JH7110_SYSRST_WAVE511_APB>,
+				 <&syscrg JH7110_SYSRST_AXIMEM0_AXI>;
+			reset-names = "rst_axi", "rst_bpu", "rst_vce",
+				      "rst_apb", "rst_sram";
+			starfive,vdec_noc_ctrl;
+			power-domains = <&pwrc JH7110_PD_VDEC>;
+			status = "disabled";
+		};
+
+		vpu_enc: vpu_enc@130B0000 {
+			compatible = "starfive,venc";
+			reg = <0x0 0x130B0000 0x0 0x10000>;
+			interrupts = <15>;
+			clocks = <&syscrg JH7110_SYSCLK_VENC_AXI>,
+				 <&syscrg JH7110_SYSCLK_WAVE420L_BPU>,
+				 <&syscrg JH7110_SYSCLK_WAVE420L_VCE>,
+				 <&syscrg JH7110_SYSCLK_WAVE420L_APB>,
+				 <&syscrg JH7110_SYSCLK_NOC_BUS_VENC_AXI>;
+			clock-names = "axi_clk", "bpu_clk", "vce_clk",
+				      "apb_clk", "noc_bus";
+			resets = <&syscrg JH7110_SYSRST_WAVE420L_AXI>,
+				 <&syscrg JH7110_SYSRST_WAVE420L_BPU>,
+				 <&syscrg JH7110_SYSRST_WAVE420L_VCE>,
+				 <&syscrg JH7110_SYSRST_WAVE420L_APB>,
+				 <&syscrg JH7110_SYSRST_AXIMEM1_AXI>;
+			reset-names = "rst_axi", "rst_bpu", "rst_vce",
+				      "rst_apb", "rst_sram";
+			starfive,venc_noc_ctrl;
+			power-domains = <&pwrc JH7110_PD_VENC>;
+			status = "disabled";
+		};
+
 		dma: dma-controller@16050000 {
 			compatible = "starfive,jh7110-axi-dma";
 			reg = <0x0 0x16050000 0x0 0x10000>;
-- 
2.7.4


From 026ddfd6de4593ea84bd9f2ee674234b9dd66b9f Mon Sep 17 00:00:00 2001
From: Samin Guo <samin.guo@starfivetech.com>
Date: Wed, 23 Aug 2023 10:43:54 +0800
Subject: [PATCH 06/16] riscv: dts: starfive: jh7110: add dma-coherent for
 vpu/jpu

Use DMA-Coherent to avoid DIRECT_REMAP when allocating DMA
buffers

Signed-off-by: Samin Guo <samin.guo@starfivetech.com>

[sw0312.kim: cherry-pick the commit dfb44f0122ba from https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_6.1.y_devel]
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>

Change-Id: Ia0d3955010e963c0fb635e10081c1a2ab31155d4
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index c8c4f0b..4ac5ca7 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -1072,6 +1072,7 @@
 
 		jpu: jpu@13090000 {
 			compatible = "starfive,jpu";
+			dma-coherent;
 			reg = <0x0 0x13090000 0x0 0x300>;
 			interrupts = <14>;
 			clocks = <&syscrg JH7110_SYSCLK_CODAJ12_AXI>,
@@ -1090,6 +1091,7 @@
 
 		vpu_dec: vpu_dec@130A0000 {
 			compatible = "starfive,vdec";
+			dma-coherent;
 			reg = <0x0 0x130A0000 0x0 0x10000>;
 			interrupts = <13>;
 			clocks = <&syscrg JH7110_SYSCLK_WAVE511_AXI>,
@@ -1113,6 +1115,7 @@
 
 		vpu_enc: vpu_enc@130B0000 {
 			compatible = "starfive,venc";
+			dma-coherent;
 			reg = <0x0 0x130B0000 0x0 0x10000>;
 			interrupts = <15>;
 			clocks = <&syscrg JH7110_SYSCLK_VENC_AXI>,
-- 
2.7.4


From 708a313fba9e9aea566c5276f7f41fd91e04f44f Mon Sep 17 00:00:00 2001
From: Seung-Woo Kim <sw0312.kim@samsung.com>
Date: Wed, 24 Jan 2024 10:50:06 +0900
Subject: [PATCH 07/16] RISCV: dts: starfive: enable jpg, vpu_dec and vpu_enc
 nodes in visionfive-2

To support video codec, wave vpu, enable related jpg, vpu_dec and
vpu_enc nodes in visionfive-2.

NOTE: Only wave511 vpu_dec is supported with wave video codec
driver because visionfive-2 vpu_enc wave420 is different from
currently supported wave521 by the driver.

Change-Id: Icdd828ce35c98eee9a90a82c69c13614e53bb970
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
---
 .../boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi      | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 77d5782..732d74a 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -280,6 +280,18 @@
 	status = "okay";
 };
 
+&jpu {
+	status = "okay";
+};
+
+&vpu_dec {
+	status = "okay";
+};
+
+&vpu_enc {
+	status = "okay";
+};
+
 &i2c0 {
 	clock-frequency = <100000>;
 	i2c-sda-hold-time-ns = <300>;
-- 
2.7.4


From 23b2320e40935ba7f952060739a15b6e83973f8a Mon Sep 17 00:00:00 2001
From: Seung-Woo Kim <sw0312.kim@samsung.com>
Date: Wed, 24 Jan 2024 10:50:20 +0900
Subject: [PATCH 08/16] media: chips-media: wave511: Fix null deference in
 wave5_vpu_dec_clr_disp_flag()

If wave5_vpu_dec_open() is not called before calling
wave5_vpu_dec_clr_disp_flag(), there is null deference. Fix the
null deference by checking codec_info.

Change-Id: I1a4d9a75681df293e1f67dd4338c6f770d789223
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
---
 drivers/media/platform/chips-media/wave5/wave5-vpuapi.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
index 5a0078a..4e38a4d 100644
--- a/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
+++ b/drivers/media/platform/chips-media/wave5/wave5-vpuapi.c
@@ -625,10 +625,14 @@ err_out:
 
 int wave5_vpu_dec_clr_disp_flag(struct vpu_instance *inst, int index)
 {
-	struct dec_info *p_dec_info = &inst->codec_info->dec_info;
+	struct dec_info *p_dec_info;
 	int ret = 0;
 	struct vpu_device *vpu_dev = inst->dev;
 
+	if (!inst->codec_info)
+		return -EINVAL;
+
+	p_dec_info = &inst->codec_info->dec_info;
 	if (index >= p_dec_info->num_of_display_fbs)
 		return -EINVAL;
 
-- 
2.7.4


From b9471f4b7c1a0981da24db958f4b29d4353f5dca Mon Sep 17 00:00:00 2001
From: Seung-Woo Kim <sw0312.kim@samsung.com>
Date: Mon, 5 Feb 2024 16:24:00 +0900
Subject: [PATCH 09/16] RISCV: config: enable wave511 video codec driver as
 module

Enable wave511 video codec driver as module and also enable all
depending configs.

Change-Id: I0aeb0dfc0a844a3cc17c5054df61454c3f88e5fb
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
---
 arch/riscv/configs/tizen_visionfive2_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig
index 62219f0..e5ff49a 100644
--- a/arch/riscv/configs/tizen_visionfive2_defconfig
+++ b/arch/riscv/configs/tizen_visionfive2_defconfig
@@ -291,6 +291,7 @@ CONFIG_USB_GSPCA_ZC3XX=m
 CONFIG_USB_VIDEO_CLASS=y
 CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_WAVE_VPU=m
 CONFIG_DRM_VERISILICON=y
 CONFIG_DRM_VERISILICON_STARFIVE_HDMI=y
 CONFIG_DRM_IMG_ROGUE=y
-- 
2.7.4


From 99ff9f776cbffd8c0cb15c524c086d7bf5c78315 Mon Sep 17 00:00:00 2001
From: Marek Szyprowski <m.szyprowski@samsung.com>
Date: Thu, 8 Feb 2024 13:36:53 +0100
Subject: [PATCH 10/16] RISCV: config: tizen_visionfive2: Disable JH7110 crypto
 driver

JH7110 crypto driver seems to be causing memory trashing, so temporarily
disable it until the issue is really fixed.

This fixes the 'i2c controller timed out' and some other random issues.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I3c1030a0eaf41d7cf97b0fdc6d228bc61681ef5e
---
 arch/riscv/configs/tizen_visionfive2_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig
index e5ff49a..83211ed 100644
--- a/arch/riscv/configs/tizen_visionfive2_defconfig
+++ b/arch/riscv/configs/tizen_visionfive2_defconfig
@@ -406,7 +406,6 @@ CONFIG_CRYPTO_LZ4=y
 CONFIG_CRYPTO_ZSTD=y
 CONFIG_CRYPTO_USER_API_HASH=y
 CONFIG_CRYPTO_DEV_VIRTIO=y
-CONFIG_CRYPTO_DEV_JH7110=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_PAGEALLOC=y
 CONFIG_SCHED_STACK_END_CHECK=y
-- 
2.7.4


From 145b72894b4aa791653885cc2b76185aac64a3a8 Mon Sep 17 00:00:00 2001
From: Tymoteusz Wenerski <t.wenerski@partner.samsung.com>
Date: Wed, 21 Feb 2024 11:28:23 +0100
Subject: [PATCH 11/16] RISCV: config: tizen_visionfive2: Enable NVME driver
MIME-Version: 1.0
Content-Type: text/plain; charset=utf8
Content-Transfer-Encoding: 8bit

Enable NVME driver to mount rootfs directly
from NVME drive during boot.

Change-Id: I60e02507f394c1001c32c802151c0152c24b1397
Signed-off-by: Tymoteusz Wenerski <t.wenerski@partner.samsung.com>
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
---
 arch/riscv/configs/tizen_visionfive2_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig
index 83211ed..462160e 100644
--- a/arch/riscv/configs/tizen_visionfive2_defconfig
+++ b/arch/riscv/configs/tizen_visionfive2_defconfig
@@ -205,6 +205,7 @@ CONFIG_VIRTIO_BLK=y
 CONFIG_TIZEN_INFORM_REBOOT=y
 CONFIG_TIZEN_INFORM_PATH="/mnt/inform/reboot-param.bin"
 CONFIG_EEPROM_AT24=y
+CONFIG_BLK_DEV_NVME=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_SCSI_VIRTIO=y
-- 
2.7.4


From 0a38c9c92037b62fb4032aaa0b053c901e5d9c1f Mon Sep 17 00:00:00 2001
From: Seung-Woo Kim <sw0312.kim@samsung.com>
Date: Thu, 7 Mar 2024 17:08:03 +0900
Subject: [PATCH 12/16] RISCV: config: tizen_*: Sync with make savedefconfig

Store minimized defconfig with "make savedefconfig" for each tizen
defconfig files.

Change-Id: I484e3b5bde342ee36a4e02010b703c1c48190d16
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
---
 arch/riscv/configs/tizen_qemu_defconfig        | 6 ------
 arch/riscv/configs/tizen_visionfive2_defconfig | 2 +-
 2 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/arch/riscv/configs/tizen_qemu_defconfig b/arch/riscv/configs/tizen_qemu_defconfig
index d24489b..7617fe4 100644
--- a/arch/riscv/configs/tizen_qemu_defconfig
+++ b/arch/riscv/configs/tizen_qemu_defconfig
@@ -25,8 +25,6 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_NET=y
 CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_ADVANCED_ROUTER=y
 CONFIG_IP_PNP=y
@@ -68,8 +66,6 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
-CONFIG_HVC_RISCV_SBI=y
 CONFIG_SERIAL_DEV_BUS=y
 CONFIG_TTY_PRINTK=y
 CONFIG_VIRTIO_CONSOLE=y
@@ -83,7 +79,6 @@ CONFIG_GPIO_SIFIVE=y
 CONFIG_DRM=y
 CONFIG_DRM_VIRTIO_GPU=y
 CONFIG_FB=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_VIRTIO=y
@@ -113,7 +108,6 @@ CONFIG_BTRFS_FS_POSIX_ACL=y
 CONFIG_F2FS_FS=y
 CONFIG_F2FS_FS_SECURITY=y
 CONFIG_FANOTIFY=y
-CONFIG_AUTOFS4_FS=y
 CONFIG_FUSE_FS=y
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig
index 462160e..74629c9 100644
--- a/arch/riscv/configs/tizen_visionfive2_defconfig
+++ b/arch/riscv/configs/tizen_visionfive2_defconfig
@@ -202,10 +202,10 @@ CONFIG_BLK_DEV_NBD=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=32768
 CONFIG_VIRTIO_BLK=y
+CONFIG_BLK_DEV_NVME=y
 CONFIG_TIZEN_INFORM_REBOOT=y
 CONFIG_TIZEN_INFORM_PATH="/mnt/inform/reboot-param.bin"
 CONFIG_EEPROM_AT24=y
-CONFIG_BLK_DEV_NVME=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_SCSI_VIRTIO=y
-- 
2.7.4


From 1b517291bff1ced5c85fb73deff1e369806aff26 Mon Sep 17 00:00:00 2001
From: Seung-Woo Kim <sw0312.kim@samsung.com>
Date: Thu, 7 Mar 2024 17:23:14 +0900
Subject: [PATCH 13/16] RISCV: config: tizen_visionfive2: Enable HID_MULTITOUCH

To support usb touchscreen, enable CONFIG_HID_MULTITOUCH.

Change-Id: I341e1a7951e704b0d16a98caea881305137c56cd
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
---
 arch/riscv/configs/tizen_visionfive2_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig
index 74629c9..f72e89b 100644
--- a/arch/riscv/configs/tizen_visionfive2_defconfig
+++ b/arch/riscv/configs/tizen_visionfive2_defconfig
@@ -310,6 +310,7 @@ CONFIG_SND_SOC_WM8960=y
 CONFIG_SND_SIMPLE_CARD=y
 CONFIG_HIDRAW=y
 CONFIG_UHID=y
+CONFIG_HID_MULTITOUCH=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
-- 
2.7.4


From cf5bccd3476119ba0c2bf9001f20d7b5840f4ef8 Mon Sep 17 00:00:00 2001
From: Seung-Woo Kim <sw0312.kim@samsung.com>
Date: Thu, 7 Mar 2024 18:05:39 +0900
Subject: [PATCH 14/16] RISCV: config: tizen_visionfive2: enable
 DRM_LOAD_EDID_FIRMWARE

Enable CONFIG_DRM_LOAD_EDID_FIRMWARE from tizen defconfigs to
support drm.edid_firmware paremeter.
Adding "drm.edid_firmware=edid/1920x1080.bin" to cmdline makes
all connected display connector has the 1920x1080 mode.

Kernel has prebuilt edids, 800x600.bin, 1024x768.bin,
1280x1024.bin, 1600x1200.bin, 1680x1050.bin and 1920x1080.bin
and to use other mode edids, put custom edid files into path
/lib/firmware/edid/.

Note: to build custom edid binary, please refer tools/edid/.

Change-Id: Ia87be1d9f7a5e6af38201dc432fc046478e80dae
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
---
 arch/riscv/configs/tizen_visionfive2_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig
index f72e89b..ec813e2 100644
--- a/arch/riscv/configs/tizen_visionfive2_defconfig
+++ b/arch/riscv/configs/tizen_visionfive2_defconfig
@@ -293,6 +293,7 @@ CONFIG_USB_VIDEO_CLASS=y
 CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_V4L_MEM2MEM_DRIVERS=y
 CONFIG_VIDEO_WAVE_VPU=m
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
 CONFIG_DRM_VERISILICON=y
 CONFIG_DRM_VERISILICON_STARFIVE_HDMI=y
 CONFIG_DRM_IMG_ROGUE=y
-- 
2.7.4


From d6492bf94d9a6b0384129b0a5d16eba574c31366 Mon Sep 17 00:00:00 2001
From: Seung-Woo Kim <sw0312.kim@samsung.com>
Date: Fri, 8 Mar 2024 14:45:26 +0900
Subject: [PATCH 15/16] drm/edid/firmware: Add built-in edid/1280x720.bin
 firmware

Add built-in edid/1280x720.bin firmware to drm_edid_loader.
The mode is generated from tools/edid/ with below edid data:
   /* 1280x720: Modeline "1280x720" 74.50 1280 1344 1472 1664 720 723 728 748 -hsync +vsync */
   #define HSYNC_POL 1
   #define VSYNC_POL 1
   #define YPULSE (63+5)
   #define XPULSE 128
   #define YPIX 720
   #define XPIX 1280
   #define VFREQ 60
   #define DPI 96
   #define CLOCK 74500
   #define VERSION 1
   #define REVISION 3
   #define XOFFSET 64
   #define YOFFSET (63+3)
   #define XY_RATIO XY_RATIO_16_9
   #define YBLANK 28
   #define XBLANK 384
   #define TIMING_NAME "1280x720"
   #include "edid.S"

Change-Id: Idfc610102a35494ee54aca06af411cfd9d737b0f
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
---
 drivers/gpu/drm/drm_edid_load.c | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_edid_load.c b/drivers/gpu/drm/drm_edid_load.c
index 5d9ef26..654c01b 100644
--- a/drivers/gpu/drm/drm_edid_load.c
+++ b/drivers/gpu/drm/drm_edid_load.c
@@ -39,10 +39,11 @@ int __drm_get_edid_firmware_path(char *buf, size_t bufsize)
 }
 EXPORT_SYMBOL(__drm_get_edid_firmware_path);
 
-#define GENERIC_EDIDS 6
+#define GENERIC_EDIDS 7
 static const char * const generic_edid_name[GENERIC_EDIDS] = {
 	"edid/800x600.bin",
 	"edid/1024x768.bin",
+	"edid/1280x720.bin",
 	"edid/1280x1024.bin",
 	"edid/1600x1200.bin",
 	"edid/1680x1050.bin",
@@ -89,6 +90,24 @@ static const u8 generic_edid[GENERIC_EDIDS][128] = {
 	{
 	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
 	0x31, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x05, 0x16, 0x01, 0x03, 0x6d, 0x21, 0x12, 0x78,
+	0xea, 0x5e, 0xc0, 0xa4, 0x59, 0x4a, 0x98, 0x25,
+	0x20, 0x50, 0x54, 0x00, 0x00, 0x00, 0x81, 0xc0,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x1a, 0x1d,
+	0x00, 0x80, 0x51, 0xd0, 0x1c, 0x20, 0x40, 0x80,
+	0x24, 0x00, 0x4d, 0xbb, 0x10, 0x00, 0x00, 0x1e,
+	0x00, 0x00, 0x00, 0xff, 0x00, 0x4c, 0x69, 0x6e,
+	0x75, 0x78, 0x20, 0x23, 0x30, 0x0a, 0x20, 0x20,
+	0x20, 0x20, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x3b,
+	0x3d, 0x2b, 0x2d, 0x08, 0x00, 0x0a, 0x20, 0x20,
+	0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
+	0x00, 0x31, 0x32, 0x38, 0x30, 0x78, 0x37, 0x32,
+	0x30, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x00, 0x6c,
+	},
+	{
+	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
+	0x31, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 	0x05, 0x16, 0x01, 0x03, 0x6d, 0x2c, 0x23, 0x78,
 	0xea, 0x5e, 0xc0, 0xa4, 0x59, 0x4a, 0x98, 0x25,
 	0x20, 0x50, 0x54, 0x00, 0x00, 0x00, 0x81, 0x80,
-- 
2.7.4


From 163de2e4bc2cd939bb937d3ff12ff685b0cb32f7 Mon Sep 17 00:00:00 2001
From: Jaehoon Chung <jh80.chung@samsung.com>
Date: Tue, 12 Mar 2024 19:33:31 +0900
Subject: [PATCH 16/16] RISCV: configs: tizen_visoinfive2: Disable RISCV_ISA_V
 config

Visionfive2 doesn't support V extenstion.
It needs to disable its configuration.

Change-Id: I6b6ddc5b7027cdd6bd411f53df787e22e48993af
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
 arch/riscv/configs/tizen_visionfive2_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig
index ec813e2..26460dd 100644
--- a/arch/riscv/configs/tizen_visionfive2_defconfig
+++ b/arch/riscv/configs/tizen_visionfive2_defconfig
@@ -29,6 +29,7 @@ CONFIG_PROFILING=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_SMP=y
+# CONFIG_RISCV_ISA_V is not set
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_STAT=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
-- 
2.7.4