From 60369185012e4ae5297b1c06670f1da5a97c0841 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Fri, 7 Jul 2023 13:11:35 +0900 Subject: [PATCH 01/16] soc: starfive: Add feature for hw event masks Add hw event masks off feature for use with other drives. Change-Id: I5b8862cd50b35f0b8ceed770d95a5c17bde8b12c Signed-off-by: Hoegeun Kwon Signed-off-by: Walker Chen --- drivers/soc/starfive/jh71xx_pmu.c | 11 +++++++++++ include/soc/starfive/jh71xx_pmu.h | 14 ++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 include/soc/starfive/jh71xx_pmu.h diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c index 7d5f50d..8bb03c9 100644 --- a/drivers/soc/starfive/jh71xx_pmu.c +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -16,6 +16,7 @@ #include /* register offset */ +#define JH71XX_PMU_HW_EVENT_TURN_OFF_MASK 0x08 #define JH71XX_PMU_SW_TURN_ON_POWER 0x0C #define JH71XX_PMU_SW_TURN_OFF_POWER 0x10 #define JH71XX_PMU_SW_ENCOURAGE 0x44 @@ -72,6 +73,14 @@ struct jh71xx_pmu_dev { struct generic_pm_domain genpd; }; +static void __iomem *pmu_base; + +void jh71xx_pmu_hw_event_turn_off_mask(u32 mask) +{ + writel(mask, pmu_base + JH71XX_PMU_HW_EVENT_TURN_OFF_MASK); +} +EXPORT_SYMBOL(jh71xx_pmu_hw_event_turn_off_mask); + static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_on) { struct jh71xx_pmu *pmu = pmd->pmu; @@ -316,6 +325,8 @@ static int jh71xx_pmu_probe(struct platform_device *pdev) return ret; } + pmu_base = pmu->base; + dev_dbg(dev, "registered %u power domains\n", i); return 0; diff --git a/include/soc/starfive/jh71xx_pmu.h b/include/soc/starfive/jh71xx_pmu.h new file mode 100644 index 0000000..425fea5 --- /dev/null +++ b/include/soc/starfive/jh71xx_pmu.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * StarFive JH71XX PMU (Power Management Unit) Controller Driver + * + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + + +#ifndef __SOC_STARFIVE_JH71XX_PMU_H__ +#define __SOC_STARFIVE_JH71XX_PMU_H__ + +void jh71xx_pmu_hw_event_turn_off_mask(u32 mask); + +#endif /* __SOC_STARFIVE_JH71XX_PMU_H__ */ -- 2.7.4 From acc91742c8dbcdae78287306ec17be87b0c6ba86 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Fri, 7 Jul 2023 13:13:14 +0900 Subject: [PATCH 02/16] gpu: drm: img: Fix to use jh71xx_pmu header Fix to use jh71xx_pmu header and sifive_flush64_range. Change-Id: I9ad7d5f3de347be0f26ceb4633b0125d2a6480ef Signed-off-by: Hoegeun Kwon --- .../img/img-rogue/services/system/rogue/sf_7110/sysconfig.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.c b/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.c index 91f7a4de..9ba5ea3 100644 --- a/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.c +++ b/drivers/gpu/drm/img/img-rogue/services/system/rogue/sf_7110/sysconfig.c @@ -45,7 +45,7 @@ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #include #include #include -#include +#include #endif #include "pvr_debug.h" @@ -95,11 +95,11 @@ static void SetFrequency(IMG_UINT32 ui32Frequency) {} static void SetVoltage(IMG_UINT32 ui32Volt) {} #endif -extern void sifive_l2_flush64_range(unsigned long start, unsigned long len); +extern void sifive_flush64_range(unsigned long start, unsigned long len); void do_sifive_l2_flush64_range(unsigned long start, unsigned long len) { - sifive_l2_flush64_range(ALIGN_DOWN(start, 64), len + start % 64); + sifive_flush64_range(ALIGN_DOWN(start, 64), len + start % 64); } void do_invalid_range(unsigned long start, unsigned long len) @@ -224,7 +224,7 @@ void SysDevHost_Cache_Maintenance(IMG_HANDLE hSysData, static IMG_UINT32 sys_gpu_runtime_resume(IMG_HANDLE hd) { - starfive_pmu_hw_event_turn_off_mask(0); + jh71xx_pmu_hw_event_turn_off_mask(0); clk_prepare_enable(sf_cfg_t.clk_axi); u0_img_gpu_enable(); @@ -235,7 +235,7 @@ static IMG_UINT32 sys_gpu_runtime_suspend(IMG_HANDLE hd) { u0_img_gpu_disable(); clk_disable_unprepare(sf_cfg_t.clk_axi); - starfive_pmu_hw_event_turn_off_mask((uint32_t)-1); + jh71xx_pmu_hw_event_turn_off_mask((uint32_t)-1); return 0; } -- 2.7.4 From 05bbaaf3735df9a39fb4eb4a665d07a49d6560f9 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Fri, 7 Jul 2023 11:16:18 +0900 Subject: [PATCH 03/16] gpu: drm: img: Fix to use iterator instead of list Change the dma fence management method from list to iterator method. Also the fences have to added individually on each other driver. So dma_resv_add_fence does not add a fence, but dma_resv_reserve_fences is used to add it. Change-Id: I4c87608b9878e218fe0ae5cc5acb564c1f9d5db9 Signed-off-by: Hoegeun Kwon --- .../services/server/env/linux/pvr_buffer_sync.c | 58 +++++----------------- 1 file changed, 13 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/img/img-rogue/services/server/env/linux/pvr_buffer_sync.c b/drivers/gpu/drm/img/img-rogue/services/server/env/linux/pvr_buffer_sync.c index b5426d4..ab99301 100644 --- a/drivers/gpu/drm/img/img-rogue/services/server/env/linux/pvr_buffer_sync.c +++ b/drivers/gpu/drm/img/img-rogue/services/server/env/linux/pvr_buffer_sync.c @@ -177,7 +177,7 @@ pvr_buffer_sync_pmrs_fence_count(u32 nr_pmrs, struct _PMR_ **pmrs, u32 *pmr_flags) { struct dma_resv *resv; - struct dma_resv_list *resv_list; + struct dma_resv_iter cursor; struct dma_fence *fence; u32 fence_count = 0; bool exclusive; @@ -190,15 +190,9 @@ pvr_buffer_sync_pmrs_fence_count(u32 nr_pmrs, struct _PMR_ **pmrs, if (WARN_ON_ONCE(!resv)) continue; - resv_list = dma_resv_shared_list(resv); - fence = dma_resv_excl_fence(resv); - - if (fence && - (!exclusive || !resv_list || !resv_list->shared_count)) + dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) { fence_count++; - - if (exclusive && resv_list) - fence_count += resv_list->shared_count; + } } return fence_count; @@ -213,11 +207,11 @@ pvr_buffer_sync_check_fences_create(struct pvr_fence_context *fence_ctx, { struct pvr_buffer_sync_check_data *data; struct dma_resv *resv; - struct dma_resv_list *resv_list; + struct dma_resv_iter cursor; struct dma_fence *fence; u32 fence_count; bool exclusive; - int i, j; + int i; int err; data = kzalloc(sizeof(*data), GFP_KERNEL); @@ -239,21 +233,14 @@ pvr_buffer_sync_check_fences_create(struct pvr_fence_context *fence_ctx, continue; exclusive = !!(pmr_flags[i] & PVR_BUFFER_FLAG_WRITE); - if (!exclusive) { - err = dma_resv_reserve_shared(resv -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0)) - , 1 -#endif - ); + + if (!fence_count) { + err = dma_resv_reserve_fences(resv, 1); if (err) goto err_destroy_fences; } - resv_list = dma_resv_shared_list(resv); - fence = dma_resv_excl_fence(resv); - - if (fence && - (!exclusive || !resv_list || !resv_list->shared_count)) { + dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) { data->fences[data->nr_fences++] = pvr_fence_create_from_fence(fence_ctx, sync_checkpoint_ctx, @@ -267,25 +254,6 @@ pvr_buffer_sync_check_fences_create(struct pvr_fence_context *fence_ctx, WARN_ON(dma_fence_wait(fence, true) <= 0); } } - - if (exclusive && resv_list) { - for (j = 0; j < resv_list->shared_count; j++) { - fence = rcu_dereference_protected(resv_list->shared[j], - dma_resv_held(resv)); - data->fences[data->nr_fences++] = - pvr_fence_create_from_fence(fence_ctx, - sync_checkpoint_ctx, - fence, - PVRSRV_NO_FENCE, - "check fence"); - if (!data->fences[data->nr_fences - 1]) { - data->nr_fences--; - PVR_FENCE_TRACE(fence, - "waiting on non-exclusive fence\n"); - WARN_ON(dma_fence_wait(fence, true) <= 0); - } - } - } } WARN_ON((i != nr_pmrs) || (data->nr_fences != fence_count)); @@ -531,14 +499,14 @@ pvr_buffer_sync_kick_succeeded(struct pvr_buffer_sync_append_data *data) PVR_FENCE_TRACE(&data->update_fence->base, "added exclusive fence (%s) to resv %p\n", data->update_fence->name, resv); - dma_resv_add_excl_fence(resv, - &data->update_fence->base); + dma_resv_add_fence(resv, + &data->update_fence->base, DMA_RESV_USAGE_WRITE); } else if (data->pmr_flags[i] & PVR_BUFFER_FLAG_READ) { PVR_FENCE_TRACE(&data->update_fence->base, "added non-exclusive fence (%s) to resv %p\n", data->update_fence->name, resv); - dma_resv_add_shared_fence(resv, - &data->update_fence->base); + dma_resv_add_fence(resv, + &data->update_fence->base, DMA_RESV_USAGE_READ); } } -- 2.7.4 From 086732b0cba217f0c5f745ba6297a6e28568b597 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Thu, 13 Jul 2023 18:49:56 +0900 Subject: [PATCH 04/16] RISCV: config: Enable img gpu config Enable Imagination PoerVR GPU driver defconfig. Change-Id: If8e8b51fe59a367a0981f65b5cc7b3f44f9a8782 Signed-off-by: Hoegeun Kwon --- arch/riscv/configs/tizen_visionfive2_defconfig | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig index a306381..32d7896 100644 --- a/arch/riscv/configs/tizen_visionfive2_defconfig +++ b/arch/riscv/configs/tizen_visionfive2_defconfig @@ -283,12 +283,13 @@ CONFIG_REGULATOR_AXP20X=y # CONFIG_MEDIA_CEC_SUPPORT is not set CONFIG_MEDIA_SUPPORT=y CONFIG_VIDEO_DEV=m -CONFIG_DRM=y -CONFIG_DRM_RADEON=m -CONFIG_DRM_NOUVEAU=m -CONFIG_DRM_VIRTIO_GPU=m +# CONFIG_CXD2880_SPI_DRV is not set +CONFIG_DRM_I2C_CH7006=m +CONFIG_DRM_I2C_SIL164=m CONFIG_DRM_VERISILICON=y CONFIG_STARFIVE_HDMI=y +CONFIG_DRM_IMG_ROGUE=y +CONFIG_DRM_LEGACY=y CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_SOUND=y -- 2.7.4 From cddbe6a44246e49b0e0f8c87d746c95fc53e07a5 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Mon, 17 Jul 2023 18:06:27 +0900 Subject: [PATCH 05/16] gpu: drm: img: Fix to check fence list instead of fence count In order to generate a reserve fences, we check to see if there is a fence list instead of fence count. Change-Id: Ibd45c154610221dd7bcd4de96570fc00066457c8 Signed-off-by: Hoegeun Kwon --- .../gpu/drm/img/img-rogue/services/server/env/linux/pvr_buffer_sync.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/img/img-rogue/services/server/env/linux/pvr_buffer_sync.c b/drivers/gpu/drm/img/img-rogue/services/server/env/linux/pvr_buffer_sync.c index ab99301..ab6a5b2 100644 --- a/drivers/gpu/drm/img/img-rogue/services/server/env/linux/pvr_buffer_sync.c +++ b/drivers/gpu/drm/img/img-rogue/services/server/env/linux/pvr_buffer_sync.c @@ -234,7 +234,7 @@ pvr_buffer_sync_check_fences_create(struct pvr_fence_context *fence_ctx, exclusive = !!(pmr_flags[i] & PVR_BUFFER_FLAG_WRITE); - if (!fence_count) { + if (!resv->fences) { err = dma_resv_reserve_fences(resv, 1); if (err) goto err_destroy_fences; -- 2.7.4 From e318dd5d3e8f38910b4a61749c58d9992e717e97 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Mon, 17 Jul 2023 16:38:34 +0900 Subject: [PATCH 06/16] drm/verisilicon: Add cache flush feature when dmabuf sync Add cache flush for gem memory. Cache flushing is done when the dmabuf sync ioctl is called. Change-Id: I8663a391b18bb10f69007bd631fec492c0e347b2 Signed-off-by: Hoegeun Kwon --- drivers/gpu/drm/verisilicon/vs_gem.c | 52 ++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/gpu/drm/verisilicon/vs_gem.c b/drivers/gpu/drm/verisilicon/vs_gem.c index a8d1556..1a3f018 100644 --- a/drivers/gpu/drm/verisilicon/vs_gem.c +++ b/drivers/gpu/drm/verisilicon/vs_gem.c @@ -10,6 +10,10 @@ #include "vs_drv.h" #include "vs_gem.h" +#ifdef CONFIG_SIFIVE_FLUSH +#include +#endif + static const struct drm_gem_object_funcs vs_gem_default_funcs; static int vs_gem_alloc_buf(struct vs_gem_object *vs_obj) @@ -220,6 +224,43 @@ static int vs_gem_mmap_obj(struct drm_gem_object *obj, return ret; } +static int vs_gem_prime_end_cpu_access(struct dma_buf *buf, + enum dma_data_direction direction) +{ +#ifdef CONFIG_SIFIVE_FLUSH + struct drm_gem_object *obj = buf->priv; + struct vs_gem_object *vs_obj = to_vs_gem_object(obj); + + starfive_flush_dcache(vs_obj->dma_addr, vs_obj->size); +#endif + + return 0; +} + +static struct dma_buf_ops vs_gem_prime_dmabuf_ops = { + .cache_sgt_mapping = true, + .attach = drm_gem_map_attach, + .detach = drm_gem_map_detach, + .map_dma_buf = drm_gem_map_dma_buf, + .unmap_dma_buf = drm_gem_unmap_dma_buf, + .release = drm_gem_dmabuf_release, + .mmap = drm_gem_dmabuf_mmap, + .vmap = drm_gem_dmabuf_vmap, + .vunmap = drm_gem_dmabuf_vunmap, + .end_cpu_access = vs_gem_prime_end_cpu_access, +}; + +static struct dma_buf *vs_gem_prime_export(struct drm_gem_object *obj, int flags) +{ + struct dma_buf *dmabuf; + + dmabuf = drm_gem_prime_export(obj, flags); + if (!IS_ERR(dmabuf)) + dmabuf->ops = &vs_gem_prime_dmabuf_ops; + + return dmabuf; +} + struct sg_table *vs_gem_prime_get_sg_table(struct drm_gem_object *obj) { struct vs_gem_object *vs_obj = to_vs_gem_object(obj); @@ -252,6 +293,7 @@ static const struct vm_operations_struct vs_vm_ops = { static const struct drm_gem_object_funcs vs_gem_default_funcs = { .free = vs_gem_free_object, + .export = vs_gem_prime_export, .get_sg_table = vs_gem_prime_get_sg_table, .vmap = vs_gem_prime_vmap, .vunmap = vs_gem_prime_vunmap, @@ -280,6 +322,16 @@ int vs_gem_dumb_create(struct drm_file *file, struct drm_gem_object *vs_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf) { + struct drm_gem_object *obj; + + if (dma_buf->ops == &vs_gem_prime_dmabuf_ops) { + obj = dma_buf->priv; + if (obj->dev == dev) { + drm_gem_object_get(obj); + return obj; + } + } + return drm_gem_prime_import_dev(dev, dma_buf, to_dma_dev(dev)); } -- 2.7.4 From 7c34e2ea4586e926c0458d4bbe524db68f907f04 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Wed, 19 Jul 2023 06:58:59 +0900 Subject: [PATCH 07/16] build: Change module image size from 32M to 20M Change module image size from 32M to 20M. In ks file, partitions size is using to 20M. If created to 30M, it will be failed on build system. So to check correct size, change module image size to 20M. Change-Id: I89cb828269e15f2162febacaf2f22386849b0f22 Signed-off-by: Jaehoon Chung --- build.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/build.sh b/build.sh index f66d4f8..3239bec 100755 --- a/build.sh +++ b/build.sh @@ -1,7 +1,7 @@ #!/bin/bash MOD_DIR="usr/tmp_mod" MOD_IMG="usr/modules.img" -MOD_SIZE=32 +MOD_SIZE=20 NCPUS=`grep ^processor /proc/cpuinfo | wc -l` NCPUS=$(($NCPUS * 2)) -- 2.7.4 From f58ab0cbdac47f571bc403d9808e2aed3253e876 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Mon, 26 Jun 2023 13:15:12 +0900 Subject: [PATCH 08/16] packaging: Update stable version to 6.1.39 Update stable version to 6.1.39. Change-Id: I0092fc745e6e968afa777d0fb409fc1f20d5e840 Signed-off-by: Jaehoon Chung --- packaging/linux-qemu.spec | 2 +- packaging/linux-riscv.spec.in | 2 +- packaging/linux-visionfive2.spec | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/packaging/linux-qemu.spec b/packaging/linux-qemu.spec index 9c6a982..5533e19 100644 --- a/packaging/linux-qemu.spec +++ b/packaging/linux-qemu.spec @@ -10,7 +10,7 @@ Name: %{variant}-linux-kernel Summary: The Linux Kernel for RISC-V %{target_board} -Version: 6.1.21 +Version: 6.1.39 Release: 0 License: GPL-2.0 ExclusiveArch: riscv64 diff --git a/packaging/linux-riscv.spec.in b/packaging/linux-riscv.spec.in index 13659a4..ea5ba6d 100644 --- a/packaging/linux-riscv.spec.in +++ b/packaging/linux-riscv.spec.in @@ -8,7 +8,7 @@ Name: %{variant}-linux-kernel Summary: The Linux Kernel for RISC-V %{target_board} -Version: 6.1.21 +Version: 6.1.39 Release: 0 License: GPL-2.0 ExclusiveArch: riscv64 diff --git a/packaging/linux-visionfive2.spec b/packaging/linux-visionfive2.spec index b2b4734..8bdec4c 100644 --- a/packaging/linux-visionfive2.spec +++ b/packaging/linux-visionfive2.spec @@ -10,7 +10,7 @@ Name: %{variant}-linux-kernel Summary: The Linux Kernel for RISC-V %{target_board} -Version: 6.1.32 +Version: 6.1.39 Release: 0 License: GPL-2.0 ExclusiveArch: riscv64 -- 2.7.4 From 44053e1eb3a522409564a59bd43f757520d069aa Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Wed, 26 Jul 2023 06:32:45 +0900 Subject: [PATCH 09/16] Revert "riscv: fix riscv64 unrecognized opcode build error" Since using gcc13 to build Tizen RISCV, this patch doesn't need anymore. This reverts commit e6c19c8fe08eb4375c7f5da1d7004ae4c533d615. Change-Id: Iea9421a0c53ac3f9a9d9a8942dbf5a1521b91665 --- arch/riscv/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 4114bda..3cb876f 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -55,7 +55,6 @@ endif riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd -riscv-march-y := $(subst imafd,g,$(riscv-march-y)) riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC -- 2.7.4 From a16ffa31a98812de35a1bd8b9c3a19d18e794b26 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Wed, 26 Jul 2023 10:50:50 +0900 Subject: [PATCH 10/16] gpu: drm: verisilicon: Fix potential Null pointer dereference It can be the poential NULL pointer dereference. [ 3.749753] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000008 [ 3.750873] starfive display-subsystem: bound 29400000.dc8200 (ops 0xffffffff812c3bc8) [ 3.758534] Oops [#1] [ 3.758538] Modules linked in: [ 3.758547] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 6.1.39-riscv-visionfive2 #1 [ 3.758555] Hardware name: StarFive VisionFive 2 v1.3B (DT) [ 3.758560] epc : dc_isr+0x22/0x60 [ 3.766483] innohdmi-starfive 29590000.hdmi: inno hdmi bind begin [ 3.768725] ra : dc_isr+0x22/0x60 [ 3.768734] epc : ffffffff806db7ee ra : ffffffff806db7ee sp : ffffffff81a03bf0 [ 3.768741] gp : ffffffff81c6a158 tp : ffffffff81a17900 t0 : 0000000000046000 [ 3.771834] innohdmi-starfive 29590000.hdmi: supply hdmi_1p8 not found, using dummy regulator Change-Id: I4a7c1f656f1d45c2fc183f2c2976a11e0b2816c1 Signed-off-by: Jaehoon Chung --- drivers/gpu/drm/verisilicon/vs_dc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisilicon/vs_dc.c index 12c09da..7c7b72c 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.c +++ b/drivers/gpu/drm/verisilicon/vs_dc.c @@ -806,6 +806,9 @@ static irqreturn_t dc_isr(int irq, void *data) struct vs_dc_info *dc_info = dc->hw.info; u32 i, ret; + if (!dc_info) + return IRQ_HANDLED; + ret = dc_hw_get_interrupt(&dc->hw); for (i = 0; i < dc_info->panel_num; i++) -- 2.7.4 From f8496c893debead6b5a75912946f048ed8c952a2 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Wed, 26 Jul 2023 20:32:55 +0900 Subject: [PATCH 11/16] soc: sifive: ccache: Add delay after flush Problems with cache flush at resolutions exceeding FUD and with inno hdmi driver. It runs a cache flush and requires a delay. So add delay after cache flush. Change-Id: Id8b1398dcce04851577912e6c1dfd4a2b580a043 Signed-off-by: Hoegeun Kwon --- drivers/soc/sifive/sifive_ccache.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 79de317..73c39c3 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -9,6 +9,9 @@ #define pr_fmt(fmt) "CCACHE: " fmt #include +#ifdef CONFIG_STARFIVE_INNO_HDMI +#include +#endif #include #include #include @@ -159,6 +162,13 @@ void sifive_flush64_range(unsigned long start, unsigned long len) writeq(line, ccache_base + SIFIVE_FLUSH64); mb(); } +#ifdef CONFIG_STARFIVE_INNO_HDMI + /* + * Problems with cache flush at resolutions exceeding FUD. + * It runs a cache flush and requires a delay. + */ + udelay(700); +#endif } EXPORT_SYMBOL_GPL(sifive_flush64_range); #endif -- 2.7.4 From 6a96d47eac5e1531e95fe461f6db12bb67ba3516 Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Tue, 1 Aug 2023 11:30:40 +0900 Subject: [PATCH 12/16] drm/verisilicon: vs_dc: Fix to disable interrupt on probe There is a case where interrupt enable is set in decon req before decon probe is completed. There is a problem that a kernel panic occurs if an interrupt is executed before the decon is bound. Disable interrupts before registering interrupts. Also, irq generated when the interrupt state is disabled is ignored. Change-Id: I8b3571b006031c28349e1647f2d9a5c508ca6235 Signed-off-by: Hoegeun Kwon --- drivers/gpu/drm/verisilicon/vs_dc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisilicon/vs_dc.c index 7c7b72c..0928846 100644 --- a/drivers/gpu/drm/verisilicon/vs_dc.c +++ b/drivers/gpu/drm/verisilicon/vs_dc.c @@ -810,6 +810,8 @@ static irqreturn_t dc_isr(int irq, void *data) return IRQ_HANDLED; ret = dc_hw_get_interrupt(&dc->hw); + if (!ret) + return IRQ_HANDLED; for (i = 0; i < dc_info->panel_num; i++) vs_crtc_handle_vblank(&dc->crtc[i]->base, dc_hw_check_underflow(&dc->hw)); @@ -1017,6 +1019,8 @@ static int dc_probe(struct platform_device *pdev) return ret; } + dc_hw_enable_interrupt(&dc->hw, 0); + irq = platform_get_irq(pdev, 0); ret = devm_request_irq(dev, irq, dc_isr, 0, dev_name(dev), dc); -- 2.7.4 From 318060a046ba65f7086477ffa799a23fb63dc005 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=C5=81ukasz=20Stelmach?= Date: Tue, 1 Aug 2023 15:03:49 +0200 Subject: [PATCH 13/16] RISCV: config: Enable RAM and NBD block devices MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Devices are supported on VisionFive2. Enable them on QEMU to use the same boot procedures on both targets. Change-Id: I210141b471d718fec4286a7bb516751226756f96 Signed-off-by: Łukasz Stelmach --- arch/riscv/configs/tizen_qemu_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/configs/tizen_qemu_defconfig b/arch/riscv/configs/tizen_qemu_defconfig index 3b66a9b..7877275 100644 --- a/arch/riscv/configs/tizen_qemu_defconfig +++ b/arch/riscv/configs/tizen_qemu_defconfig @@ -39,6 +39,9 @@ CONFIG_PCI_HOST_GENERIC=y CONFIG_PCIE_XILINX=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=32768 CONFIG_BLK_DEV_LOOP=y CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_SD=y -- 2.7.4 From 0f92872fada68d75f031a9851e5ed76749fe6828 Mon Sep 17 00:00:00 2001 From: Seung-Woo Kim Date: Thu, 3 Aug 2023 11:00:55 +0900 Subject: [PATCH 14/16] RISCV: config: Enable MEDIA_SUPPORT_FILTER and enable only usb camera configs Enable MEDIA_SUPPORT_FILTER to filter out unnecessary media configs and enable only usb camera configs including gspca module. Change-Id: Idcd217d10821467562a53a57c3783897b4363d5f Signed-off-by: Seung-Woo Kim --- arch/riscv/configs/tizen_visionfive2_defconfig | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/riscv/configs/tizen_visionfive2_defconfig b/arch/riscv/configs/tizen_visionfive2_defconfig index 32d7896..78c452e 100644 --- a/arch/riscv/configs/tizen_visionfive2_defconfig +++ b/arch/riscv/configs/tizen_visionfive2_defconfig @@ -280,10 +280,14 @@ CONFIG_WATCHDOG=y CONFIG_MFD_AXP20X_I2C=y CONFIG_REGULATOR=y CONFIG_REGULATOR_AXP20X=y -# CONFIG_MEDIA_CEC_SUPPORT is not set CONFIG_MEDIA_SUPPORT=y -CONFIG_VIDEO_DEV=m -# CONFIG_CXD2880_SPI_DRV is not set +CONFIG_MEDIA_SUPPORT_FILTER=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_VIDEO_CLASS=y CONFIG_DRM_I2C_CH7006=m CONFIG_DRM_I2C_SIL164=m CONFIG_DRM_VERISILICON=y -- 2.7.4 From e750d985a70a0ceab8166131c39a73b962f91fd6 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Tue, 8 Aug 2023 14:18:43 +0900 Subject: [PATCH 15/16] RISCV: dts: starfive: Fix the property of memory Current is getting the memory size from devicetree node. Until supporting eeprom, it needs to use the memory node. After applied this patch, Visionfive2 is showing 8GiB. Change-Id: Ic96c2a7d373b9fccee830f3e34bbd9a2d6a3d6c3 Signed-off-by: Jaehoon Chung --- arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index d81366a..1a8db60 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -32,7 +32,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x0 0x40000000 0x1 0x0>; + reg = <0x0 0x40000000 0x2 0x0>; }; thermal-zones { -- 2.7.4 From 93bbef15eb5096b416b130444f6383e353dbd00f Mon Sep 17 00:00:00 2001 From: Hoegeun Kwon Date: Wed, 9 Aug 2023 11:17:00 +0900 Subject: [PATCH 16/16] RISCV: dts: starfive: Increase CMA range from 512MB to 768MB In UHD resolution, there are many cases where alloc fail due to lack of CMA capacity. Increase CMA range to prevent cma_alloc failed. Change-Id: I6b0c355b773b08d09381e738329b986113982768 Signed-off-by: Hoegeun Kwon --- arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 1a8db60..3968ed7 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -71,9 +71,9 @@ linux,cma { compatible = "shared-dma-pool"; reusable; - size = <0x0 0x20000000>; + size = <0x0 0x30000000>; alignment = <0x0 0x1000>; - alloc-ranges = <0x0 0x80000000 0x0 0x20000000>; + alloc-ranges = <0x0 0x80000000 0x0 0x30000000>; linux,cma-default; }; }; -- 2.7.4