From cfd70d7afcc22e28bfce8805d7de1e5f759fed8b Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Mon, 24 Dec 2012 15:08:29 +0800 Subject: [PATCH] Discard the intermediate result during VME prediction on haswell There is no functional change. It is only to avoid writing the intermediate result of VME prediction. Signed-off-by: Zhao Yakui --- src/gen75_mfc.c | 6 +-- src/shaders/vme/inter_frame_haswell.asm | 77 -------------------------------- src/shaders/vme/inter_frame_haswell.g75b | 18 -------- 3 files changed, 3 insertions(+), 98 deletions(-) diff --git a/src/gen75_mfc.c b/src/gen75_mfc.c index f876953..d8007db 100644 --- a/src/gen75_mfc.c +++ b/src/gen75_mfc.c @@ -1142,9 +1142,9 @@ gen75_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, i } #define INTRA_RDO_OFFSET 4 -#define INTER_RDO_OFFSET 54 -#define INTER_MSG_OFFSET 52 -#define INTER_MV_OFFSET 224 +#define INTER_RDO_OFFSET 10 +#define INTER_MSG_OFFSET 8 +#define INTER_MV_OFFSET 48 #define RDO_MASK 0xFFFF static void diff --git a/src/shaders/vme/inter_frame_haswell.asm b/src/shaders/vme/inter_frame_haswell.asm index 80df800..5bb8ba7 100644 --- a/src/shaders/vme/inter_frame_haswell.asm +++ b/src/shaders/vme/inter_frame_haswell.asm @@ -239,83 +239,6 @@ mov (1) vme_m2.22<1>:UB vme_wb.26<0,1,0>:UB {align1}; and (1) tmp_reg0.0<1>:UW vme_wb.0<0,1,0>:UW 0x03:UW {align1}; mov (1) vme_m2.20<1>:UB tmp_reg0.0<0,1,0>:UB {align1}; -/* Write IME inter info */ -add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x02:UD {align1}; -mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; - -mov (1) msg_reg1.0<1>:UD vme_wb.0<0,1,0>:UD {align1}; - -mov (1) msg_reg1.4<1>:UD vme_wb.24<0,1,0>:UD {align1}; -/* Inter distortion of IME */ -mov (1) msg_reg1.8<1>:UD vme_wb.8<0,1,0>:UD {align1}; - -mov (1) msg_reg1.12<1>:UD obw_m0.8<0,1,0>:UD {align1}; - -/* bind index 3, write oword (16bytes), msg type: 8(OWord Block Write) */ -send (16) - msg_ind - obw_wb - null - data_port( - OBW_CACHE_TYPE, - OBW_MESSAGE_TYPE, - OBW_CONTROL_0, - OBW_BIND_IDX, - OBW_WRITE_COMMIT_CATEGORY, - OBW_HEADER_PRESENT - ) - mlen 2 - rlen obw_wb_length - {align1}; - -/* Write IME MV */ -add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x01:UD {align1}; -mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; - -mov (8) msg_reg1.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; -mov (8) msg_reg2.0<1>:ud vme_wb2.0<8,8,1>:ud {align1}; -mov (8) msg_reg3.0<1>:ud vme_wb3.0<8,8,1>:ud {align1}; -mov (8) msg_reg4.0<1>:ud vme_wb4.0<8,8,1>:ud {align1}; -/* bind index 3, write 8 oword (128 bytes), msg type: 8(OWord Block Write) */ -send (16) - msg_ind - obw_wb - null - data_port( - OBW_CACHE_TYPE, - OBW_MESSAGE_TYPE, - OBW_CONTROL_8, - OBW_BIND_IDX, - OBW_WRITE_COMMIT_CATEGORY, - OBW_HEADER_PRESENT - ) - mlen 5 - rlen obw_wb_length - {align1}; - -/* Write IME RefID */ -add (1) obw_m0.8<1>:UD obw_m0.8<0,1,0>:UD 0x08:UD {align1}; -mov (8) msg_reg0.0<1>:UD obw_m0<8,8,1>:UD {align1}; - -mov (8) msg_reg1.0<1>:UD vme_wb6.0<8,8,1>:UD {align1}; - -/* bind index 3, write 2 oword (32bytes), msg type: 8(OWord Block Write) */ -send (16) - msg_ind - obw_wb - null - data_port( - OBW_CACHE_TYPE, - OBW_MESSAGE_TYPE, - OBW_CONTROL_2, - OBW_BIND_IDX, - OBW_WRITE_COMMIT_CATEGORY, - OBW_HEADER_PRESENT - ) - mlen 2 - rlen obw_wb_length - {align1}; - /* Send FBR message into CRE */ mov (8) vme_msg_3.0<1>:UD vme_wb1.0<8,8,1>:UD {align1}; diff --git a/src/shaders/vme/inter_frame_haswell.g75b b/src/shaders/vme/inter_frame_haswell.g75b index 2e240b7..5ae0aad 100644 --- a/src/shaders/vme/inter_frame_haswell.g75b +++ b/src/shaders/vme/inter_frame_haswell.g75b @@ -102,24 +102,6 @@ { 0x00000001, 0x25760231, 0x0000019a, 0x00000000 }, { 0x00000005, 0x24002d29, 0x00000180, 0x00030003 }, { 0x00000001, 0x25740231, 0x00000400, 0x00000000 }, - { 0x00000040, 0x24880c21, 0x00000488, 0x00000002 }, - { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, - { 0x00000001, 0x28200021, 0x00000180, 0x00000000 }, - { 0x00000001, 0x28240021, 0x00000198, 0x00000000 }, - { 0x00000001, 0x28280021, 0x00000188, 0x00000000 }, - { 0x00000001, 0x282c0021, 0x00000488, 0x00000000 }, - { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0003 }, - { 0x00000040, 0x24880c21, 0x00000488, 0x00000001 }, - { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, - { 0x00600001, 0x28200021, 0x008d01a0, 0x00000000 }, - { 0x00600001, 0x28400021, 0x008d01c0, 0x00000000 }, - { 0x00600001, 0x28600021, 0x008d01e0, 0x00000000 }, - { 0x00600001, 0x28800021, 0x008d0200, 0x00000000 }, - { 0x0a800031, 0x20001cac, 0x00000800, 0x0a0a0403 }, - { 0x00000040, 0x24880c21, 0x00000488, 0x00000008 }, - { 0x00600001, 0x28000021, 0x008d0480, 0x00000000 }, - { 0x00600001, 0x28200021, 0x008d0240, 0x00000000 }, - { 0x0a800031, 0x20001cac, 0x00000800, 0x040a0203 }, { 0x00600001, 0x28600021, 0x008d01a0, 0x00000000 }, { 0x00600001, 0x28800021, 0x008d01c0, 0x00000000 }, { 0x00600001, 0x28a00021, 0x008d01e0, 0x00000000 }, -- 2.7.4