From fe7dab14d2608103b4ce8d905241f39f30634999 Mon Sep 17 00:00:00 2001 From: HyungKyu Song Date: Sat, 16 Feb 2013 00:18:53 +0900 Subject: [PATCH] Tizen 2.0 Release --- AUTHORS | 5 + COPYING | 18 + ChangeLog | 0 Makefile.am | 84 + README | 41 + RELEASING | 66 + autogen.sh | 6 + build.sh | 42 + configure.ac | 372 +++ exynos/Makefile.am | 22 + exynos/exynos_drm.c | 427 ++++ exynos/exynos_drm.h | 566 +++++ exynos/exynos_drmif.h | 90 + exynos/libdrm_exynos.pc.in | 11 + include/Makefile.am | 1 + include/drm/Makefile.am | 44 + include/drm/drm.h | 823 +++++++ include/drm/drm_fourcc.h | 130 ++ include/drm/drm_mode.h | 467 ++++ include/drm/drm_sarea.h | 82 + include/drm/i810_drm.h | 281 +++ include/drm/i830_drm.h | 342 +++ include/drm/i915_drm.h | 892 +++++++ include/drm/mach64_drm.h | 256 +++ include/drm/mga_drm.h | 419 ++++ include/drm/nouveau_drm.h | 208 ++ include/drm/r128_drm.h | 326 +++ include/drm/radeon_drm.h | 926 ++++++++ include/drm/savage_drm.h | 210 ++ include/drm/sis_drm.h | 67 + include/drm/via_drm.h | 275 +++ include/drm/vmwgfx_drm.h | 614 +++++ intel/.gitignore | 1 + intel/Makefile.am | 82 + intel/intel_aub.h | 123 + intel/intel_bufmgr.c | 321 +++ intel/intel_bufmgr.h | 275 +++ intel/intel_bufmgr_fake.c | 1633 +++++++++++++ intel/intel_bufmgr_gem.c | 2989 ++++++++++++++++++++++++ intel/intel_bufmgr_priv.h | 287 +++ intel/intel_chipset.h | 157 ++ intel/intel_debug.h | 44 + intel/intel_decode.c | 3956 ++++++++++++++++++++++++++++++++ intel/libdrm_intel.pc.in | 11 + intel/mm.c | 271 +++ intel/mm.h | 94 + intel/test_decode.c | 191 ++ intel/tests/.gitignore | 1 + intel/tests/gen4-3d.batch | Bin 0 -> 1952 bytes intel/tests/gen4-3d.batch-ref.txt | 488 ++++ intel/tests/gen4-3d.batch.sh | 20 + intel/tests/gen5-3d.batch | Bin 0 -> 2048 bytes intel/tests/gen5-3d.batch-ref.txt | 512 +++++ intel/tests/gen5-3d.batch.sh | 20 + intel/tests/gen6-3d.batch | Bin 0 -> 3960 bytes intel/tests/gen6-3d.batch-ref.txt | 990 ++++++++ intel/tests/gen6-3d.batch.sh | 20 + intel/tests/gen7-2d-copy.batch | Bin 0 -> 56 bytes intel/tests/gen7-2d-copy.batch-ref.txt | 14 + intel/tests/gen7-2d-copy.batch.sh | 20 + intel/tests/gen7-3d.batch | Bin 0 -> 848 bytes intel/tests/gen7-3d.batch-ref.txt | 212 ++ intel/tests/gen7-3d.batch.sh | 20 + intel/tests/gm45-3d.batch | Bin 0 -> 1952 bytes intel/tests/gm45-3d.batch-ref.txt | 488 ++++ intel/tests/gm45-3d.batch.sh | 20 + intel/tests/test-batch.sh | 20 + libdrm.pc.in | 10 + libdrm_lists.h | 118 + libkms/Makefile.am | 45 + libkms/api.c | 138 ++ libkms/dumb.c | 221 ++ libkms/intel.c | 238 ++ libkms/internal.h | 77 + libkms/libkms.h | 74 + libkms/libkms.pc.in | 10 + libkms/linux.c | 226 ++ libkms/nouveau.c | 220 ++ libkms/radeon.c | 242 ++ libkms/slp.c | 222 ++ libkms/vmwgfx.c | 207 ++ m4/.gitignore | 5 + nouveau/Makefile.am | 25 + nouveau/abi16.c | 198 ++ nouveau/bufctx.c | 170 ++ nouveau/libdrm_nouveau.pc.in | 11 + nouveau/nouveau.c | 492 ++++ nouveau/nouveau.h | 212 ++ nouveau/private.h | 122 + nouveau/pushbuf.c | 771 +++++++ omap/Makefile.am | 22 + omap/libdrm_omap.pc.in | 11 + omap/omap_drm.c | 331 +++ omap/omap_drm.h | 134 ++ omap/omap_drmif.h | 62 + packaging/libdrm.spec | 93 + radeon/Makefile.am | 61 + radeon/bof.c | 477 ++++ radeon/bof.h | 90 + radeon/libdrm_radeon.pc.in | 10 + radeon/r600_pci_ids.h | 353 +++ radeon/radeon_bo.c | 141 ++ radeon/radeon_bo.h | 74 + radeon/radeon_bo_gem.c | 351 +++ radeon/radeon_bo_gem.h | 44 + radeon/radeon_bo_int.h | 45 + radeon/radeon_cs.c | 96 + radeon/radeon_cs.h | 141 ++ radeon/radeon_cs_gem.c | 548 +++++ radeon/radeon_cs_gem.h | 41 + radeon/radeon_cs_int.h | 67 + radeon/radeon_cs_space.c | 245 ++ radeon/radeon_surface.c | 1025 +++++++++ radeon/radeon_surface.h | 114 + slp/Makefile.am | 22 + slp/drm_slp_bufmgr.c | 850 +++++++ slp/drm_slp_bufmgr.h | 201 ++ slp/libdrm_slp.pc.in | 11 + slp/list.h | 131 ++ tests/Makefile.am | 64 + tests/auth.c | 137 ++ tests/dristat.c | 280 +++ tests/drmstat.c | 435 ++++ tests/drmtest.c | 135 ++ tests/drmtest.h | 40 + tests/gem_basic.c | 102 + tests/gem_flink.c | 137 ++ tests/gem_mmap.c | 136 ++ tests/gem_readwrite.c | 139 ++ tests/getclient.c | 60 + tests/getstats.c | 51 + tests/getversion.c | 48 + tests/kmstest/Makefile.am | 17 + tests/kmstest/main.c | 91 + tests/lock.c | 263 +++ tests/modeprint/Makefile.am | 11 + tests/modeprint/modeprint.c | 403 ++++ tests/modetest/Makefile.am | 15 + tests/modetest/modetest.c | 1245 ++++++++++ tests/name_from_fd.c | 58 + tests/openclose.c | 37 + tests/proptest/Makefile.am | 11 + tests/proptest/proptest.c | 361 +++ tests/radeon/Makefile.am | 14 + tests/radeon/list.h | 137 ++ tests/radeon/radeon_ttm.c | 75 + tests/radeon/rbo.c | 171 ++ tests/radeon/rbo.h | 50 + tests/rottest/Makefile.am | 21 + tests/rottest/gem.c | 92 + tests/rottest/gem.h | 12 + tests/rottest/rotator.c | 297 +++ tests/rottest/rotator.h | 7 + tests/rottest/rottest.c | 460 ++++ tests/rottest/rottest.h | 25 + tests/rottest/util.c | 132 ++ tests/rottest/util.h | 12 + tests/setversion.c | 89 + tests/ttmtest/AUTHORS | 1 + tests/ttmtest/ChangeLog | 23 + tests/ttmtest/Makefile.am | 1 + tests/ttmtest/NEWS | 0 tests/ttmtest/README | 0 tests/ttmtest/configure.ac | 33 + tests/ttmtest/reconf | 2 + tests/ttmtest/src/Makefile.am | 8 + tests/ttmtest/src/ttmtest.c | 430 ++++ tests/ttmtest/src/xf86dri.c | 603 +++++ tests/ttmtest/src/xf86dri.h | 116 + tests/ttmtest/src/xf86dristr.h | 390 ++++ tests/updatedraw.c | 153 ++ tests/vbltest/Makefile.am | 11 + tests/vbltest/vbltest.c | 200 ++ xf86atomic.h | 99 + xf86drm.c | 2544 ++++++++++++++++++++ xf86drm.h | 734 ++++++ xf86drmHash.c | 428 ++++ xf86drmMode.c | 1059 +++++++++ xf86drmMode.h | 451 ++++ xf86drmRandom.c | 208 ++ xf86drmSL.c | 477 ++++ xf86mm.h | 198 ++ 182 files changed, 45277 insertions(+) create mode 100644 AUTHORS create mode 100644 COPYING create mode 100644 ChangeLog create mode 100644 Makefile.am create mode 100644 README create mode 100644 RELEASING create mode 100644 autogen.sh create mode 100644 build.sh create mode 100644 configure.ac create mode 100644 exynos/Makefile.am create mode 100644 exynos/exynos_drm.c create mode 100644 exynos/exynos_drm.h create mode 100644 exynos/exynos_drmif.h create mode 100644 exynos/libdrm_exynos.pc.in create mode 100644 include/Makefile.am create mode 100644 include/drm/Makefile.am create mode 100644 include/drm/drm.h create mode 100644 include/drm/drm_fourcc.h create mode 100644 include/drm/drm_mode.h create mode 100644 include/drm/drm_sarea.h create mode 100644 include/drm/i810_drm.h create mode 100644 include/drm/i830_drm.h create mode 100644 include/drm/i915_drm.h create mode 100644 include/drm/mach64_drm.h create mode 100644 include/drm/mga_drm.h create mode 100644 include/drm/nouveau_drm.h create mode 100644 include/drm/r128_drm.h create mode 100644 include/drm/radeon_drm.h create mode 100644 include/drm/savage_drm.h create mode 100644 include/drm/sis_drm.h create mode 100644 include/drm/via_drm.h create mode 100644 include/drm/vmwgfx_drm.h create mode 100644 intel/.gitignore create mode 100644 intel/Makefile.am create mode 100644 intel/intel_aub.h create mode 100644 intel/intel_bufmgr.c create mode 100644 intel/intel_bufmgr.h create mode 100644 intel/intel_bufmgr_fake.c create mode 100644 intel/intel_bufmgr_gem.c create mode 100644 intel/intel_bufmgr_priv.h create mode 100644 intel/intel_chipset.h create mode 100644 intel/intel_debug.h create mode 100644 intel/intel_decode.c create mode 100644 intel/libdrm_intel.pc.in create mode 100644 intel/mm.c create mode 100644 intel/mm.h create mode 100644 intel/test_decode.c create mode 100644 intel/tests/.gitignore create mode 100644 intel/tests/gen4-3d.batch create mode 100644 intel/tests/gen4-3d.batch-ref.txt create mode 100644 intel/tests/gen4-3d.batch.sh create mode 100644 intel/tests/gen5-3d.batch create mode 100644 intel/tests/gen5-3d.batch-ref.txt create mode 100644 intel/tests/gen5-3d.batch.sh create mode 100644 intel/tests/gen6-3d.batch create mode 100644 intel/tests/gen6-3d.batch-ref.txt create mode 100644 intel/tests/gen6-3d.batch.sh create mode 100644 intel/tests/gen7-2d-copy.batch create mode 100644 intel/tests/gen7-2d-copy.batch-ref.txt create mode 100644 intel/tests/gen7-2d-copy.batch.sh create mode 100644 intel/tests/gen7-3d.batch create mode 100644 intel/tests/gen7-3d.batch-ref.txt create mode 100644 intel/tests/gen7-3d.batch.sh create mode 100644 intel/tests/gm45-3d.batch create mode 100644 intel/tests/gm45-3d.batch-ref.txt create mode 100644 intel/tests/gm45-3d.batch.sh create mode 100644 intel/tests/test-batch.sh create mode 100644 libdrm.pc.in create mode 100644 libdrm_lists.h create mode 100644 libkms/Makefile.am create mode 100644 libkms/api.c create mode 100644 libkms/dumb.c create mode 100644 libkms/intel.c create mode 100644 libkms/internal.h create mode 100644 libkms/libkms.h create mode 100644 libkms/libkms.pc.in create mode 100644 libkms/linux.c create mode 100644 libkms/nouveau.c create mode 100644 libkms/radeon.c create mode 100644 libkms/slp.c create mode 100644 libkms/vmwgfx.c create mode 100644 m4/.gitignore create mode 100644 nouveau/Makefile.am create mode 100644 nouveau/abi16.c create mode 100644 nouveau/bufctx.c create mode 100644 nouveau/libdrm_nouveau.pc.in create mode 100644 nouveau/nouveau.c create mode 100644 nouveau/nouveau.h create mode 100644 nouveau/private.h create mode 100644 nouveau/pushbuf.c create mode 100644 omap/Makefile.am create mode 100644 omap/libdrm_omap.pc.in create mode 100644 omap/omap_drm.c create mode 100644 omap/omap_drm.h create mode 100644 omap/omap_drmif.h create mode 100644 packaging/libdrm.spec create mode 100644 radeon/Makefile.am create mode 100644 radeon/bof.c create mode 100644 radeon/bof.h create mode 100644 radeon/libdrm_radeon.pc.in create mode 100644 radeon/r600_pci_ids.h create mode 100644 radeon/radeon_bo.c create mode 100644 radeon/radeon_bo.h create mode 100644 radeon/radeon_bo_gem.c create mode 100644 radeon/radeon_bo_gem.h create mode 100644 radeon/radeon_bo_int.h create mode 100644 radeon/radeon_cs.c create mode 100644 radeon/radeon_cs.h create mode 100644 radeon/radeon_cs_gem.c create mode 100644 radeon/radeon_cs_gem.h create mode 100644 radeon/radeon_cs_int.h create mode 100644 radeon/radeon_cs_space.c create mode 100644 radeon/radeon_surface.c create mode 100644 radeon/radeon_surface.h create mode 100644 slp/Makefile.am create mode 100644 slp/drm_slp_bufmgr.c create mode 100644 slp/drm_slp_bufmgr.h create mode 100644 slp/libdrm_slp.pc.in create mode 100644 slp/list.h create mode 100644 tests/Makefile.am create mode 100644 tests/auth.c create mode 100644 tests/dristat.c create mode 100644 tests/drmstat.c create mode 100644 tests/drmtest.c create mode 100644 tests/drmtest.h create mode 100644 tests/gem_basic.c create mode 100644 tests/gem_flink.c create mode 100644 tests/gem_mmap.c create mode 100644 tests/gem_readwrite.c create mode 100644 tests/getclient.c create mode 100644 tests/getstats.c create mode 100644 tests/getversion.c create mode 100644 tests/kmstest/Makefile.am create mode 100644 tests/kmstest/main.c create mode 100644 tests/lock.c create mode 100644 tests/modeprint/Makefile.am create mode 100644 tests/modeprint/modeprint.c create mode 100644 tests/modetest/Makefile.am create mode 100644 tests/modetest/modetest.c create mode 100644 tests/name_from_fd.c create mode 100644 tests/openclose.c create mode 100644 tests/proptest/Makefile.am create mode 100644 tests/proptest/proptest.c create mode 100644 tests/radeon/Makefile.am create mode 100644 tests/radeon/list.h create mode 100644 tests/radeon/radeon_ttm.c create mode 100644 tests/radeon/rbo.c create mode 100644 tests/radeon/rbo.h create mode 100644 tests/rottest/Makefile.am create mode 100644 tests/rottest/gem.c create mode 100644 tests/rottest/gem.h create mode 100644 tests/rottest/rotator.c create mode 100644 tests/rottest/rotator.h create mode 100644 tests/rottest/rottest.c create mode 100644 tests/rottest/rottest.h create mode 100644 tests/rottest/util.c create mode 100644 tests/rottest/util.h create mode 100644 tests/setversion.c create mode 100644 tests/ttmtest/AUTHORS create mode 100644 tests/ttmtest/ChangeLog create mode 100644 tests/ttmtest/Makefile.am create mode 100644 tests/ttmtest/NEWS create mode 100644 tests/ttmtest/README create mode 100644 tests/ttmtest/configure.ac create mode 100644 tests/ttmtest/reconf create mode 100644 tests/ttmtest/src/Makefile.am create mode 100644 tests/ttmtest/src/ttmtest.c create mode 100644 tests/ttmtest/src/xf86dri.c create mode 100644 tests/ttmtest/src/xf86dri.h create mode 100644 tests/ttmtest/src/xf86dristr.h create mode 100644 tests/updatedraw.c create mode 100644 tests/vbltest/Makefile.am create mode 100644 tests/vbltest/vbltest.c create mode 100644 xf86atomic.h create mode 100644 xf86drm.c create mode 100644 xf86drm.h create mode 100644 xf86drmHash.c create mode 100644 xf86drmMode.c create mode 100644 xf86drmMode.h create mode 100644 xf86drmRandom.c create mode 100644 xf86drmSL.c create mode 100644 xf86mm.h diff --git a/AUTHORS b/AUTHORS new file mode 100644 index 0000000..55581aa --- /dev/null +++ b/AUTHORS @@ -0,0 +1,5 @@ +Rickard E. (Rik) Faith +Kevin E. Martin +SangJin Lee +SooChan Lim +Boram Park diff --git a/COPYING b/COPYING new file mode 100644 index 0000000..8d597e5 --- /dev/null +++ b/COPYING @@ -0,0 +1,18 @@ +Copyright (C) 2000 - 2011 Samsung Electronics co., Ltd. All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is fur- +nished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FIT- +NESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +XFREE86 PROJECT BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CON- +NECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/ChangeLog b/ChangeLog new file mode 100644 index 0000000..e69de29 diff --git a/Makefile.am b/Makefile.am new file mode 100644 index 0000000..6e74607 --- /dev/null +++ b/Makefile.am @@ -0,0 +1,84 @@ +# Copyright 2005 Adam Jackson. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# on the rights to use, copy, modify, merge, publish, distribute, sub +# license, and/or sell copies of the Software, and to permit persons to whom +# the Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +ACLOCAL_AMFLAGS = -I m4 ${ACLOCAL_FLAGS} + +DISTCHECK_CONFIGURE_FLAGS = --enable-nouveau-experimental-api --enable-radeon-experimental-api + +pkgconfigdir = @pkgconfigdir@ +pkgconfig_DATA = libdrm.pc + +if HAVE_LIBKMS +LIBKMS_SUBDIR = libkms +endif + +if HAVE_INTEL +INTEL_SUBDIR = intel +endif + +if HAVE_NOUVEAU +NOUVEAU_SUBDIR = nouveau +endif + +if HAVE_RADEON +RADEON_SUBDIR = radeon +endif + +if HAVE_OMAP +OMAP_SUBDIR = omap +endif + +if HAVE_EXYNOS +EXYNOS_SUBDIR = exynos +endif + +if HAVE_SLP +SLP_SUBDIR = slp +endif + +SUBDIRS = . $(LIBKMS_SUBDIR) $(INTEL_SUBDIR) $(NOUVEAU_SUBDIR) $(RADEON_SUBDIR) $(OMAP_SUBDIR) $(EXYNOS_SUBDIR) $(SLP_SUBDIR) tests include + +libdrm_la_LTLIBRARIES = libdrm.la +libdrm_ladir = $(libdir) +libdrm_la_LDFLAGS = -version-number 2:4:0 -no-undefined +libdrm_la_LIBADD = @CLOCK_LIB@ + +libdrm_la_CPPFLAGS = -I$(top_srcdir)/include/drm + +libdrm_la_SOURCES = \ + xf86drm.c \ + xf86drmHash.c \ + xf86drmRandom.c \ + xf86drmSL.c \ + xf86drmMode.c \ + xf86atomic.h \ + libdrm_lists.h + +libdrmincludedir = ${includedir} +libdrminclude_HEADERS = xf86drm.h xf86drmMode.h + +EXTRA_DIST = libdrm.pc.in include/drm/* + +copy-headers : + cp -r $(kernel_source)/usr/include/drm $(top_srcdir)/include + +commit-headers : copy-headers + git add include + git commit -am "Copy headers from kernel $$(GIT_DIR=$(kernel_source)/.git git describe)" diff --git a/README b/README new file mode 100644 index 0000000..603a1c1 --- /dev/null +++ b/README @@ -0,0 +1,41 @@ +libdrm - userspace library for drm + +This is libdrm, a userspace library for accessing the DRM, direct +rendering manager, on Linux, BSD and other operating systes that +support the ioctl interface. The library provides wrapper functions +for the ioctls to avoid exposing the kernel interface directly, and +for chipsets with drm memory manager, support for tracking relocations +and buffers. libdrm is a low-level library, typically used by +graphics drivers such as the Mesa DRI drivers, the X drivers, libva +and similar projects. New functionality in the kernel DRM drivers +typically requires a new libdrm, but a new libdrm will always work +with an older kernel. + + +Compiling +--------- + +libdrm is a standard autotools packages and follows the normal +configure, build and install steps. The first step is to configure +the package, which is done by running the configure shell script: + + ./configure + +By default, libdrm will install into the /usr/local/ prefix. If you +want to install this DRM to replace your system copy, pass +--prefix=/usr and --exec-prefix=/ to configure. If you are building +libdrm from a git checkout, you first need to run the autogen.sh +script. You can pass any options to autogen.sh that you would other +wise pass to configure, or you can just re-run configure with the +options you need once autogen.sh finishes. + +Next step is to build libdrm: + + make + +and once make finishes successfully, install the package using + + make install + +If you are install into a system location, you will need to be root to +perform the install step. diff --git a/RELEASING b/RELEASING new file mode 100644 index 0000000..3f07146 --- /dev/null +++ b/RELEASING @@ -0,0 +1,66 @@ +The release criteria for libdrm is essentially "if you need a release, +make one". There is no designated release engineer or maintainer. +Anybody is free to make a release if there's a certain feature or bug +fix they need in a released version of libdrm. + +When new ioctl definitions are merged into drm-next, we will add +support to libdrm, at which point we typically create a new release. +However, this is up to whoever is driving the feature in question. + +Follow these steps to release a new version of libdrm: + + 1) Ensure that there are no local, uncommitted/unpushed + modifications. You're probably in a good state if both "git diff + HEAD" and "git log master..origin/master" give no output. + + 3) Bump the version number in configure.ac. We seem to have settled + for 2.4.x as the versioning scheme for libdrm, so just bump the + micro version. + + 4) Run autoconf and then re-run ./configure so the build system + picks up the new version number. + + 5) Verify that the code passes "make distcheck". libdrm is tricky + to distcheck since the test suite will need to become drm master. + This means that you need to run it outside X, that is, in text + mode (KMS or no KMS doesn't matter). + + Running "make distcheck" should result in no warnings or errors + and end with a message of the form: + + ============================================= + libdrm-X.Y.Z archives ready for distribution: + libdrm-X.Y.Z.tar.gz + libdrm-X.Y.Z.tar.bz2 + ============================================= + + Make sure that the version number reported by distcheck and in + the tarball names matches the number you bumped to in configure.ac. + + 6) Commit the configure.ac change and make an annotated tag for that + commit with the version number of the release as the name and a + message of "libdrm X.Y.Z". For example, for the 2.4.16 release + the command is: + + git tag -a 2.4.16 -m "libdrm 2.4.16" + + 7) Push the commit and tag by saying + + git push --tags origin master + + assuming the remote for the upstream libdrm repo is called origin. + + 6) Use the release.sh script from the xorg/util/modular repo to + upload the tarballs to the freedesktop.org download area and + create an annouce email template. The script takes three + arguments: a "section", the previous tag and the new tag we just + created. For 2.4.16 again, the command is: + + ../modular/release.sh libdrm 2.4.15 2.4.16 + + This copies the two tarballs to freedesktop.org and creates + libdrm-2.4.16.announce which has a detailed summary of the + changes, links to the tarballs, MD5 and SHA1 sums and pre-filled + out email headers. Fill out the blank between the email headers + and the list of changes with a brief message of what changed or + what prompted this release. Send out the email and you're done! diff --git a/autogen.sh b/autogen.sh new file mode 100644 index 0000000..30d679f --- /dev/null +++ b/autogen.sh @@ -0,0 +1,6 @@ +#! /bin/sh + +test -n "$srcdir" || srcdir=`dirname "$0"` +test -n "$srcdir" || srcdir=. +autoreconf --force --install --verbose "$srcdir" +test -n "$NOCONFIGURE" || "$srcdir/configure" "$@" diff --git a/build.sh b/build.sh new file mode 100644 index 0000000..c31e652 --- /dev/null +++ b/build.sh @@ -0,0 +1,42 @@ +#!/bin/sh + +USER=`whoami` +PREFIX=/usr/local/build +KERNEL_DIR=/home/pub/git/party/linux-mobile +CROSS_COMPILER="/opt/toolchains/arm-linux-link/bin/arm-none-linux-gnueabi-" + +if [ "$USER" = "dofmind" ]; then + PREFIX=/usr/local/build + KERNEL_DIR=/home/pub/git/gerrit/linux-2.6 + CROSS_COMPILER="/opt/toolchains/arm-linux-link/bin/arm-none-linux-gnueabi-" +fi +if [ "$USER" = "daeinki" ]; then + PREFIX=/home/daeinki/project/share + KERNEL_DIR=/home/daeinki/project/s5pc210/linux-mobile + CROSS_COMPILER="/usr/local/arm/arm-2009q3-93/bin/arm-none-linux-gnueabi-" +fi + +HOST="`echo $CROSS_COMPILER | sed 's/.*bin\///' | sed 's/-$//'`" + +make distclean +./autogen.sh +./configure --host=$HOST --prefix=$PREFIX --disable-intel --disable-radeon --enable-exynos-experimental-api --with-kernel-source=$KERNEL_DIR + +sudo rm -rf $PREFIX +sudo mkdir -p $PREFIX +sudo chown $USER.$USER $PREFIX + +make +make install + +mkdir $PREFIX/bin +cp -a ./tests/gemtest/.libs/gemtest $PREFIX/bin +cp -a ./tests/kmstest/.libs/kmstest $PREFIX/bin +cp -a ./tests/modeprint/.libs/modeprint $PREFIX/bin +cp -a ./tests/modetest/.libs/modetest $PREFIX/bin +cp -a ./tests/proptest/.libs/proptest $PREFIX/bin +cp -a ./tests/ipptest/.libs/ipptest $PREFIX/bin +cp -a ./tests/g2dtest/.libs/g2dtest $PREFIX/bin +cp -a ./tests/rottest/.libs/rottest $PREFIX/bin + +tar zcvf libdrm.tar.gz $PREFIX diff --git a/configure.ac b/configure.ac new file mode 100644 index 0000000..a8c6de6 --- /dev/null +++ b/configure.ac @@ -0,0 +1,372 @@ +# Copyright 2005 Adam Jackson. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# on the rights to use, copy, modify, merge, publish, distribute, sub +# license, and/or sell copies of the Software, and to permit persons to whom +# the Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +AC_PREREQ([2.63]) +AC_INIT([libdrm], + [2.4.35], + [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], + [libdrm]) + +AC_CONFIG_HEADERS([config.h]) +AC_CONFIG_SRCDIR([Makefile.am]) +AC_CONFIG_MACRO_DIR([m4]) +AC_CONFIG_AUX_DIR([build-aux]) + +AM_INIT_AUTOMAKE([1.10 foreign dist-bzip2]) +AM_MAINTAINER_MODE([enable]) + +# Enable quiet compiles on automake 1.11. +m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])]) + +# Check for programs +AC_PROG_CC + +AC_USE_SYSTEM_EXTENSIONS +AC_SYS_LARGEFILE +AC_FUNC_ALLOCA + +# Initialize libtool +LT_PREREQ([2.2]) +LT_INIT([disable-static]) + + +PKG_CHECK_MODULES(PTHREADSTUBS, pthread-stubs) +AC_SUBST(PTHREADSTUBS_CFLAGS) +AC_SUBST(PTHREADSTUBS_LIBS) + +pkgconfigdir=${libdir}/pkgconfig +AC_SUBST(pkgconfigdir) +AC_ARG_ENABLE([udev], + [AS_HELP_STRING([--enable-udev], + [Enable support for using udev instead of mknod (default: disabled)])], + [UDEV=$enableval], [UDEV=no]) + +AC_ARG_ENABLE(libkms, + AS_HELP_STRING([--disable-libkms], + [Disable KMS mm abstraction library (default: auto)]), + [LIBKMS=$enableval], [LIBKMS=auto]) + +AC_ARG_ENABLE(intel, + AS_HELP_STRING([--disable-intel], + [Enable support for intel's KMS API (default: auto)]), + [INTEL=$enableval], [INTEL=auto]) + +AC_ARG_ENABLE(radeon, + AS_HELP_STRING([--disable-radeon], + [Enable support for radeon's KMS API (default: auto)]), + [RADEON=$enableval], [RADEON=auto]) + +AC_ARG_ENABLE(nouveau, + AS_HELP_STRING([--disable-nouveau], + [Enable support for nouveau's KMS API (default: auto)]), + [NOUVEAU=$enableval], [NOUVEAU=auto]) + +AC_ARG_ENABLE(vmwgfx-experimental-api, + AS_HELP_STRING([--enable-vmwgfx-experimental-api], + [Install vmwgfx's experimental kernel API header (default: disabled)]), + [VMWGFX=$enableval], [VMWGFX=no]) + +AC_ARG_ENABLE(omap-experimental-api, + AS_HELP_STRING([--enable-omap-experimental-api], + [Enable support for OMAP's experimental API (default: disabled)]), + [OMAP=$enableval], [OMAP=no]) + +AC_ARG_ENABLE(exynos-experimental-api, + AS_HELP_STRING([--enable-exynos-experimental-api], + [Enable support for EXYNOS's experimental API (default: disabled)]), + [EXYNOS=$enableval], [EXYNOS=no]) + +AC_ARG_ENABLE(slp, + AS_HELP_STRING([--disable-slp], + [Enable support for slp's API (default: auto)]), + [SLP=$enableval], [SLP=auto]) + +AC_ARG_VAR([bufmgr_dir], [Directory of slp-bufmgr]) + +if test "x$bufmgr_dir" = xyes; then + AC_DEFINE_UNQUOTED(BUFMGR_DIR, "$bufmgr_dir", [Directory for the modules of slp_bufmgr]) +else + AC_DEFINE(BUFMGR_DIR, "/usr/lib/bufmgr", [Directory for the modules of slp_bufmgr]) +fi + +dnl =========================================================================== +dnl check compiler flags +AC_DEFUN([LIBDRM_CC_TRY_FLAG], [ + AC_MSG_CHECKING([whether $CC supports $1]) + + libdrm_save_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS $1" + + AC_COMPILE_IFELSE([ ], [libdrm_cc_flag=yes], [libdrm_cc_flag=no]) + CFLAGS="$libdrm_save_CFLAGS" + + if test "x$libdrm_cc_flag" = "xyes"; then + ifelse([$2], , :, [$2]) + else + ifelse([$3], , :, [$3]) + fi + AC_MSG_RESULT([$libdrm_cc_flag]) +]) + +dnl We use clock_gettime to check for timeouts in drmWaitVBlank + +AC_CHECK_FUNCS([clock_gettime], [CLOCK_LIB=], + [AC_CHECK_LIB([rt], [clock_gettime], [CLOCK_LIB=-lrt], + [AC_MSG_ERROR([Couldn't find clock_gettime])])]) +AC_SUBST([CLOCK_LIB]) + +AC_CHECK_FUNCS([open_memstream], [HAVE_OPEN_MEMSTREAM=yes]) + +dnl Use lots of warning flags with with gcc and compatible compilers + +dnl Note: if you change the following variable, the cache is automatically +dnl skipped and all flags rechecked. So there's no need to do anything +dnl else. If for any reason you need to force a recheck, just change +dnl MAYBE_WARN in an ignorable way (like adding whitespace) + +MAYBE_WARN="-Wall -Wextra \ +-Wsign-compare -Werror-implicit-function-declaration \ +-Wpointer-arith -Wwrite-strings -Wstrict-prototypes \ +-Wmissing-prototypes -Wmissing-declarations -Wnested-externs \ +-Wpacked -Wswitch-enum -Wmissing-format-attribute \ +-Wstrict-aliasing=2 -Winit-self -Wunsafe-loop-optimizations \ +-Wdeclaration-after-statement -Wold-style-definition \ +-Wno-missing-field-initializers -Wno-unused-parameter \ +-Wno-attributes -Wno-long-long -Winline" + +# invalidate cached value if MAYBE_WARN has changed +if test "x$libdrm_cv_warn_maybe" != "x$MAYBE_WARN"; then + unset libdrm_cv_warn_cflags +fi +AC_CACHE_CHECK([for supported warning flags], libdrm_cv_warn_cflags, [ + echo + WARN_CFLAGS="" + + # Some warning options are not supported by all versions of + # gcc, so test all desired options against the current + # compiler. + # + # Note that there are some order dependencies + # here. Specifically, an option that disables a warning will + # have no net effect if a later option then enables that + # warnings, (perhaps implicitly). So we put some grouped + # options (-Wall and -Wextra) up front and the -Wno options + # last. + + for W in $MAYBE_WARN; do + LIBDRM_CC_TRY_FLAG([$W], [WARN_CFLAGS="$WARN_CFLAGS $W"]) + done + + libdrm_cv_warn_cflags=$WARN_CFLAGS + libdrm_cv_warn_maybe=$MAYBE_WARN + + AC_MSG_CHECKING([which warning flags were supported])]) +WARN_CFLAGS="$libdrm_cv_warn_cflags" + +if test "x$UDEV" = xyes; then + AC_DEFINE(UDEV, 1, [Have UDEV support]) +fi + +AC_CANONICAL_HOST +if test "x$LIBKMS" = xauto ; then + case $host_os in + linux*) LIBKMS="yes" ;; + *) LIBKMS="no" ;; + esac +fi + +AM_CONDITIONAL(HAVE_LIBKMS, [test "x$LIBKMS" = xyes]) + +AM_CONDITIONAL(HAVE_VMWGFX, [test "x$VMWGFX" = xyes]) +if test "x$VMWGFX" = xyes; then + AC_DEFINE(HAVE_VMWGFX, 1, [Have vmwgfx kernel headers]) +fi + +AM_CONDITIONAL(HAVE_NOUVEAU, [test "x$NOUVEAU" = xyes]) +if test "x$NOUVEAU" = xyes; then + AC_DEFINE(HAVE_NOUVEAU, 1, [Have nouveau (nvidia) support]) +fi + +AM_CONDITIONAL(HAVE_OMAP, [test "x$OMAP" = xyes]) +if test "x$OMAP" = xyes; then + AC_DEFINE(HAVE_OMAP, 1, [Have OMAP support]) +fi + +AM_CONDITIONAL(HAVE_EXYNOS, [test "x$EXYNOS" = xyes]) +if test "x$EXYNOS" = xyes; then + AC_DEFINE(HAVE_EXYNOS, 1, [Have EXYNOS support]) +fi + +PKG_CHECK_MODULES(CAIRO, cairo, [HAVE_CAIRO=yes], [HAVE_CAIRO=no]) +if test "x$HAVE_CAIRO" = xyes; then + AC_DEFINE(HAVE_CAIRO, 1, [Have cairo support]) +fi +AM_CONDITIONAL(HAVE_CAIRO, [test "x$HAVE_CAIRO" = xyes]) + +# For enumerating devices in test case +PKG_CHECK_MODULES(LIBUDEV, libudev, [HAVE_LIBUDEV=yes], [HAVE_LIBUDEV=no]) +if test "x$HAVE_LIBUDEV" = xyes; then + AC_DEFINE(HAVE_LIBUDEV, 1, [Have libudev support]) +fi +AM_CONDITIONAL(HAVE_LIBUDEV, [test "x$HAVE_LIBUDEV" = xyes]) + +if test "x$INTEL" != "xno" -o "x$RADEON" != "xno" -o "x$NOUVEAU" != "xno" -o "x$SLP" != "xno"; then + # Check for atomic intrinsics + AC_CACHE_CHECK([for native atomic primitives], drm_cv_atomic_primitives, + [ + drm_cv_atomic_primitives="none" + + AC_LINK_IFELSE([AC_LANG_PROGRAM([[ + int atomic_add(int i) { return __sync_fetch_and_add (&i, 1); } + int atomic_cmpxchg(int i, int j, int k) { return __sync_val_compare_and_swap (&i, j, k); } + ]],[[]])], + [drm_cv_atomic_primitives="Intel"],[]) + + if test "x$drm_cv_atomic_primitives" = "xnone"; then + AC_CHECK_HEADER([atomic_ops.h], drm_cv_atomic_primitives="libatomic-ops") + fi + + # atomic functions defined in & libc on Solaris + if test "x$drm_cv_atomic_primitives" = "xnone"; then + AC_CHECK_FUNC([atomic_cas_uint], + drm_cv_atomic_primitives="Solaris") + fi + + ]) + if test "x$drm_cv_atomic_primitives" = xIntel; then + AC_DEFINE(HAVE_LIBDRM_ATOMIC_PRIMITIVES, 1, + [Enable if your compiler supports the Intel __sync_* atomic primitives]) + fi + if test "x$drm_cv_atomic_primitives" = "xlibatomic-ops"; then + AC_DEFINE(HAVE_LIB_ATOMIC_OPS, 1, [Enable if you have libatomic-ops-dev installed]) + fi + + if test "x$drm_cv_atomic_primitives" = "xnone"; then + if test "x$INTEL" != "xauto"; then + if test "x$INTEL" != "xno"; then + AC_MSG_ERROR([libdrm_intel depends upon atomic operations, which were not found for your compiler/cpu. Try compiling with -march=native, or install the libatomics-op-dev package, or, failing both of those, disable support for Intel GPUs by passing --disable-intel to ./configure]) + fi + else + AC_MSG_WARN([Disabling libdrm_intel. It depends on atomic operations, which were not found for your compiler/cpu. Try compiling with -march=native, or install the libatomics-op-dev package.]) + INTEL=no + fi + if test "x$RADEON" != "xauto"; then + if test "x$RADEON" != "xno"; then + AC_MSG_ERROR([libdrm_radeon depends upon atomic operations, which were not found for your compiler/cpu. Try compiling with -march=native, or install the libatomics-op-dev package, or, failing both of those, disable support for Radeon support by passing --disable-radeon to ./configure]) + fi + else + AC_MSG_WARN([Disabling libdrm_radeon. It depends on atomic operations, which were not found for your compiler/cpu. Try compiling with -march=native, or install the libatomics-op-dev package.]) + RADEON=no + fi + if test "x$NOUVEAU" != "xauto"; then + if test "x$NOUVEAU" != "xno"; then + AC_MSG_ERROR([libdrm_nouveau depends upon atomic operations, which were not found for your compiler/cpu. Try compiling with -march=native, or install the libatomics-op-dev package, or, failing both of those, disable support for NVIDIA GPUs by passing --disable-nouveau to ./configure]) + fi + else + AC_MSG_WARN([Disabling libdrm_nouveau. It depends on atomic operations, which were not found for your compiler/cpu. Try compiling with -march=native, or install the libatomics-op-dev package.]) + NOUVEAU=no + fi + else + if test "x$INTEL" != "xno"; then + case $host_cpu in + i?86|x86_64) INTEL=yes ;; + *) INTEL=no ;; + esac + fi + if test "x$RADEON" != "xno"; then + RADEON=yes + fi + if test "x$NOUVEAU" != "xno"; then + NOUVEAU=yes + fi + fi +fi + +if test "x$SLP" != "xno"; then + AC_DEFINE(HAVE_SLP, 1, [Have slp]) +fi + +if test "x$INTEL" != "xno"; then + PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10]) +fi +AC_SUBST(PCIACCESS_CFLAGS) +AC_SUBST(PCIACCESS_LIBS) + +PKG_CHECK_MODULES(VALGRIND, [valgrind], [have_valgrind=yes], [have_valgrind=no]) +if test "x$have_valgrind" = "xyes"; then + AC_DEFINE([HAVE_VALGRIND], 1, [Use valgrind intrinsics to suppress false warnings]) +fi + +AM_CONDITIONAL(HAVE_SLP, [test "x$SLP" != "xno"]) +AM_CONDITIONAL(HAVE_INTEL, [test "x$INTEL" != "xno"]) +AM_CONDITIONAL(HAVE_RADEON, [test "x$RADEON" != "xno"]) +AM_CONDITIONAL(HAVE_NOUVEAU, [test "x$NOUVEAU" != "xno"]) +if test "x$RADEON" = xyes; then + AC_DEFINE(HAVE_RADEON, 1, [Have radeon support]) +fi + +AC_ARG_WITH([kernel-source], + [AS_HELP_STRING([--with-kernel-source], + [specify path to linux kernel source])], + [kernel_source="$with_kernel_source"]) +AC_SUBST(kernel_source) + +AC_SUBST(WARN_CFLAGS) +AC_CONFIG_FILES([ + Makefile + libkms/Makefile + libkms/libkms.pc + slp/Makefile + slp/libdrm_slp.pc + intel/Makefile + intel/libdrm_intel.pc + radeon/Makefile + radeon/libdrm_radeon.pc + nouveau/Makefile + nouveau/libdrm_nouveau.pc + omap/Makefile + omap/libdrm_omap.pc + exynos/Makefile + exynos/libdrm_exynos.pc + tests/Makefile + tests/modeprint/Makefile + tests/modetest/Makefile + tests/kmstest/Makefile + tests/proptest/Makefile + tests/radeon/Makefile + tests/vbltest/Makefile + include/Makefile + include/drm/Makefile + libdrm.pc]) +AC_OUTPUT + +echo "" +echo "$PACKAGE_STRING will be compiled with:" +echo "" +echo " libkms $LIBKMS" +echo " Intel API $INTEL" +echo " vmwgfx API $VMWGFX" +echo " Radeon API $RADEON" +echo " Nouveau API $NOUVEAU" +echo " OMAP API $OMAP" +echo " EXYNOS API $EXYNOS" +echo " SLP API $SLP" +echo " SLP bufmgr_dir $bufmgr_dir" +echo "" diff --git a/exynos/Makefile.am b/exynos/Makefile.am new file mode 100644 index 0000000..e782d34 --- /dev/null +++ b/exynos/Makefile.am @@ -0,0 +1,22 @@ +AM_CFLAGS = \ + $(WARN_CFLAGS) \ + -I$(top_srcdir) \ + -I$(top_srcdir)/exynos \ + $(PTHREADSTUBS_CFLAGS) \ + -I$(top_srcdir)/include/drm + +libdrm_exynos_la_LTLIBRARIES = libdrm_exynos.la +libdrm_exynos_ladir = $(libdir) +libdrm_exynos_la_LDFLAGS = -version-number 1:0:0 -no-undefined +libdrm_exynos_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@ + +libdrm_exynos_la_SOURCES = exynos_drm.c + +libdrm_exynoscommonincludedir = ${includedir}/exynos +libdrm_exynoscommoninclude_HEADERS = exynos_drm.h + +libdrm_exynosincludedir = ${includedir}/libdrm +libdrm_exynosinclude_HEADERS = exynos_drmif.h + +pkgconfigdir = @pkgconfigdir@ +pkgconfig_DATA = libdrm_exynos.pc diff --git a/exynos/exynos_drm.c b/exynos/exynos_drm.c new file mode 100644 index 0000000..dea4d4a --- /dev/null +++ b/exynos/exynos_drm.c @@ -0,0 +1,427 @@ +/* + * Copyright (C) 2012 Samsung Electronics Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Inki Dae + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include + +#include +#include + +#include + +#include "exynos_drm.h" +#include "exynos_drmif.h" + +/* + * Create exynos drm device object. + * + * @fd: file descriptor to exynos drm driver opened. + * + * if true, return the device object else NULL. + */ +struct exynos_device * exynos_device_create(int fd) +{ + struct exynos_device *dev; + + dev = calloc(sizeof(*dev), 1); + if (!dev) { + fprintf(stderr, "failed to create device[%s].\n", + strerror(errno)); + return NULL; + } + + dev->fd = fd; + + return dev; +} + +/* + * Destroy exynos drm device object + * + * @dev: exynos drm device object. + */ +void exynos_device_destroy(struct exynos_device *dev) +{ + free(dev); +} + +/* + * Create a exynos buffer object to exynos drm device. + * + * @dev: exynos drm device object. + * @size: user-desired size. + * flags: user-desired memory type. + * user can set one or more types among several types to memory + * allocation and cache attribute types. and as default, + * EXYNOS_BO_NONCONTIG and EXYNOS-BO_NONCACHABLE types would + * be used. + * + * if true, return a exynos buffer object else NULL. + */ +struct exynos_bo * exynos_bo_create(struct exynos_device *dev, + size_t size, uint32_t flags) +{ + struct exynos_bo *bo; + struct drm_exynos_gem_create req = { + .size = size, + .flags = flags, + }; + + if (size == 0) { + fprintf(stderr, "invalid size.\n"); + goto fail; + } + + bo = calloc(sizeof(*bo), 1); + if (!bo) { + fprintf(stderr, "failed to create bo[%s].\n", + strerror(errno)); + goto err_free_bo; + } + + bo->dev = dev; + + if (drmIoctl(dev->fd, DRM_IOCTL_EXYNOS_GEM_CREATE, &req)){ + fprintf(stderr, "failed to create gem object[%s].\n", + strerror(errno)); + goto err_free_bo; + } + + bo->handle = req.handle; + bo->size = size; + bo->flags = flags; + + return bo; + +err_free_bo: + free(bo); +fail: + return NULL; +} + +/* + * Get information to gem region allocated. + * + * @dev: exynos drm device object. + * @handle: gem handle to request gem info. + * @size: size to gem object and returned by kernel side. + * @flags: gem flags to gem object and returned by kernel side. + * + * with this function call, you can get flags and size to gem handle + * through bo object. + * + * if true, return 0 else negative. + */ +int exynos_bo_get_info(struct exynos_device *dev, uint32_t handle, + size_t *size, uint32_t *flags) +{ + int ret; + struct drm_exynos_gem_info req = { + .handle = handle, + }; + + ret = drmIoctl(dev->fd, DRM_IOCTL_EXYNOS_GEM_GET, &req); + if (ret < 0) { + fprintf(stderr, "failed to get gem object information[%s].\n", + strerror(errno)); + return ret; + } + + *size = req.size; + *flags = req.flags; + + return 0; +} + +/* + * Destroy a exynos buffer object. + * + * @bo: a exynos buffer object to be destroyed. + */ +void exynos_bo_destroy(struct exynos_bo *bo) +{ + if (!bo) + return; + + if (bo->vaddr) + munmap(bo->vaddr, bo->size); + + if (bo->handle) { + struct drm_gem_close req = { + .handle = bo->handle, + }; + + drmIoctl(bo->dev->fd, DRM_IOCTL_GEM_CLOSE, &req); + } + + free(bo); +} + + +/* + * Get a exynos buffer object from a gem global object name. + * + * @dev: a exynos device object. + * @name: a gem global object name exported by another process. + * + * this interface is used to get a exynos buffer object from a gem + * global object name sent by another process for buffer sharing. + * + * if true, return a exynos buffer object else NULL. + * + */ +struct exynos_bo * exynos_bo_from_name(struct exynos_device *dev, uint32_t name) +{ + struct exynos_bo *bo; + struct drm_gem_open req = { + .name = name, + }; + + bo = calloc(sizeof(*bo), 1); + if (!bo) { + fprintf(stderr, "failed to allocate bo[%s].\n", + strerror(errno)); + return NULL; + } + + if (drmIoctl(dev->fd, DRM_IOCTL_GEM_OPEN, &req)) { + fprintf(stderr, "failed to open gem object[%s].\n", + strerror(errno)); + goto err_free_bo; + } + + bo->dev = dev; + bo->name = name; + bo->handle = req.handle; + + return bo; + +err_free_bo: + free(bo); + return NULL; +} + +/* + * Get a gem global object name from a gem object handle. + * + * @bo: a exynos buffer object including gem handle. + * @name: a gem global object name to be got by kernel driver. + * + * this interface is used to get a gem global object name from a gem object + * handle to a buffer that wants to share it with another process. + * + * if true, return 0 else negative. + */ +int exynos_bo_get_name(struct exynos_bo *bo, uint32_t *name) +{ + if (!bo->name) { + struct drm_gem_flink req = { + .handle = bo->handle, + }; + int ret; + + ret = drmIoctl(bo->dev->fd, DRM_IOCTL_GEM_FLINK, &req); + if (ret) { + fprintf(stderr, "failed to get gem global name[%s].\n", + strerror(errno)); + return ret; + } + + bo->name = req.name; + } + + *name = bo->name; + + return 0; +} + +uint32_t exynos_bo_handle(struct exynos_bo *bo) +{ + return bo->handle; +} + +/* + * Mmap a buffer to user space. + * + * @bo: a exynos buffer object including a gem object handle to be mmapped + * to user space. + * + * if true, user pointer mmaped else NULL. + */ +void *exynos_bo_map(struct exynos_bo *bo) +{ + if (!bo->vaddr) { + struct exynos_device *dev = bo->dev; + struct drm_exynos_gem_mmap req = { + .handle = bo->handle, + .size = bo->size, + }; + int ret; + + ret = drmIoctl(dev->fd, DRM_IOCTL_EXYNOS_GEM_MMAP, &req); + if (ret) { + fprintf(stderr, "failed to mmap[%s].\n", + strerror(errno)); + return NULL; + } + + bo->vaddr = req.mapped; + } + + return bo->vaddr; +} + +/* + * Get a gem handle to user address space. + * + * @dev: a exynos device object. + * @vaddr: user space address to be imported into gem. + * @size: size to user space to be imported into gem. + * @handle: gem handle to gem object imported from user address and + * returned by kernel side. + * + * if true, return 0 else negative. + */ +int exynos_userptr(struct exynos_device *dev, uint64_t vaddr, + size_t size, uint32_t *handle) +{ + int ret; + struct drm_exynos_gem_userptr req = { + .userptr = vaddr, + .size = size, + }; + + ret = drmIoctl(dev->fd, DRM_IOCTL_EXYNOS_GEM_USERPTR, &req); + if (ret) { + fprintf(stderr, "failed to mmap[%s].\n", + strerror(errno)); + return ret; + } + + *handle = req.handle; + return 0; +} + +/* + * Export gem object to dmabuf as file descriptor. + * + * @dev: a exynos device object. + * @handle: gem handle to be exported into dmabuf as file descriptor. + * @fd: file descriptor to dmabuf exported from gem handle and + * returned by kernel side. + * + * if true, return 0 else negative. + */ +int exynos_prime_handle_to_fd(struct exynos_device *dev, uint32_t handle, + int *fd) +{ + int ret; + struct drm_prime_handle req = { + .handle = handle, + }; + + ret = drmIoctl(dev->fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &req); + if (ret) { + fprintf(stderr, "failed to mmap[%s].\n", + strerror(errno)); + return ret; + } + + *fd = req.fd; + return 0; +} + +/* + * Import file descriptor into gem handle. + * + * @dev: a exynos device object. + * @fd: file descriptor exported into dmabuf. + * @handle: gem handle to gem object imported from file descriptor + * and returned by kernel side. + * + * if true, return 0 else negative. + */ +int exynos_prime_fd_to_handle(struct exynos_device *dev, int fd, + uint32_t *handle) +{ + int ret; + struct drm_prime_handle req = { + .fd = fd, + }; + + ret = drmIoctl(dev->fd, DRM_IOCTL_PRIME_FD_TO_HANDLE, &req); + if (ret) { + fprintf(stderr, "failed to mmap[%s].\n", + strerror(errno)); + return ret; + } + + *handle = req.handle; + return 0; +} + + + +/* + * Request Wireless Display connection or disconnection. + * + * @dev: a exynos device object. + * @connect: indicate whether connectoin or disconnection request. + * @ext: indicate whether edid data includes extentions data or not. + * @edid: a pointer to edid data from Wireless Display device. + * + * this interface is used to request Virtual Display driver connection or + * disconnection. for this, user should get a edid data from the Wireless + * Display device and then send that data to kernel driver with connection + * request + * + * if true, return 0 else negative. + */ +int exynos_vidi_connection(struct exynos_device *dev, uint32_t connect, + uint32_t ext, void *edid) +{ + struct drm_exynos_vidi_connection req = { + .connection = connect, + .extensions = ext, + .edid = edid, + }; + int ret; + + ret = drmIoctl(dev->fd, DRM_IOCTL_EXYNOS_VIDI_CONNECTION, &req); + if (ret) { + fprintf(stderr, "failed to request vidi connection[%s].\n", + strerror(errno)); + return ret; + } + + return 0; +} diff --git a/exynos/exynos_drm.h b/exynos/exynos_drm.h new file mode 100644 index 0000000..447596b --- /dev/null +++ b/exynos/exynos_drm.h @@ -0,0 +1,566 @@ +/* exynos_drm.h + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * Authors: + * Inki Dae + * Joonyoung Shim + * Seung-Woo Kim + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _EXYNOS_DRM_H_ +#define _EXYNOS_DRM_H_ + +#include "drm.h" + +/** + * User-desired buffer creation information structure. + * + * @size: user-desired memory allocation size. + * - this size value would be page-aligned internally. + * @flags: user request for setting memory type or cache attributes. + * @handle: returned a handle to created gem object. + * - this handle will be set by gem module of kernel side. + */ +struct drm_exynos_gem_create { + uint64_t size; + unsigned int flags; + unsigned int handle; +}; + +/** + * A structure for getting buffer offset. + * + * @handle: a pointer to gem object created. + * @pad: just padding to be 64-bit aligned. + * @offset: relatived offset value of the memory region allocated. + * - this value should be set by user. + */ +struct drm_exynos_gem_map_off { + unsigned int handle; + unsigned int pad; + uint64_t offset; +}; + +/** + * A structure for mapping buffer. + * + * @handle: a handle to gem object created. + * @pad: just padding to be 64-bit aligned. + * @size: memory size to be mapped. + * @mapped: having user virtual address mmaped. + * - this variable would be filled by exynos gem module + * of kernel side with user virtual address which is allocated + * by do_mmap(). + */ +struct drm_exynos_gem_mmap { + unsigned int handle; + unsigned int pad; + uint64_t size; + uint64_t mapped; +}; + +/** + * User-requested user space importing structure + * + * @userptr: user space address allocated by malloc. + * @size: size to the buffer allocated by malloc. + * @flags: indicate user-desired cache attribute to map the allocated buffer + * to kernel space. + * @handle: a returned handle to created gem object. + * - this handle will be set by gem module of kernel side. + */ +struct drm_exynos_gem_userptr { + uint64_t userptr; + uint64_t size; + unsigned int flags; + unsigned int handle; +}; + +/** + * A structure to gem information. + * + * @handle: a handle to gem object created. + * @flags: flag value including memory type and cache attribute and + * this value would be set by driver. + * @size: size to memory region allocated by gem and this size would + * be set by driver. + */ +struct drm_exynos_gem_info { + unsigned int handle; + unsigned int flags; + uint64_t size; +}; + +/** + * A structure for user connection request of virtual display. + * + * @connection: indicate whether doing connetion or not by user. + * @extensions: if this value is 1 then the vidi driver would need additional + * 128bytes edid data. + * @edid: the edid data pointer from user side. + */ +struct drm_exynos_vidi_connection { + unsigned int connection; + unsigned int extensions; + uint64_t *edid; +}; + +/** + * A structure for ump. + * + * @gem_handle: a pointer to gem object created. + * @secure_id: ump secure id and this value would be filled + * by kernel side. + */ +struct drm_exynos_gem_ump { + unsigned int gem_handle; + unsigned int secure_id; +}; + + +/* temporary codes for legacy fimc and mfc drivers. */ + +/** + * A structure for getting physical address corresponding to a gem handle. + */ +struct drm_exynos_gem_get_phy { + unsigned int gem_handle; + unsigned int pad; + uint64_t size; + uint64_t phy_addr; +}; + +/** + * A structure for importing physical memory to a gem. + */ +struct drm_exynos_gem_phy_imp { + uint64_t phy_addr; + uint64_t size; + unsigned int gem_handle; + unsigned int pad; +}; + +/* Indicate exynos specific vblank flags */ +enum e_drm_exynos_vblank { + _DRM_VBLANK_EXYNOS_VIDI = 2, +}; + +/* indicate cache units. */ +enum e_drm_exynos_gem_cache_sel { + EXYNOS_DRM_L1_CACHE = 1 << 0, + EXYNOS_DRM_L2_CACHE = 1 << 1, + EXYNOS_DRM_ALL_CORES = 1 << 2, + EXYNOS_DRM_ALL_CACHES = EXYNOS_DRM_L1_CACHE | + EXYNOS_DRM_L2_CACHE, + EXYNOS_DRM_ALL_CACHES_CORES = EXYNOS_DRM_L1_CACHE | + EXYNOS_DRM_L2_CACHE | + EXYNOS_DRM_ALL_CORES, + EXYNOS_DRM_CACHE_SEL_MASK = EXYNOS_DRM_ALL_CACHES_CORES +}; + +/* indicate cache operation types. */ +enum e_drm_exynos_gem_cache_op { + EXYNOS_DRM_CACHE_INV_ALL = 1 << 3, + EXYNOS_DRM_CACHE_INV_RANGE = 1 << 4, + EXYNOS_DRM_CACHE_CLN_ALL = 1 << 5, + EXYNOS_DRM_CACHE_CLN_RANGE = 1 << 6, + EXYNOS_DRM_CACHE_FSH_ALL = EXYNOS_DRM_CACHE_INV_ALL | + EXYNOS_DRM_CACHE_CLN_ALL, + EXYNOS_DRM_CACHE_FSH_RANGE = EXYNOS_DRM_CACHE_INV_RANGE | + EXYNOS_DRM_CACHE_CLN_RANGE, + EXYNOS_DRM_CACHE_OP_MASK = EXYNOS_DRM_CACHE_FSH_ALL | + EXYNOS_DRM_CACHE_FSH_RANGE +}; + +/* memory type definitions. */ +enum e_drm_exynos_gem_mem_type { + /* Physically Continuous memory and used as default. */ + EXYNOS_BO_CONTIG = 0 << 0, + /* Physically Non-Continuous memory. */ + EXYNOS_BO_NONCONTIG = 1 << 0, + /* non-cachable mapping and used as default. */ + EXYNOS_BO_NONCACHABLE = 0 << 1, + /* cachable mapping. */ + EXYNOS_BO_CACHABLE = 1 << 1, + /* write-combine mapping. */ + EXYNOS_BO_WC = 1 << 2, + /* user space memory allocated by malloc. */ + EXYNOS_BO_USERPTR = 1 << 3, + EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | + EXYNOS_BO_WC | EXYNOS_BO_USERPTR +}; + +/** + * A structure for cache operation. + * + * @usr_addr: user space address. + * P.S. it SHOULD BE user space. + * @size: buffer size for cache operation. + * @flags: select cache unit and cache operation. + * @gem_handle: a handle to a gem object. + * this gem handle is needed for cache range operation to L2 cache. + */ +struct drm_exynos_gem_cache_op { + uint64_t usr_addr; + unsigned int size; + unsigned int flags; + unsigned int gem_handle; +}; + +struct drm_exynos_g2d_get_ver { + __u32 major; + __u32 minor; +}; + +struct drm_exynos_g2d_cmd { + __u32 offset; + __u32 data; +}; + +enum drm_exynos_g2d_event_type { + G2D_EVENT_NOT, + G2D_EVENT_NONSTOP, + G2D_EVENT_STOP, /* not yet */ +}; + +struct drm_exynos_g2d_set_cmdlist { + struct drm_exynos_g2d_cmd *cmd; + struct drm_exynos_g2d_cmd *cmd_gem; + __u32 cmd_nr; + __u32 cmd_gem_nr; + + /* for g2d event */ + __u64 user_data; + __u32 event_type; + __u32 reserved; +}; + +struct drm_exynos_g2d_exec { + __u32 async; + __u32 reserved; +}; + +/* definition of operations types */ +enum drm_exynos_ops_id { + EXYNOS_DRM_OPS_SRC, + EXYNOS_DRM_OPS_DST, + EXYNOS_DRM_OPS_MAX, +}; + +/* definition of size */ +struct drm_exynos_sz { + __u32 hsize; + __u32 vsize; +}; + +/* definition of position */ +struct drm_exynos_pos { + __u32 x; + __u32 y; + __u32 w; + __u32 h; +}; + +/* definition of flip */ +enum drm_exynos_flip { + EXYNOS_DRM_FLIP_NONE = (0 << 0), + EXYNOS_DRM_FLIP_VERTICAL = (1 << 0), + EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1), +}; + +/* definition of rotation degree */ +enum drm_exynos_degree { + EXYNOS_DRM_DEGREE_0, + EXYNOS_DRM_DEGREE_90, + EXYNOS_DRM_DEGREE_180, + EXYNOS_DRM_DEGREE_270, +}; + +/* definition of planar */ +enum drm_exynos_planer { + EXYNOS_DRM_PLANAR_Y, + EXYNOS_DRM_PLANAR_CB, + EXYNOS_DRM_PLANAR_CR, + EXYNOS_DRM_PLANAR_MAX, +}; + +/** + * A structure for ipp supported property list. + * + * @version: version of this structure. + * @ipp_id: id of ipp driver. + * @count: count of ipp driver. + * @writeback: flag of writeback supporting. + * @flip: flag of flip supporting. + * @degree: flag of degree information. + * @csc: flag of csc supporting. + * @crop: flag of crop supporting. + * @scale: flag of scale supporting. + * @refresh_min: min hz of refresh. + * @refresh_max: max hz of refresh. + * @crop_min: crop min resolution. + * @crop_max: crop max resolution. + * @scale_min: scale min resolution. + * @scale_max: scale max resolution. + */ +struct drm_exynos_ipp_prop_list { + __u32 version; + __u32 ipp_id; + __u32 count; + __u32 writeback; + __u32 flip; + __u32 degree; + __u32 csc; + __u32 crop; + __u32 scale; + __u32 refresh_min; + __u32 refresh_max; + __u32 reserved; + struct drm_exynos_sz crop_min; + struct drm_exynos_sz crop_max; + struct drm_exynos_sz scale_min; + struct drm_exynos_sz scale_max; +}; + +/** + * A structure for ipp config. + * + * @ops_id: property of operation directions. + * @flip: property of mirror, flip. + * @degree: property of rotation degree. + * @fmt: property of image format. + * @sz: property of image size. + * @pos: property of image position(src-cropped,dst-scaler). + */ +struct drm_exynos_ipp_config { + enum drm_exynos_ops_id ops_id; + enum drm_exynos_flip flip; + enum drm_exynos_degree degree; + __u32 fmt; + struct drm_exynos_sz sz; + struct drm_exynos_pos pos; +}; + +/* definition of command */ +enum drm_exynos_ipp_cmd { + IPP_CMD_NONE, + IPP_CMD_M2M, + IPP_CMD_WB, + IPP_CMD_OUTPUT, + IPP_CMD_MAX, +}; + +/** + * A structure for ipp property. + * + * @config: source, destination config. + * @cmd: definition of command. + * @ipp_id: id of ipp driver. + * @prop_id: id of property. + * @refresh_rate: refresh rate for writeback. + */ +struct drm_exynos_ipp_property { + struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; + enum drm_exynos_ipp_cmd cmd; + __u32 ipp_id; + __u32 prop_id; + __u32 refresh_rate; +}; + +/* definition of buffer */ +enum drm_exynos_ipp_buf_type { + IPP_BUF_ENQUEUE, + IPP_BUF_DEQUEUE, +}; + +/** + * A structure for ipp buffer operations. + * + * @ops_id: operation directions. + * @buf_type: definition of buffer. + * @prop_id: id of property. + * @buf_id: id of buffer. + * @handle: Y, Cb, Cr each planar handle. + * @user_data: user data. + */ +struct drm_exynos_ipp_queue_buf { + enum drm_exynos_ops_id ops_id; + enum drm_exynos_ipp_buf_type buf_type; + __u32 prop_id; + __u32 buf_id; + __u32 handle[EXYNOS_DRM_PLANAR_MAX]; + __u32 reserved; + __u64 user_data; +}; + +/* definition of control */ +enum drm_exynos_ipp_ctrl { + IPP_CTRL_PLAY, + IPP_CTRL_STOP, + IPP_CTRL_PAUSE, + IPP_CTRL_RESUME, + IPP_CTRL_MAX, +}; + +/** + * A structure for ipp start/stop operations. + * + * @prop_id: id of property. + * @ctrl: definition of control. + */ +struct drm_exynos_ipp_cmd_ctrl { + __u32 prop_id; + enum drm_exynos_ipp_ctrl ctrl; +}; + +/* type of hdmi audio */ +enum drm_exynos_hdmi_type { + HDMI_TYPE_I2S, + HDMI_TYPE_SPDIF, + HDMI_TYPE_MAX, +}; + +/* codec of hdmi audio */ +enum drm_exynos_hdmi_codec { + HDMI_CODEC_PCM, + HDMI_CODEC_AC3, + HDMI_CODEC_MP3, + HDMI_CODEC_WMA, + HDMI_CODEC_MAX, +}; + +/** + * A structure for hdmi audio enable. + * + * @type: audio type list. + * @codec: audio codec list. + * @enable: enable or disable audio. + */ +struct drm_exynos_hdmi_audio { + enum drm_exynos_hdmi_type type; + enum drm_exynos_hdmi_codec codec; + __u32 enable; + __u32 reserved; +}; + +#define DRM_EXYNOS_GEM_CREATE 0x00 +#define DRM_EXYNOS_GEM_MAP_OFFSET 0x01 +#define DRM_EXYNOS_GEM_MMAP 0x02 +#define DRM_EXYNOS_GEM_USERPTR 0x03 +#define DRM_EXYNOS_GEM_GET 0x04 +#define DRM_EXYNOS_VIDI_CONNECTION 0x07 + +/* temporary ioctl command. */ +#define DRM_EXYNOS_GEM_EXPORT_UMP 0x10 +#define DRM_EXYNOS_GEM_CACHE_OP 0x12 + +#define DRM_EXYNOS_GEM_GET_PHY 0x13 +#define DRM_EXYNOS_GEM_PHY_IMP 0x14 + +/* G2D */ +#define DRM_EXYNOS_G2D_GET_VER 0x20 +#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 +#define DRM_EXYNOS_G2D_EXEC 0x22 + +/* IPP - Image Post Processing */ +#define DRM_EXYNOS_IPP_GET_PROPERTY 0x30 +#define DRM_EXYNOS_IPP_SET_PROPERTY 0x31 +#define DRM_EXYNOS_IPP_QUEUE_BUF 0x32 +#define DRM_EXYNOS_IPP_CMD_CTRL 0x33 + +/* HDMI - Audio */ +#define DRM_EXYNOS_HDMI_AUDIO 0x40 + +#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) + +#define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off) + +#define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap) + +#define DRM_IOCTL_EXYNOS_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_GEM_USERPTR, struct drm_exynos_gem_userptr) + +#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) + +#define DRM_IOCTL_EXYNOS_GEM_EXPORT_UMP DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_GEM_EXPORT_UMP, struct drm_exynos_gem_ump) + +#define DRM_IOCTL_EXYNOS_GEM_CACHE_OP DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_GEM_CACHE_OP, struct drm_exynos_gem_cache_op) + +/* temporary ioctl command. */ +#define DRM_IOCTL_EXYNOS_GEM_GET_PHY DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_GEM_GET_PHY, struct drm_exynos_gem_get_phy) +#define DRM_IOCTL_EXYNOS_GEM_PHY_IMP DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_GEM_PHY_IMP, struct drm_exynos_gem_phy_imp) + +#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) + +#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) +#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) +#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) + +#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list) +#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property) +#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf) +#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl) + +#define DRM_IOCTL_EXYNOS_HDMI_AUDIO DRM_IOWR(DRM_COMMAND_BASE + \ + DRM_EXYNOS_HDMI_AUDIO, struct drm_exynos_hdmi_audio) + +/* EXYNOS specific events */ +#define DRM_EXYNOS_G2D_EVENT 0x80000000 +#define DRM_EXYNOS_IPP_EVENT 0x80000001 + +struct drm_exynos_g2d_event { + struct drm_event base; + __u64 user_data; + __u32 tv_sec; + __u32 tv_usec; + __u32 cmdlist_no; + __u32 reserved; +}; + +struct drm_exynos_ipp_event { + struct drm_event base; + __u64 user_data; + __u32 tv_sec; + __u32 tv_usec; + __u32 prop_id; + __u32 reserved; + __u32 buf_id[EXYNOS_DRM_OPS_MAX]; +}; + + +#endif diff --git a/exynos/exynos_drmif.h b/exynos/exynos_drmif.h new file mode 100644 index 0000000..24d2f64 --- /dev/null +++ b/exynos/exynos_drmif.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2012 Samsung Electronics Co., Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Inki Dae + */ + +#ifndef EXYNOS_DRMIF_H_ +#define EXYNOS_DRMIF_H_ + +#include +#include +#include "exynos_drm.h" + +struct exynos_device { + int fd; +}; + +/* + * Exynos Buffer Object structure. + * + * @dev: exynos device object allocated. + * @handle: a gem handle to gem object created. + * @flags: indicate memory allocation and cache attribute types. + * @fd: file descriptor exported into dmabuf. + * @size: size to the buffer created. + * @vaddr: user space address to a gem buffer mmaped. + * @name: a gem global handle from flink request. + */ +struct exynos_bo { + struct exynos_device *dev; + uint32_t handle; + uint32_t flags; + int fd; + size_t size; + void *vaddr; + uint32_t name; +}; + +/* + * device related functions: + */ +struct exynos_device * exynos_device_create(int fd); +void exynos_device_destroy(struct exynos_device *dev); + +/* + * buffer-object related functions: + */ +struct exynos_bo * exynos_bo_create(struct exynos_device *dev, + size_t size, uint32_t flags); +int exynos_bo_get_info(struct exynos_device *dev, uint32_t handle, + size_t *size, uint32_t *flags); +void exynos_bo_destroy(struct exynos_bo *bo); +struct exynos_bo * exynos_bo_from_name(struct exynos_device *dev, uint32_t name); +int exynos_bo_get_name(struct exynos_bo *bo, uint32_t *name); +uint32_t exynos_bo_handle(struct exynos_bo *bo); +void * exynos_bo_map(struct exynos_bo *bo); +int exynos_userptr(struct exynos_device *dev, uint64_t vaddr, + size_t size, uint32_t *handle); +int exynos_prime_handle_to_fd(struct exynos_device *dev, uint32_t handle, + int *fd); +int exynos_prime_fd_to_handle(struct exynos_device *dev, int fd, + uint32_t *handle); + +/* + * Virtual Display related functions: + */ +int exynos_vidi_connection(struct exynos_device *dev, uint32_t connect, + uint32_t ext, void *edid); + +#endif /* EXYNOS_DRMIF_H_ */ diff --git a/exynos/libdrm_exynos.pc.in b/exynos/libdrm_exynos.pc.in new file mode 100644 index 0000000..5ce9118 --- /dev/null +++ b/exynos/libdrm_exynos.pc.in @@ -0,0 +1,11 @@ +prefix=@prefix@ +exec_prefix=@exec_prefix@ +libdir=@libdir@ +includedir=@includedir@ + +Name: libdrm_exynos +Description: Userspace interface to exynos kernel DRM services +Version: 0.6 +Libs: -L${libdir} -ldrm_exynos +Cflags: -I${includedir} -I${includedir}/libdrm -I${includedir}/exynos +Requires.private: libdrm diff --git a/include/Makefile.am b/include/Makefile.am new file mode 100644 index 0000000..55ea506 --- /dev/null +++ b/include/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = drm diff --git a/include/drm/Makefile.am b/include/drm/Makefile.am new file mode 100644 index 0000000..2923ab4 --- /dev/null +++ b/include/drm/Makefile.am @@ -0,0 +1,44 @@ +# Copyright 2005 Adam Jackson. +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# on the rights to use, copy, modify, merge, publish, distribute, sub +# license, and/or sell copies of the Software, and to permit persons to whom +# the Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +# ADAM JACKSON BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +# XXX airlied says, nothing besides *_drm.h and drm*.h should be necessary. +# however, r300 and via need their reg headers installed in order to build. +# better solutions are welcome. + +klibdrmincludedir = ${includedir}/libdrm +klibdrminclude_HEADERS = \ + drm.h \ + drm_mode.h \ + drm_fourcc.h \ + drm_sarea.h \ + i915_drm.h \ + mga_drm.h \ + nouveau_drm.h \ + r128_drm.h \ + radeon_drm.h \ + savage_drm.h \ + sis_drm.h \ + via_drm.h \ + mach64_drm.h + + +if HAVE_VMWGFX +klibdrminclude_HEADERS += vmwgfx_drm.h +endif diff --git a/include/drm/drm.h b/include/drm/drm.h new file mode 100644 index 0000000..5e6cd29 --- /dev/null +++ b/include/drm/drm.h @@ -0,0 +1,823 @@ +/** + * \file drm.h + * Header for the Direct Rendering Manager + * + * \author Rickard E. (Rik) Faith + * + * \par Acknowledgments: + * Dec 1999, Richard Henderson , move to generic \c cmpxchg. + */ + +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DRM_H_ +#define _DRM_H_ + +#if defined(__linux__) + +#include +#include +typedef unsigned int drm_handle_t; + +#else /* One of the BSDs */ + +#include +#include +typedef int8_t __s8; +typedef uint8_t __u8; +typedef int16_t __s16; +typedef uint16_t __u16; +typedef int32_t __s32; +typedef uint32_t __u32; +typedef int64_t __s64; +typedef uint64_t __u64; +typedef unsigned long drm_handle_t; + +#endif + +#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ +#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ +#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ +#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ + +#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ +#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ +#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) +#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) +#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) + +typedef unsigned int drm_context_t; +typedef unsigned int drm_drawable_t; +typedef unsigned int drm_magic_t; + +/** + * Cliprect. + * + * \warning: If you change this structure, make sure you change + * XF86DRIClipRectRec in the server as well + * + * \note KW: Actually it's illegal to change either for + * backwards-compatibility reasons. + */ +struct drm_clip_rect { + unsigned short x1; + unsigned short y1; + unsigned short x2; + unsigned short y2; +}; + +/** + * Drawable information. + */ +struct drm_drawable_info { + unsigned int num_rects; + struct drm_clip_rect *rects; +}; + +/** + * Texture region, + */ +struct drm_tex_region { + unsigned char next; + unsigned char prev; + unsigned char in_use; + unsigned char padding; + unsigned int age; +}; + +/** + * Hardware lock. + * + * The lock structure is a simple cache-line aligned integer. To avoid + * processor bus contention on a multiprocessor system, there should not be any + * other data stored in the same cache line. + */ +struct drm_hw_lock { + __volatile__ unsigned int lock; /**< lock variable */ + char padding[60]; /**< Pad to cache line */ +}; + +/** + * DRM_IOCTL_VERSION ioctl argument type. + * + * \sa drmGetVersion(). + */ +struct drm_version { + int version_major; /**< Major version */ + int version_minor; /**< Minor version */ + int version_patchlevel; /**< Patch level */ + size_t name_len; /**< Length of name buffer */ + char *name; /**< Name of driver */ + size_t date_len; /**< Length of date buffer */ + char *date; /**< User-space buffer to hold date */ + size_t desc_len; /**< Length of desc buffer */ + char *desc; /**< User-space buffer to hold desc */ +}; + +/** + * DRM_IOCTL_GET_UNIQUE ioctl argument type. + * + * \sa drmGetBusid() and drmSetBusId(). + */ +struct drm_unique { + size_t unique_len; /**< Length of unique */ + char *unique; /**< Unique name for driver instantiation */ +}; + +struct drm_list { + int count; /**< Length of user-space structures */ + struct drm_version *version; +}; + +struct drm_block { + int unused; +}; + +/** + * DRM_IOCTL_CONTROL ioctl argument type. + * + * \sa drmCtlInstHandler() and drmCtlUninstHandler(). + */ +struct drm_control { + enum { + DRM_ADD_COMMAND, + DRM_RM_COMMAND, + DRM_INST_HANDLER, + DRM_UNINST_HANDLER + } func; + int irq; +}; + +/** + * Type of memory to map. + */ +enum drm_map_type { + _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ + _DRM_REGISTERS = 1, /**< no caching, no core dump */ + _DRM_SHM = 2, /**< shared, cached */ + _DRM_AGP = 3, /**< AGP/GART */ + _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ + _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ + _DRM_GEM = 6, /**< GEM object */ +}; + +/** + * Memory mapping flags. + */ +enum drm_map_flags { + _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ + _DRM_READ_ONLY = 0x02, + _DRM_LOCKED = 0x04, /**< shared, cached, locked */ + _DRM_KERNEL = 0x08, /**< kernel requires access */ + _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ + _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ + _DRM_REMOVABLE = 0x40, /**< Removable mapping */ + _DRM_DRIVER = 0x80 /**< Managed by driver */ +}; + +struct drm_ctx_priv_map { + unsigned int ctx_id; /**< Context requesting private mapping */ + void *handle; /**< Handle of map */ +}; + +/** + * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls + * argument type. + * + * \sa drmAddMap(). + */ +struct drm_map { + unsigned long offset; /**< Requested physical address (0 for SAREA)*/ + unsigned long size; /**< Requested physical size (bytes) */ + enum drm_map_type type; /**< Type of memory to map */ + enum drm_map_flags flags; /**< Flags */ + void *handle; /**< User-space: "Handle" to pass to mmap() */ + /**< Kernel-space: kernel-virtual address */ + int mtrr; /**< MTRR slot used */ + /* Private data */ +}; + +/** + * DRM_IOCTL_GET_CLIENT ioctl argument type. + */ +struct drm_client { + int idx; /**< Which client desired? */ + int auth; /**< Is client authenticated? */ + unsigned long pid; /**< Process ID */ + unsigned long uid; /**< User ID */ + unsigned long magic; /**< Magic */ + unsigned long iocs; /**< Ioctl count */ +}; + +enum drm_stat_type { + _DRM_STAT_LOCK, + _DRM_STAT_OPENS, + _DRM_STAT_CLOSES, + _DRM_STAT_IOCTLS, + _DRM_STAT_LOCKS, + _DRM_STAT_UNLOCKS, + _DRM_STAT_VALUE, /**< Generic value */ + _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ + _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ + + _DRM_STAT_IRQ, /**< IRQ */ + _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ + _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ + _DRM_STAT_DMA, /**< DMA */ + _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ + _DRM_STAT_MISSED /**< Missed DMA opportunity */ + /* Add to the *END* of the list */ +}; + +/** + * DRM_IOCTL_GET_STATS ioctl argument type. + */ +struct drm_stats { + unsigned long count; + struct { + unsigned long value; + enum drm_stat_type type; + } data[15]; +}; + +/** + * Hardware locking flags. + */ +enum drm_lock_flags { + _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ + _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ + _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ + _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ + /* These *HALT* flags aren't supported yet + -- they will be used to support the + full-screen DGA-like mode. */ + _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ + _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ +}; + +/** + * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. + * + * \sa drmGetLock() and drmUnlock(). + */ +struct drm_lock { + int context; + enum drm_lock_flags flags; +}; + +/** + * DMA flags + * + * \warning + * These values \e must match xf86drm.h. + * + * \sa drm_dma. + */ +enum drm_dma_flags { + /* Flags for DMA buffer dispatch */ + _DRM_DMA_BLOCK = 0x01, /**< + * Block until buffer dispatched. + * + * \note The buffer may not yet have + * been processed by the hardware -- + * getting a hardware lock with the + * hardware quiescent will ensure + * that the buffer has been + * processed. + */ + _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ + _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ + + /* Flags for DMA buffer request */ + _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ + _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ + _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ +}; + +/** + * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. + * + * \sa drmAddBufs(). + */ +struct drm_buf_desc { + int count; /**< Number of buffers of this size */ + int size; /**< Size in bytes */ + int low_mark; /**< Low water mark */ + int high_mark; /**< High water mark */ + enum { + _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ + _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ + _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ + _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ + _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ + } flags; + unsigned long agp_start; /**< + * Start address of where the AGP buffers are + * in the AGP aperture + */ +}; + +/** + * DRM_IOCTL_INFO_BUFS ioctl argument type. + */ +struct drm_buf_info { + int count; /**< Entries in list */ + struct drm_buf_desc *list; +}; + +/** + * DRM_IOCTL_FREE_BUFS ioctl argument type. + */ +struct drm_buf_free { + int count; + int *list; +}; + +/** + * Buffer information + * + * \sa drm_buf_map. + */ +struct drm_buf_pub { + int idx; /**< Index into the master buffer list */ + int total; /**< Buffer size */ + int used; /**< Amount of buffer in use (for DMA) */ + void *address; /**< Address of buffer */ +}; + +/** + * DRM_IOCTL_MAP_BUFS ioctl argument type. + */ +struct drm_buf_map { + int count; /**< Length of the buffer list */ +#ifdef __cplusplus + void *virt; +#else + void *virtual; /**< Mmap'd area in user-virtual */ +#endif + struct drm_buf_pub *list; /**< Buffer information */ +}; + +/** + * DRM_IOCTL_DMA ioctl argument type. + * + * Indices here refer to the offset into the buffer list in drm_buf_get. + * + * \sa drmDMA(). + */ +struct drm_dma { + int context; /**< Context handle */ + int send_count; /**< Number of buffers to send */ + int *send_indices; /**< List of handles to buffers */ + int *send_sizes; /**< Lengths of data to send */ + enum drm_dma_flags flags; /**< Flags */ + int request_count; /**< Number of buffers requested */ + int request_size; /**< Desired size for buffers */ + int *request_indices; /**< Buffer information */ + int *request_sizes; + int granted_count; /**< Number of buffers granted */ +}; + +enum drm_ctx_flags { + _DRM_CONTEXT_PRESERVED = 0x01, + _DRM_CONTEXT_2DONLY = 0x02 +}; + +/** + * DRM_IOCTL_ADD_CTX ioctl argument type. + * + * \sa drmCreateContext() and drmDestroyContext(). + */ +struct drm_ctx { + drm_context_t handle; + enum drm_ctx_flags flags; +}; + +/** + * DRM_IOCTL_RES_CTX ioctl argument type. + */ +struct drm_ctx_res { + int count; + struct drm_ctx *contexts; +}; + +/** + * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. + */ +struct drm_draw { + drm_drawable_t handle; +}; + +/** + * DRM_IOCTL_UPDATE_DRAW ioctl argument type. + */ +typedef enum { + DRM_DRAWABLE_CLIPRECTS, +} drm_drawable_info_type_t; + +struct drm_update_draw { + drm_drawable_t handle; + unsigned int type; + unsigned int num; + unsigned long long data; +}; + +/** + * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. + */ +struct drm_auth { + drm_magic_t magic; +}; + +/** + * DRM_IOCTL_IRQ_BUSID ioctl argument type. + * + * \sa drmGetInterruptFromBusID(). + */ +struct drm_irq_busid { + int irq; /**< IRQ number */ + int busnum; /**< bus number */ + int devnum; /**< device number */ + int funcnum; /**< function number */ +}; + +enum drm_vblank_seq_type { + _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ + _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ + _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ + _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ + _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ + _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ + _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ +}; + +#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) +#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ + _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) + +struct drm_wait_vblank_request { + enum drm_vblank_seq_type type; + unsigned int sequence; + unsigned long signal; +}; + +struct drm_wait_vblank_reply { + enum drm_vblank_seq_type type; + unsigned int sequence; + long tval_sec; + long tval_usec; +}; + +/** + * DRM_IOCTL_WAIT_VBLANK ioctl argument type. + * + * \sa drmWaitVBlank(). + */ +union drm_wait_vblank { + struct drm_wait_vblank_request request; + struct drm_wait_vblank_reply reply; +}; + +#define _DRM_PRE_MODESET 1 +#define _DRM_POST_MODESET 2 + +/** + * DRM_IOCTL_MODESET_CTL ioctl argument type + * + * \sa drmModesetCtl(). + */ +struct drm_modeset_ctl { + __u32 crtc; + __u32 cmd; +}; + +/** + * DRM_IOCTL_AGP_ENABLE ioctl argument type. + * + * \sa drmAgpEnable(). + */ +struct drm_agp_mode { + unsigned long mode; /**< AGP mode */ +}; + +/** + * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. + * + * \sa drmAgpAlloc() and drmAgpFree(). + */ +struct drm_agp_buffer { + unsigned long size; /**< In bytes -- will round to page boundary */ + unsigned long handle; /**< Used for binding / unbinding */ + unsigned long type; /**< Type of memory to allocate */ + unsigned long physical; /**< Physical used by i810 */ +}; + +/** + * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. + * + * \sa drmAgpBind() and drmAgpUnbind(). + */ +struct drm_agp_binding { + unsigned long handle; /**< From drm_agp_buffer */ + unsigned long offset; /**< In bytes -- will round to page boundary */ +}; + +/** + * DRM_IOCTL_AGP_INFO ioctl argument type. + * + * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), + * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), + * drmAgpVendorId() and drmAgpDeviceId(). + */ +struct drm_agp_info { + int agp_version_major; + int agp_version_minor; + unsigned long mode; + unsigned long aperture_base; /* physical address */ + unsigned long aperture_size; /* bytes */ + unsigned long memory_allowed; /* bytes */ + unsigned long memory_used; + + /* PCI information */ + unsigned short id_vendor; + unsigned short id_device; +}; + +/** + * DRM_IOCTL_SG_ALLOC ioctl argument type. + */ +struct drm_scatter_gather { + unsigned long size; /**< In bytes -- will round to page boundary */ + unsigned long handle; /**< Used for mapping / unmapping */ +}; + +/** + * DRM_IOCTL_SET_VERSION ioctl argument type. + */ +struct drm_set_version { + int drm_di_major; + int drm_di_minor; + int drm_dd_major; + int drm_dd_minor; +}; + +/** DRM_IOCTL_GEM_CLOSE ioctl argument type */ +struct drm_gem_close { + /** Handle of the object to be closed. */ + __u32 handle; + __u32 pad; +}; + +/** DRM_IOCTL_GEM_FLINK ioctl argument type */ +struct drm_gem_flink { + /** Handle for the object being named */ + __u32 handle; + + /** Returned global name */ + __u32 name; +}; + +/** DRM_IOCTL_GEM_OPEN ioctl argument type */ +struct drm_gem_open { + /** Name of object being opened */ + __u32 name; + + /** Returned handle for the object */ + __u32 handle; + + /** Returned size of the object */ + __u64 size; +}; + +/** DRM_IOCTL_GET_CAP ioctl argument type */ +struct drm_get_cap { + __u64 capability; + __u64 value; +}; + +#define DRM_CLOEXEC O_CLOEXEC +struct drm_prime_handle { + __u32 handle; + + /** Flags.. only applicable for handle->fd */ + __u32 flags; + + /** Returned dmabuf file descriptor */ + __s32 fd; +}; + +#include "drm_mode.h" + +#define DRM_IOCTL_BASE 'd' +#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) +#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) +#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) +#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) + +#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) +#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) +#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) +#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) +#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) +#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) +#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) +#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) +#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) +#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) +#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) +#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) +#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) + +#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) +#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) +#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) +#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) +#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) +#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) +#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) +#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) +#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) +#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) +#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) + +#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) + +#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) +#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) + +#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) +#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) + +#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) +#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) +#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) +#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) +#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) +#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) +#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) +#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) +#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) +#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) +#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) +#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) +#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) + +#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) +#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) +#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) +#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) +#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) +#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) +#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) +#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) + +#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) +#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) + +#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) +#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) + +#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) + +#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) + +#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) +#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) +#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) +#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) +#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) +#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) +#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) +#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) +#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) +#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) + +#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) +#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) +#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) +#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) +#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) +#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) +#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) +#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) + +#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) +#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) +#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) +#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) +#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) +#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) +#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) +#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) +#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) + +/** + * Device specific ioctls should only be in their respective headers + * The device specific ioctl range is from 0x40 to 0x99. + * Generic IOCTLS restart at 0xA0. + * + * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and + * drmCommandReadWrite(). + */ +#define DRM_COMMAND_BASE 0x40 +#define DRM_COMMAND_END 0xA0 + +/** + * Header for events written back to userspace on the drm fd. The + * type defines the type of event, the length specifies the total + * length of the event (including the header), and user_data is + * typically a 64 bit value passed with the ioctl that triggered the + * event. A read on the drm fd will always only return complete + * events, that is, if for example the read buffer is 100 bytes, and + * there are two 64 byte events pending, only one will be returned. + * + * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and + * up are chipset specific. + */ +struct drm_event { + __u32 type; + __u32 length; +}; + +#define DRM_EVENT_VBLANK 0x01 +#define DRM_EVENT_FLIP_COMPLETE 0x02 + +struct drm_event_vblank { + struct drm_event base; + __u64 user_data; + __u32 tv_sec; + __u32 tv_usec; + __u32 sequence; + __u32 reserved; +}; + +#define DRM_CAP_DUMB_BUFFER 0x1 +#define DRM_CAP_VBLANK_HIGH_CRTC 0x2 + +/* typedef area */ +typedef struct drm_clip_rect drm_clip_rect_t; +typedef struct drm_drawable_info drm_drawable_info_t; +typedef struct drm_tex_region drm_tex_region_t; +typedef struct drm_hw_lock drm_hw_lock_t; +typedef struct drm_version drm_version_t; +typedef struct drm_unique drm_unique_t; +typedef struct drm_list drm_list_t; +typedef struct drm_block drm_block_t; +typedef struct drm_control drm_control_t; +typedef enum drm_map_type drm_map_type_t; +typedef enum drm_map_flags drm_map_flags_t; +typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; +typedef struct drm_map drm_map_t; +typedef struct drm_client drm_client_t; +typedef enum drm_stat_type drm_stat_type_t; +typedef struct drm_stats drm_stats_t; +typedef enum drm_lock_flags drm_lock_flags_t; +typedef struct drm_lock drm_lock_t; +typedef enum drm_dma_flags drm_dma_flags_t; +typedef struct drm_buf_desc drm_buf_desc_t; +typedef struct drm_buf_info drm_buf_info_t; +typedef struct drm_buf_free drm_buf_free_t; +typedef struct drm_buf_pub drm_buf_pub_t; +typedef struct drm_buf_map drm_buf_map_t; +typedef struct drm_dma drm_dma_t; +typedef union drm_wait_vblank drm_wait_vblank_t; +typedef struct drm_agp_mode drm_agp_mode_t; +typedef enum drm_ctx_flags drm_ctx_flags_t; +typedef struct drm_ctx drm_ctx_t; +typedef struct drm_ctx_res drm_ctx_res_t; +typedef struct drm_draw drm_draw_t; +typedef struct drm_update_draw drm_update_draw_t; +typedef struct drm_auth drm_auth_t; +typedef struct drm_irq_busid drm_irq_busid_t; +typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; + +typedef struct drm_agp_buffer drm_agp_buffer_t; +typedef struct drm_agp_binding drm_agp_binding_t; +typedef struct drm_agp_info drm_agp_info_t; +typedef struct drm_scatter_gather drm_scatter_gather_t; +typedef struct drm_set_version drm_set_version_t; + +#endif diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h new file mode 100644 index 0000000..85facb0 --- /dev/null +++ b/include/drm/drm_fourcc.h @@ -0,0 +1,130 @@ +/* + * Copyright 2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DRM_FOURCC_H +#define DRM_FOURCC_H + +#include + +#define fourcc_code(a,b,c,d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ + ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) + +#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ + +/* color index */ +#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */ + +/* 8 bpp RGB */ +#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */ +#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */ + +/* 16 bpp RGB */ +#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */ +#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */ +#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */ +#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */ + +#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */ +#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */ +#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */ +#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */ + +#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */ +#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */ +#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */ +#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */ + +#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */ +#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */ +#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */ +#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */ + +#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */ +#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */ + +/* 24 bpp RGB */ +#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */ +#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */ + +/* 32 bpp RGB */ +#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */ +#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */ +#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */ +#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */ + +#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */ +#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */ +#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */ +#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */ + +#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */ +#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */ +#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */ +#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */ + +#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */ +#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */ +#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ +#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ + +/* packed YCbCr */ +#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ +#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ +#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */ +#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */ + +#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */ + +/* + * 2 plane YCbCr + * index 0 = Y plane, [7:0] Y + * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian + * or + * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian + */ +#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ + +/* + * 3 plane YCbCr + * index 0: Y plane, [7:0] Y + * index 1: Cb plane, [7:0] Cb + * index 2: Cr plane, [7:0] Cr + * or + * index 1: Cr plane, [7:0] Cr + * index 2: Cb plane, [7:0] Cb + */ +#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */ +#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */ +#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */ +#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */ +#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ +#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */ +#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */ +#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */ +#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ +#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ + +#endif /* DRM_FOURCC_H */ diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h new file mode 100644 index 0000000..c3f374d --- /dev/null +++ b/include/drm/drm_mode.h @@ -0,0 +1,467 @@ +/* + * Copyright (c) 2007 Dave Airlie + * Copyright (c) 2007 Jakob Bornecrantz + * Copyright (c) 2008 Red Hat Inc. + * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA + * Copyright (c) 2007-2008 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef _DRM_MODE_H +#define _DRM_MODE_H + +#define DRM_DISPLAY_INFO_LEN 32 +#define DRM_CONNECTOR_NAME_LEN 32 +#define DRM_DISPLAY_MODE_LEN 32 +#define DRM_PROP_NAME_LEN 32 + +#define DRM_MODE_TYPE_BUILTIN (1<<0) +#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) +#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) +#define DRM_MODE_TYPE_PREFERRED (1<<3) +#define DRM_MODE_TYPE_DEFAULT (1<<4) +#define DRM_MODE_TYPE_USERDEF (1<<5) +#define DRM_MODE_TYPE_DRIVER (1<<6) + +/* Video mode flags */ +/* bit compatible with the xorg definitions. */ +#define DRM_MODE_FLAG_PHSYNC (1<<0) +#define DRM_MODE_FLAG_NHSYNC (1<<1) +#define DRM_MODE_FLAG_PVSYNC (1<<2) +#define DRM_MODE_FLAG_NVSYNC (1<<3) +#define DRM_MODE_FLAG_INTERLACE (1<<4) +#define DRM_MODE_FLAG_DBLSCAN (1<<5) +#define DRM_MODE_FLAG_CSYNC (1<<6) +#define DRM_MODE_FLAG_PCSYNC (1<<7) +#define DRM_MODE_FLAG_NCSYNC (1<<8) +#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ +#define DRM_MODE_FLAG_BCAST (1<<10) +#define DRM_MODE_FLAG_PIXMUX (1<<11) +#define DRM_MODE_FLAG_DBLCLK (1<<12) +#define DRM_MODE_FLAG_CLKDIV2 (1<<13) + +/* DPMS flags */ +/* bit compatible with the xorg definitions. */ +#define DRM_MODE_DPMS_ON 0 +#define DRM_MODE_DPMS_STANDBY 1 +#define DRM_MODE_DPMS_SUSPEND 2 +#define DRM_MODE_DPMS_OFF 3 + +/* Scaling mode options */ +#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or + software can still scale) */ +#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */ +#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ +#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ + +/* Dithering mode options */ +#define DRM_MODE_DITHERING_OFF 0 +#define DRM_MODE_DITHERING_ON 1 +#define DRM_MODE_DITHERING_AUTO 2 + +/* Dirty info options */ +#define DRM_MODE_DIRTY_OFF 0 +#define DRM_MODE_DIRTY_ON 1 +#define DRM_MODE_DIRTY_ANNOTATE 2 + +struct drm_mode_modeinfo { + __u32 clock; + __u16 hdisplay, hsync_start, hsync_end, htotal, hskew; + __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan; + + __u32 vrefresh; + + __u32 flags; + __u32 type; + char name[DRM_DISPLAY_MODE_LEN]; +}; + +struct drm_mode_card_res { + __u64 fb_id_ptr; + __u64 crtc_id_ptr; + __u64 connector_id_ptr; + __u64 encoder_id_ptr; + __u32 count_fbs; + __u32 count_crtcs; + __u32 count_connectors; + __u32 count_encoders; + __u32 min_width, max_width; + __u32 min_height, max_height; +}; + +struct drm_mode_crtc { + __u64 set_connectors_ptr; + __u32 count_connectors; + + __u32 crtc_id; /**< Id */ + __u32 fb_id; /**< Id of framebuffer */ + + __u32 x, y; /**< Position on the frameuffer */ + + __u32 gamma_size; + __u32 mode_valid; + struct drm_mode_modeinfo mode; +}; + +#define DRM_MODE_PRESENT_TOP_FIELD (1<<0) +#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1) + +/* Planes blend with or override other bits on the CRTC */ +struct drm_mode_set_plane { + __u32 plane_id; + __u32 crtc_id; + __u32 fb_id; /* fb object contains surface format type */ + __u32 flags; + + /* Signed dest location allows it to be partially off screen */ + __s32 crtc_x, crtc_y; + __u32 crtc_w, crtc_h; + + /* Source values are 16.16 fixed point */ + __u32 src_x, src_y; + __u32 src_h, src_w; +}; + +struct drm_mode_get_plane { + __u32 plane_id; + + __u32 crtc_id; + __u32 fb_id; + + __u32 possible_crtcs; + __u32 gamma_size; + + __u32 count_format_types; + __u64 format_type_ptr; +}; + +struct drm_mode_get_plane_res { + __u64 plane_id_ptr; + __u32 count_planes; +}; + +#define DRM_MODE_ENCODER_NONE 0 +#define DRM_MODE_ENCODER_DAC 1 +#define DRM_MODE_ENCODER_TMDS 2 +#define DRM_MODE_ENCODER_LVDS 3 +#define DRM_MODE_ENCODER_TVDAC 4 +#define DRM_MODE_ENCODER_VIRTUAL 5 + +struct drm_mode_get_encoder { + __u32 encoder_id; + __u32 encoder_type; + + __u32 crtc_id; /**< Id of crtc */ + + __u32 possible_crtcs; + __u32 possible_clones; +}; + +/* This is for connectors with multiple signal types. */ +/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ +#define DRM_MODE_SUBCONNECTOR_Automatic 0 +#define DRM_MODE_SUBCONNECTOR_Unknown 0 +#define DRM_MODE_SUBCONNECTOR_DVID 3 +#define DRM_MODE_SUBCONNECTOR_DVIA 4 +#define DRM_MODE_SUBCONNECTOR_Composite 5 +#define DRM_MODE_SUBCONNECTOR_SVIDEO 6 +#define DRM_MODE_SUBCONNECTOR_Component 8 +#define DRM_MODE_SUBCONNECTOR_SCART 9 + +#define DRM_MODE_CONNECTOR_Unknown 0 +#define DRM_MODE_CONNECTOR_VGA 1 +#define DRM_MODE_CONNECTOR_DVII 2 +#define DRM_MODE_CONNECTOR_DVID 3 +#define DRM_MODE_CONNECTOR_DVIA 4 +#define DRM_MODE_CONNECTOR_Composite 5 +#define DRM_MODE_CONNECTOR_SVIDEO 6 +#define DRM_MODE_CONNECTOR_LVDS 7 +#define DRM_MODE_CONNECTOR_Component 8 +#define DRM_MODE_CONNECTOR_9PinDIN 9 +#define DRM_MODE_CONNECTOR_DisplayPort 10 +#define DRM_MODE_CONNECTOR_HDMIA 11 +#define DRM_MODE_CONNECTOR_HDMIB 12 +#define DRM_MODE_CONNECTOR_TV 13 +#define DRM_MODE_CONNECTOR_eDP 14 +#define DRM_MODE_CONNECTOR_VIRTUAL 15 + +struct drm_mode_get_connector { + + __u64 encoders_ptr; + __u64 modes_ptr; + __u64 props_ptr; + __u64 prop_values_ptr; + + __u32 count_modes; + __u32 count_props; + __u32 count_encoders; + + __u32 encoder_id; /**< Current Encoder */ + __u32 connector_id; /**< Id */ + __u32 connector_type; + __u32 connector_type_id; + + __u32 connection; + __u32 mm_width, mm_height; /**< HxW in millimeters */ + __u32 subpixel; +}; + +#define DRM_MODE_PROP_PENDING (1<<0) +#define DRM_MODE_PROP_RANGE (1<<1) +#define DRM_MODE_PROP_IMMUTABLE (1<<2) +#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ +#define DRM_MODE_PROP_BLOB (1<<4) +#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */ + +struct drm_mode_property_enum { + __u64 value; + char name[DRM_PROP_NAME_LEN]; +}; + +struct drm_mode_get_property { + __u64 values_ptr; /* values and blob lengths */ + __u64 enum_blob_ptr; /* enum and blob id ptrs */ + + __u32 prop_id; + __u32 flags; + char name[DRM_PROP_NAME_LEN]; + + __u32 count_values; + __u32 count_enum_blobs; +}; + +struct drm_mode_connector_set_property { + __u64 value; + __u32 prop_id; + __u32 connector_id; +}; + +#define DRM_MODE_OBJECT_CRTC 0xcccccccc +#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0 +#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0 +#define DRM_MODE_OBJECT_MODE 0xdededede +#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0 +#define DRM_MODE_OBJECT_FB 0xfbfbfbfb +#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb +#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee + +struct drm_mode_obj_get_properties { + __u64 props_ptr; + __u64 prop_values_ptr; + __u32 count_props; + __u32 obj_id; + __u32 obj_type; +}; + +struct drm_mode_obj_set_property { + __u64 value; + __u32 prop_id; + __u32 obj_id; + __u32 obj_type; +}; + +struct drm_mode_get_blob { + __u32 blob_id; + __u32 length; + __u64 data; +}; + +struct drm_mode_fb_cmd { + __u32 fb_id; + __u32 width, height; + __u32 pitch; + __u32 bpp; + __u32 depth; + /* driver specific handle */ + __u32 handle; +}; + +#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ + +struct drm_mode_fb_cmd2 { + __u32 fb_id; + __u32 width, height; + __u32 pixel_format; /* fourcc code from drm_fourcc.h */ + __u32 flags; + + /* + * In case of planar formats, this ioctl allows up to 4 + * buffer objects with offsets and pitches per plane. + * The pitch and offset order is dictated by the fourcc, + * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as: + * + * YUV 4:2:0 image with a plane of 8 bit Y samples + * followed by an interleaved U/V plane containing + * 8 bit 2x2 subsampled colour difference samples. + * + * So it would consist of Y as offset[0] and UV as + * offset[1]. Note that offset[0] will generally + * be 0. + */ + __u32 handles[4]; + __u32 pitches[4]; /* pitch for each plane */ + __u32 offsets[4]; /* offset of each plane */ +}; + +#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 +#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02 +#define DRM_MODE_FB_DIRTY_FLAGS 0x03 + +/* + * Mark a region of a framebuffer as dirty. + * + * Some hardware does not automatically update display contents + * as a hardware or software draw to a framebuffer. This ioctl + * allows userspace to tell the kernel and the hardware what + * regions of the framebuffer have changed. + * + * The kernel or hardware is free to update more then just the + * region specified by the clip rects. The kernel or hardware + * may also delay and/or coalesce several calls to dirty into a + * single update. + * + * Userspace may annotate the updates, the annotates are a + * promise made by the caller that the change is either a copy + * of pixels or a fill of a single color in the region specified. + * + * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then + * the number of updated regions are half of num_clips given, + * where the clip rects are paired in src and dst. The width and + * height of each one of the pairs must match. + * + * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller + * promises that the region specified of the clip rects is filled + * completely with a single color as given in the color argument. + */ + +struct drm_mode_fb_dirty_cmd { + __u32 fb_id; + __u32 flags; + __u32 color; + __u32 num_clips; + __u64 clips_ptr; +}; + +struct drm_mode_mode_cmd { + __u32 connector_id; + struct drm_mode_modeinfo mode; +}; + +#define DRM_MODE_CURSOR_BO (1<<0) +#define DRM_MODE_CURSOR_MOVE (1<<1) + +/* + * depending on the value in flags diffrent members are used. + * + * CURSOR_BO uses + * crtc + * width + * height + * handle - if 0 turns the cursor of + * + * CURSOR_MOVE uses + * crtc + * x + * y + */ +struct drm_mode_cursor { + __u32 flags; + __u32 crtc_id; + __s32 x; + __s32 y; + __u32 width; + __u32 height; + /* driver specific handle */ + __u32 handle; +}; + +struct drm_mode_crtc_lut { + __u32 crtc_id; + __u32 gamma_size; + + /* pointers to arrays */ + __u64 red; + __u64 green; + __u64 blue; +}; + +#define DRM_MODE_PAGE_FLIP_EVENT 0x01 +#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT + +/* + * Request a page flip on the specified crtc. + * + * This ioctl will ask KMS to schedule a page flip for the specified + * crtc. Once any pending rendering targeting the specified fb (as of + * ioctl time) has completed, the crtc will be reprogrammed to display + * that fb after the next vertical refresh. The ioctl returns + * immediately, but subsequent rendering to the current fb will block + * in the execbuffer ioctl until the page flip happens. If a page + * flip is already pending as the ioctl is called, EBUSY will be + * returned. + * + * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will + * request that drm sends back a vblank event (see drm.h: struct + * drm_event_vblank) when the page flip is done. The user_data field + * passed in with this ioctl will be returned as the user_data field + * in the vblank event struct. + * + * The reserved field must be zero until we figure out something + * clever to use it for. + */ + +struct drm_mode_crtc_page_flip { + __u32 crtc_id; + __u32 fb_id; + __u32 flags; + __u32 reserved; + __u64 user_data; +}; + +/* create a dumb scanout buffer */ +struct drm_mode_create_dumb { + __u32 height; + __u32 width; + __u32 bpp; + __u32 flags; + /* handle, pitch, size will be returned */ + __u32 handle; + __u32 pitch; + __u64 size; +}; + +/* set up for mmap of a dumb scanout buffer */ +struct drm_mode_map_dumb { + /** Handle for the object being mapped. */ + __u32 handle; + __u32 pad; + /** + * Fake offset to use for subsequent mmap call + * + * This is a fixed-size type for 32/64 compatibility. + */ + __u64 offset; +}; + +struct drm_mode_destroy_dumb { + __u32 handle; +}; + +#endif diff --git a/include/drm/drm_sarea.h b/include/drm/drm_sarea.h new file mode 100644 index 0000000..7325558 --- /dev/null +++ b/include/drm/drm_sarea.h @@ -0,0 +1,82 @@ +/** + * \file drm_sarea.h + * \brief SAREA definitions + * + * \author Michel Dänzer + */ + +/* + * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _DRM_SAREA_H_ +#define _DRM_SAREA_H_ + +#include "drm.h" + +/* SAREA area needs to be at least a page */ +#if defined(__alpha__) +#define SAREA_MAX 0x2000U +#elif defined(__ia64__) +#define SAREA_MAX 0x10000U /* 64kB */ +#else +/* Intel 830M driver needs at least 8k SAREA */ +#define SAREA_MAX 0x2000U +#endif + +/** Maximum number of drawables in the SAREA */ +#define SAREA_MAX_DRAWABLES 256 + +#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000 + +/** SAREA drawable */ +struct drm_sarea_drawable { + unsigned int stamp; + unsigned int flags; +}; + +/** SAREA frame */ +struct drm_sarea_frame { + unsigned int x; + unsigned int y; + unsigned int width; + unsigned int height; + unsigned int fullscreen; +}; + +/** SAREA */ +struct drm_sarea { + /** first thing is always the DRM locking structure */ + struct drm_hw_lock lock; + /** \todo Use readers/writer lock for drm_sarea::drawable_lock */ + struct drm_hw_lock drawable_lock; + struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ + struct drm_sarea_frame frame; /**< frame */ + drm_context_t dummy_context; +}; + +typedef struct drm_sarea_drawable drm_sarea_drawable_t; +typedef struct drm_sarea_frame drm_sarea_frame_t; +typedef struct drm_sarea drm_sarea_t; + +#endif /* _DRM_SAREA_H_ */ diff --git a/include/drm/i810_drm.h b/include/drm/i810_drm.h new file mode 100644 index 0000000..7a10bb6 --- /dev/null +++ b/include/drm/i810_drm.h @@ -0,0 +1,281 @@ +#ifndef _I810_DRM_H_ +#define _I810_DRM_H_ + +/* WARNING: These defines must be the same as what the Xserver uses. + * if you change them, you must change the defines in the Xserver. + */ + +#ifndef _I810_DEFINES_ +#define _I810_DEFINES_ + +#define I810_DMA_BUF_ORDER 12 +#define I810_DMA_BUF_SZ (1< + * Frank C. Earl + * Leif Delgass + */ + +#ifndef __MACH64_DRM_H__ +#define __MACH64_DRM_H__ + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (mach64_sarea.h) + */ +#ifndef __MACH64_SAREA_DEFINES__ +#define __MACH64_SAREA_DEFINES__ + +/* What needs to be changed for the current vertex buffer? + * GH: We're going to be pedantic about this. We want the card to do as + * little as possible, so let's avoid having it fetch a whole bunch of + * register values that don't change all that often, if at all. + */ +#define MACH64_UPLOAD_DST_OFF_PITCH 0x0001 +#define MACH64_UPLOAD_Z_OFF_PITCH 0x0002 +#define MACH64_UPLOAD_Z_ALPHA_CNTL 0x0004 +#define MACH64_UPLOAD_SCALE_3D_CNTL 0x0008 +#define MACH64_UPLOAD_DP_FOG_CLR 0x0010 +#define MACH64_UPLOAD_DP_WRITE_MASK 0x0020 +#define MACH64_UPLOAD_DP_PIX_WIDTH 0x0040 +#define MACH64_UPLOAD_SETUP_CNTL 0x0080 +#define MACH64_UPLOAD_MISC 0x0100 +#define MACH64_UPLOAD_TEXTURE 0x0200 +#define MACH64_UPLOAD_TEX0IMAGE 0x0400 +#define MACH64_UPLOAD_TEX1IMAGE 0x0800 +#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */ +#define MACH64_UPLOAD_CONTEXT 0x00ff +#define MACH64_UPLOAD_ALL 0x1fff + +/* DMA buffer size + */ +#define MACH64_BUFFER_SIZE 16384 + +/* Max number of swaps allowed on the ring + * before the client must wait + */ +#define MACH64_MAX_QUEUED_FRAMES 3U + +/* Byte offsets for host blit buffer data + */ +#define MACH64_HOSTDATA_BLIT_OFFSET 104 + +/* Keep these small for testing. + */ +#define MACH64_NR_SAREA_CLIPRECTS 8 + +#define MACH64_CARD_HEAP 0 +#define MACH64_AGP_HEAP 1 +#define MACH64_NR_TEX_HEAPS 2 +#define MACH64_NR_TEX_REGIONS 64 +#define MACH64_LOG_TEX_GRANULARITY 16 + +#define MACH64_TEX_MAXLEVELS 1 + +#define MACH64_NR_CONTEXT_REGS 15 +#define MACH64_NR_TEXTURE_REGS 4 + +#endif /* __MACH64_SAREA_DEFINES__ */ + +typedef struct { + unsigned int dst_off_pitch; + + unsigned int z_off_pitch; + unsigned int z_cntl; + unsigned int alpha_tst_cntl; + + unsigned int scale_3d_cntl; + + unsigned int sc_left_right; + unsigned int sc_top_bottom; + + unsigned int dp_fog_clr; + unsigned int dp_write_mask; + unsigned int dp_pix_width; + unsigned int dp_mix; + unsigned int dp_src; + + unsigned int clr_cmp_cntl; + unsigned int gui_traj_cntl; + + unsigned int setup_cntl; + + unsigned int tex_size_pitch; + unsigned int tex_cntl; + unsigned int secondary_tex_off; + unsigned int tex_offset; +} drm_mach64_context_regs_t; + +typedef struct drm_mach64_sarea { + /* The channel for communication of state information to the kernel + * on firing a vertex dma buffer. + */ + drm_mach64_context_regs_t context_state; + unsigned int dirty; + unsigned int vertsize; + + /* The current cliprects, or a subset thereof. + */ + struct drm_clip_rect boxes[MACH64_NR_SAREA_CLIPRECTS]; + unsigned int nbox; + + /* Counters for client-side throttling of rendering clients. + */ + unsigned int frames_queued; + + /* Texture memory LRU. + */ + struct drm_tex_region tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS + + 1]; + unsigned int tex_age[MACH64_NR_TEX_HEAPS]; + int ctx_owner; +} drm_mach64_sarea_t; + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (mach64_common.h) + */ + +/* Mach64 specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ + +#define DRM_MACH64_INIT 0x00 +#define DRM_MACH64_IDLE 0x01 +#define DRM_MACH64_RESET 0x02 +#define DRM_MACH64_SWAP 0x03 +#define DRM_MACH64_CLEAR 0x04 +#define DRM_MACH64_VERTEX 0x05 +#define DRM_MACH64_BLIT 0x06 +#define DRM_MACH64_FLUSH 0x07 +#define DRM_MACH64_GETPARAM 0x08 + +#define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t) +#define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE ) +#define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET ) +#define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP ) +#define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t) +#define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t) +#define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t) +#define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH ) +#define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t) + +/* Buffer flags for clears + */ +#define MACH64_FRONT 0x1 +#define MACH64_BACK 0x2 +#define MACH64_DEPTH 0x4 + +/* Primitive types for vertex buffers + */ +#define MACH64_PRIM_POINTS 0x00000000 +#define MACH64_PRIM_LINES 0x00000001 +#define MACH64_PRIM_LINE_LOOP 0x00000002 +#define MACH64_PRIM_LINE_STRIP 0x00000003 +#define MACH64_PRIM_TRIANGLES 0x00000004 +#define MACH64_PRIM_TRIANGLE_STRIP 0x00000005 +#define MACH64_PRIM_TRIANGLE_FAN 0x00000006 +#define MACH64_PRIM_QUADS 0x00000007 +#define MACH64_PRIM_QUAD_STRIP 0x00000008 +#define MACH64_PRIM_POLYGON 0x00000009 + +typedef enum _drm_mach64_dma_mode_t { + MACH64_MODE_DMA_ASYNC, + MACH64_MODE_DMA_SYNC, + MACH64_MODE_MMIO +} drm_mach64_dma_mode_t; + +typedef struct drm_mach64_init { + enum { + DRM_MACH64_INIT_DMA = 0x01, + DRM_MACH64_CLEANUP_DMA = 0x02 + } func; + + unsigned long sarea_priv_offset; + int is_pci; + drm_mach64_dma_mode_t dma_mode; + + unsigned int fb_bpp; + unsigned int front_offset, front_pitch; + unsigned int back_offset, back_pitch; + + unsigned int depth_bpp; + unsigned int depth_offset, depth_pitch; + + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long ring_offset; + unsigned long buffers_offset; + unsigned long agp_textures_offset; +} drm_mach64_init_t; + +typedef struct drm_mach64_clear { + unsigned int flags; + int x, y, w, h; + unsigned int clear_color; + unsigned int clear_depth; +} drm_mach64_clear_t; + +typedef struct drm_mach64_vertex { + int prim; + void *buf; /* Address of vertex buffer */ + unsigned long used; /* Number of bytes in buffer */ + int discard; /* Client finished with buffer? */ +} drm_mach64_vertex_t; + +typedef struct drm_mach64_blit { + void *buf; + int pitch; + int offset; + int format; + unsigned short x, y; + unsigned short width, height; +} drm_mach64_blit_t; + +typedef struct drm_mach64_getparam { + enum { + MACH64_PARAM_FRAMES_QUEUED = 0x01, + MACH64_PARAM_IRQ_NR = 0x02 + } param; + void *value; +} drm_mach64_getparam_t; + +#endif diff --git a/include/drm/mga_drm.h b/include/drm/mga_drm.h new file mode 100644 index 0000000..b630e8f --- /dev/null +++ b/include/drm/mga_drm.h @@ -0,0 +1,419 @@ +/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*- + * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jeff Hartmann + * Keith Whitwell + * + * Rewritten by: + * Gareth Hughes + */ + +#ifndef __MGA_DRM_H__ +#define __MGA_DRM_H__ + +#include "drm.h" + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (mga_sarea.h) + */ + +#ifndef __MGA_SAREA_DEFINES__ +#define __MGA_SAREA_DEFINES__ + +/* WARP pipe flags + */ +#define MGA_F 0x1 /* fog */ +#define MGA_A 0x2 /* alpha */ +#define MGA_S 0x4 /* specular */ +#define MGA_T2 0x8 /* multitexture */ + +#define MGA_WARP_TGZ 0 +#define MGA_WARP_TGZF (MGA_F) +#define MGA_WARP_TGZA (MGA_A) +#define MGA_WARP_TGZAF (MGA_F|MGA_A) +#define MGA_WARP_TGZS (MGA_S) +#define MGA_WARP_TGZSF (MGA_S|MGA_F) +#define MGA_WARP_TGZSA (MGA_S|MGA_A) +#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A) +#define MGA_WARP_T2GZ (MGA_T2) +#define MGA_WARP_T2GZF (MGA_T2|MGA_F) +#define MGA_WARP_T2GZA (MGA_T2|MGA_A) +#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F) +#define MGA_WARP_T2GZS (MGA_T2|MGA_S) +#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F) +#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A) +#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A) + +#define MGA_MAX_G200_PIPES 8 /* no multitex */ +#define MGA_MAX_G400_PIPES 16 +#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES +#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */ + +#define MGA_CARD_TYPE_G200 1 +#define MGA_CARD_TYPE_G400 2 +#define MGA_CARD_TYPE_G450 3 /* not currently used */ +#define MGA_CARD_TYPE_G550 4 + +#define MGA_FRONT 0x1 +#define MGA_BACK 0x2 +#define MGA_DEPTH 0x4 + +/* What needs to be changed for the current vertex dma buffer? + */ +#define MGA_UPLOAD_CONTEXT 0x1 +#define MGA_UPLOAD_TEX0 0x2 +#define MGA_UPLOAD_TEX1 0x4 +#define MGA_UPLOAD_PIPE 0x8 +#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */ +#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */ +#define MGA_UPLOAD_2D 0x40 +#define MGA_WAIT_AGE 0x80 /* handled client-side */ +#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */ +#if 0 +#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock + quiescent */ +#endif + +/* 32 buffers of 64k each, total 2 meg. + */ +#define MGA_BUFFER_SIZE (1 << 16) +#define MGA_NUM_BUFFERS 128 + +/* Keep these small for testing. + */ +#define MGA_NR_SAREA_CLIPRECTS 8 + +/* 2 heaps (1 for card, 1 for agp), each divided into upto 128 + * regions, subject to a minimum region size of (1<<16) == 64k. + * + * Clients may subdivide regions internally, but when sharing between + * clients, the region size is the minimum granularity. + */ + +#define MGA_CARD_HEAP 0 +#define MGA_AGP_HEAP 1 +#define MGA_NR_TEX_HEAPS 2 +#define MGA_NR_TEX_REGIONS 16 +#define MGA_LOG_MIN_TEX_REGION_SIZE 16 + +#define DRM_MGA_IDLE_RETRY 2048 + +#endif /* __MGA_SAREA_DEFINES__ */ + +/* Setup registers for 3D context + */ +typedef struct { + unsigned int dstorg; + unsigned int maccess; + unsigned int plnwt; + unsigned int dwgctl; + unsigned int alphactrl; + unsigned int fogcolor; + unsigned int wflag; + unsigned int tdualstage0; + unsigned int tdualstage1; + unsigned int fcol; + unsigned int stencil; + unsigned int stencilctl; +} drm_mga_context_regs_t; + +/* Setup registers for 2D, X server + */ +typedef struct { + unsigned int pitch; +} drm_mga_server_regs_t; + +/* Setup registers for each texture unit + */ +typedef struct { + unsigned int texctl; + unsigned int texctl2; + unsigned int texfilter; + unsigned int texbordercol; + unsigned int texorg; + unsigned int texwidth; + unsigned int texheight; + unsigned int texorg1; + unsigned int texorg2; + unsigned int texorg3; + unsigned int texorg4; +} drm_mga_texture_regs_t; + +/* General aging mechanism + */ +typedef struct { + unsigned int head; /* Position of head pointer */ + unsigned int wrap; /* Primary DMA wrap count */ +} drm_mga_age_t; + +typedef struct _drm_mga_sarea { + /* The channel for communication of state information to the kernel + * on firing a vertex dma buffer. + */ + drm_mga_context_regs_t context_state; + drm_mga_server_regs_t server_state; + drm_mga_texture_regs_t tex_state[2]; + unsigned int warp_pipe; + unsigned int dirty; + unsigned int vertsize; + + /* The current cliprects, or a subset thereof. + */ + struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS]; + unsigned int nbox; + + /* Information about the most recently used 3d drawable. The + * client fills in the req_* fields, the server fills in the + * exported_ fields and puts the cliprects into boxes, above. + * + * The client clears the exported_drawable field before + * clobbering the boxes data. + */ + unsigned int req_drawable; /* the X drawable id */ + unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */ + + unsigned int exported_drawable; + unsigned int exported_index; + unsigned int exported_stamp; + unsigned int exported_buffers; + unsigned int exported_nfront; + unsigned int exported_nback; + int exported_back_x, exported_front_x, exported_w; + int exported_back_y, exported_front_y, exported_h; + struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS]; + + /* Counters for aging textures and for client-side throttling. + */ + unsigned int status[4]; + unsigned int last_wrap; + + drm_mga_age_t last_frame; + unsigned int last_enqueue; /* last time a buffer was enqueued */ + unsigned int last_dispatch; /* age of the most recently dispatched buffer */ + unsigned int last_quiescent; /* */ + + /* LRU lists for texture memory in agp space and on the card. + */ + struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1]; + unsigned int texAge[MGA_NR_TEX_HEAPS]; + + /* Mechanism to validate card state. + */ + int ctxOwner; +} drm_mga_sarea_t; + +/* MGA specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_MGA_INIT 0x00 +#define DRM_MGA_FLUSH 0x01 +#define DRM_MGA_RESET 0x02 +#define DRM_MGA_SWAP 0x03 +#define DRM_MGA_CLEAR 0x04 +#define DRM_MGA_VERTEX 0x05 +#define DRM_MGA_INDICES 0x06 +#define DRM_MGA_ILOAD 0x07 +#define DRM_MGA_BLIT 0x08 +#define DRM_MGA_GETPARAM 0x09 + +/* 3.2: + * ioctls for operating on fences. + */ +#define DRM_MGA_SET_FENCE 0x0a +#define DRM_MGA_WAIT_FENCE 0x0b +#define DRM_MGA_DMA_BOOTSTRAP 0x0c + +#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t) +#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t) +#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET) +#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP) +#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t) +#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t) +#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t) +#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t) +#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t) +#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t) +#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, __u32) +#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, __u32) +#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t) + +typedef struct _drm_mga_warp_index { + int installed; + unsigned long phys_addr; + int size; +} drm_mga_warp_index_t; + +typedef struct drm_mga_init { + enum { + MGA_INIT_DMA = 0x01, + MGA_CLEANUP_DMA = 0x02 + } func; + + unsigned long sarea_priv_offset; + + int chipset; + int sgram; + + unsigned int maccess; + + unsigned int fb_cpp; + unsigned int front_offset, front_pitch; + unsigned int back_offset, back_pitch; + + unsigned int depth_cpp; + unsigned int depth_offset, depth_pitch; + + unsigned int texture_offset[MGA_NR_TEX_HEAPS]; + unsigned int texture_size[MGA_NR_TEX_HEAPS]; + + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long status_offset; + unsigned long warp_offset; + unsigned long primary_offset; + unsigned long buffers_offset; +} drm_mga_init_t; + +typedef struct drm_mga_dma_bootstrap { + /** + * \name AGP texture region + * + * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will + * be filled in with the actual AGP texture settings. + * + * \warning + * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode + * is zero, it means that PCI memory (most likely through the use of + * an IOMMU) is being used for "AGP" textures. + */ + /*@{ */ + unsigned long texture_handle; /**< Handle used to map AGP textures. */ + __u32 texture_size; /**< Size of the AGP texture region. */ + /*@} */ + + /** + * Requested size of the primary DMA region. + * + * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be + * filled in with the actual AGP mode. If AGP was not available + */ + __u32 primary_size; + + /** + * Requested number of secondary DMA buffers. + * + * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be + * filled in with the actual number of secondary DMA buffers + * allocated. Particularly when PCI DMA is used, this may be + * (subtantially) less than the number requested. + */ + __u32 secondary_bin_count; + + /** + * Requested size of each secondary DMA buffer. + * + * While the kernel \b is free to reduce + * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed + * to reduce dma_mga_dma_bootstrap::secondary_bin_size. + */ + __u32 secondary_bin_size; + + /** + * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X, + * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is + * zero, it means that PCI DMA should be used, even if AGP is + * possible. + * + * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be + * filled in with the actual AGP mode. If AGP was not available + * (i.e., PCI DMA was used), this value will be zero. + */ + __u32 agp_mode; + + /** + * Desired AGP GART size, measured in megabytes. + */ + __u8 agp_size; +} drm_mga_dma_bootstrap_t; + +typedef struct drm_mga_clear { + unsigned int flags; + unsigned int clear_color; + unsigned int clear_depth; + unsigned int color_mask; + unsigned int depth_mask; +} drm_mga_clear_t; + +typedef struct drm_mga_vertex { + int idx; /* buffer to queue */ + int used; /* bytes in use */ + int discard; /* client finished with buffer? */ +} drm_mga_vertex_t; + +typedef struct drm_mga_indices { + int idx; /* buffer to queue */ + unsigned int start; + unsigned int end; + int discard; /* client finished with buffer? */ +} drm_mga_indices_t; + +typedef struct drm_mga_iload { + int idx; + unsigned int dstorg; + unsigned int length; +} drm_mga_iload_t; + +typedef struct _drm_mga_blit { + unsigned int planemask; + unsigned int srcorg; + unsigned int dstorg; + int src_pitch, dst_pitch; + int delta_sx, delta_sy; + int delta_dx, delta_dy; + int height, ydir; /* flip image vertically */ + int source_pitch, dest_pitch; +} drm_mga_blit_t; + +/* 3.1: An ioctl to get parameters that aren't available to the 3d + * client any other way. + */ +#define MGA_PARAM_IRQ_NR 1 + +/* 3.2: Query the actual card type. The DDX only distinguishes between + * G200 chips and non-G200 chips, which it calls G400. It turns out that + * there are some very sublte differences between the G4x0 chips and the G550 + * chips. Using this parameter query, a client-side driver can detect the + * difference between a G4x0 and a G550. + */ +#define MGA_PARAM_CARD_TYPE 2 + +typedef struct drm_mga_getparam { + int param; + void *value; +} drm_mga_getparam_t; + +#endif diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h new file mode 100644 index 0000000..b18cad0 --- /dev/null +++ b/include/drm/nouveau_drm.h @@ -0,0 +1,208 @@ +/* + * Copyright 2005 Stephane Marchesin. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __NOUVEAU_DRM_H__ +#define __NOUVEAU_DRM_H__ + +#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16 + +struct drm_nouveau_channel_alloc { + uint32_t fb_ctxdma_handle; + uint32_t tt_ctxdma_handle; + + int channel; + uint32_t pushbuf_domains; + + /* Notifier memory */ + uint32_t notifier_handle; + + /* DRM-enforced subchannel assignments */ + struct { + uint32_t handle; + uint32_t grclass; + } subchan[8]; + uint32_t nr_subchan; +}; + +struct drm_nouveau_channel_free { + int channel; +}; + +struct drm_nouveau_grobj_alloc { + int channel; + uint32_t handle; + int class; +}; + +struct drm_nouveau_notifierobj_alloc { + uint32_t channel; + uint32_t handle; + uint32_t size; + uint32_t offset; +}; + +struct drm_nouveau_gpuobj_free { + int channel; + uint32_t handle; +}; + +/* FIXME : maybe unify {GET,SET}PARAMs */ +#define NOUVEAU_GETPARAM_PCI_VENDOR 3 +#define NOUVEAU_GETPARAM_PCI_DEVICE 4 +#define NOUVEAU_GETPARAM_BUS_TYPE 5 +#define NOUVEAU_GETPARAM_FB_PHYSICAL 6 +#define NOUVEAU_GETPARAM_AGP_PHYSICAL 7 +#define NOUVEAU_GETPARAM_FB_SIZE 8 +#define NOUVEAU_GETPARAM_AGP_SIZE 9 +#define NOUVEAU_GETPARAM_PCI_PHYSICAL 10 +#define NOUVEAU_GETPARAM_CHIPSET_ID 11 +#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 +#define NOUVEAU_GETPARAM_GRAPH_UNITS 13 +#define NOUVEAU_GETPARAM_PTIMER_TIME 14 +#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 +#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16 +struct drm_nouveau_getparam { + uint64_t param; + uint64_t value; +}; + +struct drm_nouveau_setparam { + uint64_t param; + uint64_t value; +}; + +#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) +#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) +#define NOUVEAU_GEM_DOMAIN_GART (1 << 2) +#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3) + +#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00 +#define NOUVEAU_GEM_TILE_16BPP 0x00000001 +#define NOUVEAU_GEM_TILE_32BPP 0x00000002 +#define NOUVEAU_GEM_TILE_ZETA 0x00000004 +#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 + +struct drm_nouveau_gem_info { + uint32_t handle; + uint32_t domain; + uint64_t size; + uint64_t offset; + uint64_t map_handle; + uint32_t tile_mode; + uint32_t tile_flags; +}; + +struct drm_nouveau_gem_new { + struct drm_nouveau_gem_info info; + uint32_t channel_hint; + uint32_t align; +}; + +#define NOUVEAU_GEM_MAX_BUFFERS 1024 +struct drm_nouveau_gem_pushbuf_bo_presumed { + uint32_t valid; + uint32_t domain; + uint64_t offset; +}; + +struct drm_nouveau_gem_pushbuf_bo { + uint64_t user_priv; + uint32_t handle; + uint32_t read_domains; + uint32_t write_domains; + uint32_t valid_domains; + struct drm_nouveau_gem_pushbuf_bo_presumed presumed; +}; + +#define NOUVEAU_GEM_RELOC_LOW (1 << 0) +#define NOUVEAU_GEM_RELOC_HIGH (1 << 1) +#define NOUVEAU_GEM_RELOC_OR (1 << 2) +#define NOUVEAU_GEM_MAX_RELOCS 1024 +struct drm_nouveau_gem_pushbuf_reloc { + uint32_t reloc_bo_index; + uint32_t reloc_bo_offset; + uint32_t bo_index; + uint32_t flags; + uint32_t data; + uint32_t vor; + uint32_t tor; +}; + +#define NOUVEAU_GEM_MAX_PUSH 512 +struct drm_nouveau_gem_pushbuf_push { + uint32_t bo_index; + uint32_t pad; + uint64_t offset; + uint64_t length; +}; + +struct drm_nouveau_gem_pushbuf { + uint32_t channel; + uint32_t nr_buffers; + uint64_t buffers; + uint32_t nr_relocs; + uint32_t nr_push; + uint64_t relocs; + uint64_t push; + uint32_t suffix0; + uint32_t suffix1; + uint64_t vram_available; + uint64_t gart_available; +}; + +#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 +#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 +#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 +struct drm_nouveau_gem_cpu_prep { + uint32_t handle; + uint32_t flags; +}; + +struct drm_nouveau_gem_cpu_fini { + uint32_t handle; +}; + +enum nouveau_bus_type { + NV_AGP = 0, + NV_PCI = 1, + NV_PCIE = 2, +}; + +struct drm_nouveau_sarea { +}; + +#define DRM_NOUVEAU_GETPARAM 0x00 +#define DRM_NOUVEAU_SETPARAM 0x01 +#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 +#define DRM_NOUVEAU_CHANNEL_FREE 0x03 +#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 +#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 +#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 +#define DRM_NOUVEAU_GEM_NEW 0x40 +#define DRM_NOUVEAU_GEM_PUSHBUF 0x41 +#define DRM_NOUVEAU_GEM_CPU_PREP 0x42 +#define DRM_NOUVEAU_GEM_CPU_FINI 0x43 +#define DRM_NOUVEAU_GEM_INFO 0x44 + +#endif /* __NOUVEAU_DRM_H__ */ diff --git a/include/drm/r128_drm.h b/include/drm/r128_drm.h new file mode 100644 index 0000000..ede78ff --- /dev/null +++ b/include/drm/r128_drm.h @@ -0,0 +1,326 @@ +/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- + * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com + */ +/* + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Gareth Hughes + * Kevin E. Martin + */ + +#ifndef __R128_DRM_H__ +#define __R128_DRM_H__ + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the X server file (r128_sarea.h) + */ +#ifndef __R128_SAREA_DEFINES__ +#define __R128_SAREA_DEFINES__ + +/* What needs to be changed for the current vertex buffer? + */ +#define R128_UPLOAD_CONTEXT 0x001 +#define R128_UPLOAD_SETUP 0x002 +#define R128_UPLOAD_TEX0 0x004 +#define R128_UPLOAD_TEX1 0x008 +#define R128_UPLOAD_TEX0IMAGES 0x010 +#define R128_UPLOAD_TEX1IMAGES 0x020 +#define R128_UPLOAD_CORE 0x040 +#define R128_UPLOAD_MASKS 0x080 +#define R128_UPLOAD_WINDOW 0x100 +#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ +#define R128_REQUIRE_QUIESCENCE 0x400 +#define R128_UPLOAD_ALL 0x7ff + +#define R128_FRONT 0x1 +#define R128_BACK 0x2 +#define R128_DEPTH 0x4 + +/* Primitive types + */ +#define R128_POINTS 0x1 +#define R128_LINES 0x2 +#define R128_LINE_STRIP 0x3 +#define R128_TRIANGLES 0x4 +#define R128_TRIANGLE_FAN 0x5 +#define R128_TRIANGLE_STRIP 0x6 + +/* Vertex/indirect buffer size + */ +#define R128_BUFFER_SIZE 16384 + +/* Byte offsets for indirect buffer data + */ +#define R128_INDEX_PRIM_OFFSET 20 +#define R128_HOSTDATA_BLIT_OFFSET 32 + +/* Keep these small for testing. + */ +#define R128_NR_SAREA_CLIPRECTS 12 + +/* There are 2 heaps (local/AGP). Each region within a heap is a + * minimum of 64k, and there are at most 64 of them per heap. + */ +#define R128_LOCAL_TEX_HEAP 0 +#define R128_AGP_TEX_HEAP 1 +#define R128_NR_TEX_HEAPS 2 +#define R128_NR_TEX_REGIONS 64 +#define R128_LOG_TEX_GRANULARITY 16 + +#define R128_NR_CONTEXT_REGS 12 + +#define R128_MAX_TEXTURE_LEVELS 11 +#define R128_MAX_TEXTURE_UNITS 2 + +#endif /* __R128_SAREA_DEFINES__ */ + +typedef struct { + /* Context state - can be written in one large chunk */ + unsigned int dst_pitch_offset_c; + unsigned int dp_gui_master_cntl_c; + unsigned int sc_top_left_c; + unsigned int sc_bottom_right_c; + unsigned int z_offset_c; + unsigned int z_pitch_c; + unsigned int z_sten_cntl_c; + unsigned int tex_cntl_c; + unsigned int misc_3d_state_cntl_reg; + unsigned int texture_clr_cmp_clr_c; + unsigned int texture_clr_cmp_msk_c; + unsigned int fog_color_c; + + /* Texture state */ + unsigned int tex_size_pitch_c; + unsigned int constant_color_c; + + /* Setup state */ + unsigned int pm4_vc_fpu_setup; + unsigned int setup_cntl; + + /* Mask state */ + unsigned int dp_write_mask; + unsigned int sten_ref_mask_c; + unsigned int plane_3d_mask_c; + + /* Window state */ + unsigned int window_xy_offset; + + /* Core state */ + unsigned int scale_3d_cntl; +} drm_r128_context_regs_t; + +/* Setup registers for each texture unit + */ +typedef struct { + unsigned int tex_cntl; + unsigned int tex_combine_cntl; + unsigned int tex_size_pitch; + unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS]; + unsigned int tex_border_color; +} drm_r128_texture_regs_t; + +typedef struct drm_r128_sarea { + /* The channel for communication of state information to the kernel + * on firing a vertex buffer. + */ + drm_r128_context_regs_t context_state; + drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS]; + unsigned int dirty; + unsigned int vertsize; + unsigned int vc_format; + + /* The current cliprects, or a subset thereof. + */ + struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS]; + unsigned int nbox; + + /* Counters for client-side throttling of rendering clients. + */ + unsigned int last_frame; + unsigned int last_dispatch; + + struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1]; + unsigned int tex_age[R128_NR_TEX_HEAPS]; + int ctx_owner; + int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ + int pfCurrentPage; /* which buffer is being displayed? */ +} drm_r128_sarea_t; + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmR128.h) + */ + +/* Rage 128 specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_R128_INIT 0x00 +#define DRM_R128_CCE_START 0x01 +#define DRM_R128_CCE_STOP 0x02 +#define DRM_R128_CCE_RESET 0x03 +#define DRM_R128_CCE_IDLE 0x04 +/* 0x05 not used */ +#define DRM_R128_RESET 0x06 +#define DRM_R128_SWAP 0x07 +#define DRM_R128_CLEAR 0x08 +#define DRM_R128_VERTEX 0x09 +#define DRM_R128_INDICES 0x0a +#define DRM_R128_BLIT 0x0b +#define DRM_R128_DEPTH 0x0c +#define DRM_R128_STIPPLE 0x0d +/* 0x0e not used */ +#define DRM_R128_INDIRECT 0x0f +#define DRM_R128_FULLSCREEN 0x10 +#define DRM_R128_CLEAR2 0x11 +#define DRM_R128_GETPARAM 0x12 +#define DRM_R128_FLIP 0x13 + +#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t) +#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START) +#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t) +#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET) +#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE) +/* 0x05 not used */ +#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET) +#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP) +#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t) +#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t) +#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t) +#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t) +#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t) +#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t) +/* 0x0e not used */ +#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t) +#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t) +#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t) +#define DRM_IOCTL_R128_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t) +#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP) + +typedef struct drm_r128_init { + enum { + R128_INIT_CCE = 0x01, + R128_CLEANUP_CCE = 0x02 + } func; + unsigned long sarea_priv_offset; + int is_pci; + int cce_mode; + int cce_secure; + int ring_size; + int usec_timeout; + + unsigned int fb_bpp; + unsigned int front_offset, front_pitch; + unsigned int back_offset, back_pitch; + unsigned int depth_bpp; + unsigned int depth_offset, depth_pitch; + unsigned int span_offset; + + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long ring_offset; + unsigned long ring_rptr_offset; + unsigned long buffers_offset; + unsigned long agp_textures_offset; +} drm_r128_init_t; + +typedef struct drm_r128_cce_stop { + int flush; + int idle; +} drm_r128_cce_stop_t; + +typedef struct drm_r128_clear { + unsigned int flags; + unsigned int clear_color; + unsigned int clear_depth; + unsigned int color_mask; + unsigned int depth_mask; +} drm_r128_clear_t; + +typedef struct drm_r128_vertex { + int prim; + int idx; /* Index of vertex buffer */ + int count; /* Number of vertices in buffer */ + int discard; /* Client finished with buffer? */ +} drm_r128_vertex_t; + +typedef struct drm_r128_indices { + int prim; + int idx; + int start; + int end; + int discard; /* Client finished with buffer? */ +} drm_r128_indices_t; + +typedef struct drm_r128_blit { + int idx; + int pitch; + int offset; + int format; + unsigned short x, y; + unsigned short width, height; +} drm_r128_blit_t; + +typedef struct drm_r128_depth { + enum { + R128_WRITE_SPAN = 0x01, + R128_WRITE_PIXELS = 0x02, + R128_READ_SPAN = 0x03, + R128_READ_PIXELS = 0x04 + } func; + int n; + int *x; + int *y; + unsigned int *buffer; + unsigned char *mask; +} drm_r128_depth_t; + +typedef struct drm_r128_stipple { + unsigned int *mask; +} drm_r128_stipple_t; + +typedef struct drm_r128_indirect { + int idx; + int start; + int end; + int discard; +} drm_r128_indirect_t; + +typedef struct drm_r128_fullscreen { + enum { + R128_INIT_FULLSCREEN = 0x01, + R128_CLEANUP_FULLSCREEN = 0x02 + } func; +} drm_r128_fullscreen_t; + +/* 2.3: An ioctl to get parameters that aren't available to the 3d + * client any other way. + */ +#define R128_PARAM_IRQ_NR 1 + +typedef struct drm_r128_getparam { + int param; + void *value; +} drm_r128_getparam_t; + +#endif diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h new file mode 100644 index 0000000..00d66b3 --- /dev/null +++ b/include/drm/radeon_drm.h @@ -0,0 +1,926 @@ +/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- + * + * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. + * All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Kevin E. Martin + * Gareth Hughes + * Keith Whitwell + */ + +#ifndef __RADEON_DRM_H__ +#define __RADEON_DRM_H__ + +#include "drm.h" + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the X server file (radeon_sarea.h) + */ +#ifndef __RADEON_SAREA_DEFINES__ +#define __RADEON_SAREA_DEFINES__ + +/* Old style state flags, required for sarea interface (1.1 and 1.2 + * clears) and 1.2 drm_vertex2 ioctl. + */ +#define RADEON_UPLOAD_CONTEXT 0x00000001 +#define RADEON_UPLOAD_VERTFMT 0x00000002 +#define RADEON_UPLOAD_LINE 0x00000004 +#define RADEON_UPLOAD_BUMPMAP 0x00000008 +#define RADEON_UPLOAD_MASKS 0x00000010 +#define RADEON_UPLOAD_VIEWPORT 0x00000020 +#define RADEON_UPLOAD_SETUP 0x00000040 +#define RADEON_UPLOAD_TCL 0x00000080 +#define RADEON_UPLOAD_MISC 0x00000100 +#define RADEON_UPLOAD_TEX0 0x00000200 +#define RADEON_UPLOAD_TEX1 0x00000400 +#define RADEON_UPLOAD_TEX2 0x00000800 +#define RADEON_UPLOAD_TEX0IMAGES 0x00001000 +#define RADEON_UPLOAD_TEX1IMAGES 0x00002000 +#define RADEON_UPLOAD_TEX2IMAGES 0x00004000 +#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ +#define RADEON_REQUIRE_QUIESCENCE 0x00010000 +#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ +#define RADEON_UPLOAD_ALL 0x003effff +#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff + +/* New style per-packet identifiers for use in cmd_buffer ioctl with + * the RADEON_EMIT_PACKET command. Comments relate new packets to old + * state bits and the packet size: + */ +#define RADEON_EMIT_PP_MISC 0 /* context/7 */ +#define RADEON_EMIT_PP_CNTL 1 /* context/3 */ +#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ +#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ +#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ +#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ +#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ +#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ +#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ +#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ +#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ +#define RADEON_EMIT_RE_MISC 11 /* misc/1 */ +#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ +#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ +#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ +#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ +#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ +#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ +#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ +#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ +#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ +#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ +#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ +#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ +#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ +#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ +#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ +#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ +#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ +#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ +#define R200_EMIT_TFACTOR_0 30 /* tf/7 */ +#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ +#define R200_EMIT_VAP_CTL 32 /* vap/1 */ +#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ +#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ +#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ +#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ +#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ +#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ +#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ +#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ +#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ +#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ +#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ +#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ +#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ +#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ +#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ +#define R200_EMIT_VTE_CNTL 48 /* vte/1 */ +#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ +#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ +#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ +#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ +#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ +#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ +#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ +#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ +#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ +#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ +#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ +#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ +#define R200_EMIT_PP_CUBIC_FACES_0 61 +#define R200_EMIT_PP_CUBIC_OFFSETS_0 62 +#define R200_EMIT_PP_CUBIC_FACES_1 63 +#define R200_EMIT_PP_CUBIC_OFFSETS_1 64 +#define R200_EMIT_PP_CUBIC_FACES_2 65 +#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 +#define R200_EMIT_PP_CUBIC_FACES_3 67 +#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 +#define R200_EMIT_PP_CUBIC_FACES_4 69 +#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 +#define R200_EMIT_PP_CUBIC_FACES_5 71 +#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 +#define RADEON_EMIT_PP_TEX_SIZE_0 73 +#define RADEON_EMIT_PP_TEX_SIZE_1 74 +#define RADEON_EMIT_PP_TEX_SIZE_2 75 +#define R200_EMIT_RB3D_BLENDCOLOR 76 +#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 +#define RADEON_EMIT_PP_CUBIC_FACES_0 78 +#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 +#define RADEON_EMIT_PP_CUBIC_FACES_1 80 +#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 +#define RADEON_EMIT_PP_CUBIC_FACES_2 82 +#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 +#define R200_EMIT_PP_TRI_PERF_CNTL 84 +#define R200_EMIT_PP_AFS_0 85 +#define R200_EMIT_PP_AFS_1 86 +#define R200_EMIT_ATF_TFACTOR 87 +#define R200_EMIT_PP_TXCTLALL_0 88 +#define R200_EMIT_PP_TXCTLALL_1 89 +#define R200_EMIT_PP_TXCTLALL_2 90 +#define R200_EMIT_PP_TXCTLALL_3 91 +#define R200_EMIT_PP_TXCTLALL_4 92 +#define R200_EMIT_PP_TXCTLALL_5 93 +#define R200_EMIT_VAP_PVS_CNTL 94 +#define RADEON_MAX_STATE_PACKETS 95 + +/* Commands understood by cmd_buffer ioctl. More can be added but + * obviously these can't be removed or changed: + */ +#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ +#define RADEON_CMD_SCALARS 2 /* emit scalar data */ +#define RADEON_CMD_VECTORS 3 /* emit vector data */ +#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ +#define RADEON_CMD_PACKET3 5 /* emit hw packet */ +#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ +#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ +#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: + * doesn't make the cpu wait, just + * the graphics hardware */ +#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ + +typedef union { + int i; + struct { + unsigned char cmd_type, pad0, pad1, pad2; + } header; + struct { + unsigned char cmd_type, packet_id, pad0, pad1; + } packet; + struct { + unsigned char cmd_type, offset, stride, count; + } scalars; + struct { + unsigned char cmd_type, offset, stride, count; + } vectors; + struct { + unsigned char cmd_type, addr_lo, addr_hi, count; + } veclinear; + struct { + unsigned char cmd_type, buf_idx, pad0, pad1; + } dma; + struct { + unsigned char cmd_type, flags, pad0, pad1; + } wait; +} drm_radeon_cmd_header_t; + +#define RADEON_WAIT_2D 0x1 +#define RADEON_WAIT_3D 0x2 + +/* Allowed parameters for R300_CMD_PACKET3 + */ +#define R300_CMD_PACKET3_CLEAR 0 +#define R300_CMD_PACKET3_RAW 1 + +/* Commands understood by cmd_buffer ioctl for R300. + * The interface has not been stabilized, so some of these may be removed + * and eventually reordered before stabilization. + */ +#define R300_CMD_PACKET0 1 +#define R300_CMD_VPU 2 /* emit vertex program upload */ +#define R300_CMD_PACKET3 3 /* emit a packet3 */ +#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ +#define R300_CMD_CP_DELAY 5 +#define R300_CMD_DMA_DISCARD 6 +#define R300_CMD_WAIT 7 +# define R300_WAIT_2D 0x1 +# define R300_WAIT_3D 0x2 +/* these two defines are DOING IT WRONG - however + * we have userspace which relies on using these. + * The wait interface is backwards compat new + * code should use the NEW_WAIT defines below + * THESE ARE NOT BIT FIELDS + */ +# define R300_WAIT_2D_CLEAN 0x3 +# define R300_WAIT_3D_CLEAN 0x4 + +# define R300_NEW_WAIT_2D_3D 0x3 +# define R300_NEW_WAIT_2D_2D_CLEAN 0x4 +# define R300_NEW_WAIT_3D_3D_CLEAN 0x6 +# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 + +#define R300_CMD_SCRATCH 8 +#define R300_CMD_R500FP 9 + +typedef union { + unsigned int u; + struct { + unsigned char cmd_type, pad0, pad1, pad2; + } header; + struct { + unsigned char cmd_type, count, reglo, reghi; + } packet0; + struct { + unsigned char cmd_type, count, adrlo, adrhi; + } vpu; + struct { + unsigned char cmd_type, packet, pad0, pad1; + } packet3; + struct { + unsigned char cmd_type, packet; + unsigned short count; /* amount of packet2 to emit */ + } delay; + struct { + unsigned char cmd_type, buf_idx, pad0, pad1; + } dma; + struct { + unsigned char cmd_type, flags, pad0, pad1; + } wait; + struct { + unsigned char cmd_type, reg, n_bufs, flags; + } scratch; + struct { + unsigned char cmd_type, count, adrlo, adrhi_flags; + } r500fp; +} drm_r300_cmd_header_t; + +#define RADEON_FRONT 0x1 +#define RADEON_BACK 0x2 +#define RADEON_DEPTH 0x4 +#define RADEON_STENCIL 0x8 +#define RADEON_CLEAR_FASTZ 0x80000000 +#define RADEON_USE_HIERZ 0x40000000 +#define RADEON_USE_COMP_ZBUF 0x20000000 + +#define R500FP_CONSTANT_TYPE (1 << 1) +#define R500FP_CONSTANT_CLAMP (1 << 2) + +/* Primitive types + */ +#define RADEON_POINTS 0x1 +#define RADEON_LINES 0x2 +#define RADEON_LINE_STRIP 0x3 +#define RADEON_TRIANGLES 0x4 +#define RADEON_TRIANGLE_FAN 0x5 +#define RADEON_TRIANGLE_STRIP 0x6 + +/* Vertex/indirect buffer size + */ +#define RADEON_BUFFER_SIZE 65536 + +/* Byte offsets for indirect buffer data + */ +#define RADEON_INDEX_PRIM_OFFSET 20 + +#define RADEON_SCRATCH_REG_OFFSET 32 + +#define R600_SCRATCH_REG_OFFSET 256 + +#define RADEON_NR_SAREA_CLIPRECTS 12 + +/* There are 2 heaps (local/GART). Each region within a heap is a + * minimum of 64k, and there are at most 64 of them per heap. + */ +#define RADEON_LOCAL_TEX_HEAP 0 +#define RADEON_GART_TEX_HEAP 1 +#define RADEON_NR_TEX_HEAPS 2 +#define RADEON_NR_TEX_REGIONS 64 +#define RADEON_LOG_TEX_GRANULARITY 16 + +#define RADEON_MAX_TEXTURE_LEVELS 12 +#define RADEON_MAX_TEXTURE_UNITS 3 + +#define RADEON_MAX_SURFACES 8 + +/* Blits have strict offset rules. All blit offset must be aligned on + * a 1K-byte boundary. + */ +#define RADEON_OFFSET_SHIFT 10 +#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) +#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) + +#endif /* __RADEON_SAREA_DEFINES__ */ + +typedef struct { + unsigned int red; + unsigned int green; + unsigned int blue; + unsigned int alpha; +} radeon_color_regs_t; + +typedef struct { + /* Context state */ + unsigned int pp_misc; /* 0x1c14 */ + unsigned int pp_fog_color; + unsigned int re_solid_color; + unsigned int rb3d_blendcntl; + unsigned int rb3d_depthoffset; + unsigned int rb3d_depthpitch; + unsigned int rb3d_zstencilcntl; + + unsigned int pp_cntl; /* 0x1c38 */ + unsigned int rb3d_cntl; + unsigned int rb3d_coloroffset; + unsigned int re_width_height; + unsigned int rb3d_colorpitch; + unsigned int se_cntl; + + /* Vertex format state */ + unsigned int se_coord_fmt; /* 0x1c50 */ + + /* Line state */ + unsigned int re_line_pattern; /* 0x1cd0 */ + unsigned int re_line_state; + + unsigned int se_line_width; /* 0x1db8 */ + + /* Bumpmap state */ + unsigned int pp_lum_matrix; /* 0x1d00 */ + + unsigned int pp_rot_matrix_0; /* 0x1d58 */ + unsigned int pp_rot_matrix_1; + + /* Mask state */ + unsigned int rb3d_stencilrefmask; /* 0x1d7c */ + unsigned int rb3d_ropcntl; + unsigned int rb3d_planemask; + + /* Viewport state */ + unsigned int se_vport_xscale; /* 0x1d98 */ + unsigned int se_vport_xoffset; + unsigned int se_vport_yscale; + unsigned int se_vport_yoffset; + unsigned int se_vport_zscale; + unsigned int se_vport_zoffset; + + /* Setup state */ + unsigned int se_cntl_status; /* 0x2140 */ + + /* Misc state */ + unsigned int re_top_left; /* 0x26c0 */ + unsigned int re_misc; +} drm_radeon_context_regs_t; + +typedef struct { + /* Zbias state */ + unsigned int se_zbias_factor; /* 0x1dac */ + unsigned int se_zbias_constant; +} drm_radeon_context2_regs_t; + +/* Setup registers for each texture unit + */ +typedef struct { + unsigned int pp_txfilter; + unsigned int pp_txformat; + unsigned int pp_txoffset; + unsigned int pp_txcblend; + unsigned int pp_txablend; + unsigned int pp_tfactor; + unsigned int pp_border_color; +} drm_radeon_texture_regs_t; + +typedef struct { + unsigned int start; + unsigned int finish; + unsigned int prim:8; + unsigned int stateidx:8; + unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ + unsigned int vc_format; /* vertex format */ +} drm_radeon_prim_t; + +typedef struct { + drm_radeon_context_regs_t context; + drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; + drm_radeon_context2_regs_t context2; + unsigned int dirty; +} drm_radeon_state_t; + +typedef struct { + /* The channel for communication of state information to the + * kernel on firing a vertex buffer with either of the + * obsoleted vertex/index ioctls. + */ + drm_radeon_context_regs_t context_state; + drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; + unsigned int dirty; + unsigned int vertsize; + unsigned int vc_format; + + /* The current cliprects, or a subset thereof. + */ + struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; + unsigned int nbox; + + /* Counters for client-side throttling of rendering clients. + */ + unsigned int last_frame; + unsigned int last_dispatch; + unsigned int last_clear; + + struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + + 1]; + unsigned int tex_age[RADEON_NR_TEX_HEAPS]; + int ctx_owner; + int pfState; /* number of 3d windows (0,1,2ormore) */ + int pfCurrentPage; /* which buffer is being displayed? */ + int crtc2_base; /* CRTC2 frame offset */ + int tiling_enabled; /* set by drm, read by 2d + 3d clients */ +} drm_radeon_sarea_t; + +/* WARNING: If you change any of these defines, make sure to change the + * defines in the Xserver file (xf86drmRadeon.h) + * + * KW: actually it's illegal to change any of this (backwards compatibility). + */ + +/* Radeon specific ioctls + * The device specific ioctl range is 0x40 to 0x79. + */ +#define DRM_RADEON_CP_INIT 0x00 +#define DRM_RADEON_CP_START 0x01 +#define DRM_RADEON_CP_STOP 0x02 +#define DRM_RADEON_CP_RESET 0x03 +#define DRM_RADEON_CP_IDLE 0x04 +#define DRM_RADEON_RESET 0x05 +#define DRM_RADEON_FULLSCREEN 0x06 +#define DRM_RADEON_SWAP 0x07 +#define DRM_RADEON_CLEAR 0x08 +#define DRM_RADEON_VERTEX 0x09 +#define DRM_RADEON_INDICES 0x0A +#define DRM_RADEON_NOT_USED +#define DRM_RADEON_STIPPLE 0x0C +#define DRM_RADEON_INDIRECT 0x0D +#define DRM_RADEON_TEXTURE 0x0E +#define DRM_RADEON_VERTEX2 0x0F +#define DRM_RADEON_CMDBUF 0x10 +#define DRM_RADEON_GETPARAM 0x11 +#define DRM_RADEON_FLIP 0x12 +#define DRM_RADEON_ALLOC 0x13 +#define DRM_RADEON_FREE 0x14 +#define DRM_RADEON_INIT_HEAP 0x15 +#define DRM_RADEON_IRQ_EMIT 0x16 +#define DRM_RADEON_IRQ_WAIT 0x17 +#define DRM_RADEON_CP_RESUME 0x18 +#define DRM_RADEON_SETPARAM 0x19 +#define DRM_RADEON_SURF_ALLOC 0x1a +#define DRM_RADEON_SURF_FREE 0x1b +/* KMS ioctl */ +#define DRM_RADEON_GEM_INFO 0x1c +#define DRM_RADEON_GEM_CREATE 0x1d +#define DRM_RADEON_GEM_MMAP 0x1e +#define DRM_RADEON_GEM_PREAD 0x21 +#define DRM_RADEON_GEM_PWRITE 0x22 +#define DRM_RADEON_GEM_SET_DOMAIN 0x23 +#define DRM_RADEON_GEM_WAIT_IDLE 0x24 +#define DRM_RADEON_CS 0x26 +#define DRM_RADEON_INFO 0x27 +#define DRM_RADEON_GEM_SET_TILING 0x28 +#define DRM_RADEON_GEM_GET_TILING 0x29 +#define DRM_RADEON_GEM_BUSY 0x2a + +#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) +#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) +#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) +#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) +#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) +#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) +#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) +#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) +#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) +#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) +#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) +#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) +#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) +#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) +#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) +#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) +#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) +#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) +#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) +#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) +#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) +#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) +#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) +#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) +#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) +#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) +#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) +/* KMS */ +#define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) +#define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) +#define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) +#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) +#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) +#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) +#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) +#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) +#define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) +#define DRM_IOCTL_RADEON_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) +#define DRM_IOCTL_RADEON_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) +#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) + +typedef struct drm_radeon_init { + enum { + RADEON_INIT_CP = 0x01, + RADEON_CLEANUP_CP = 0x02, + RADEON_INIT_R200_CP = 0x03, + RADEON_INIT_R300_CP = 0x04, + RADEON_INIT_R600_CP = 0x05 + } func; + unsigned long sarea_priv_offset; + int is_pci; + int cp_mode; + int gart_size; + int ring_size; + int usec_timeout; + + unsigned int fb_bpp; + unsigned int front_offset, front_pitch; + unsigned int back_offset, back_pitch; + unsigned int depth_bpp; + unsigned int depth_offset, depth_pitch; + + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long ring_offset; + unsigned long ring_rptr_offset; + unsigned long buffers_offset; + unsigned long gart_textures_offset; +} drm_radeon_init_t; + +typedef struct drm_radeon_cp_stop { + int flush; + int idle; +} drm_radeon_cp_stop_t; + +typedef struct drm_radeon_fullscreen { + enum { + RADEON_INIT_FULLSCREEN = 0x01, + RADEON_CLEANUP_FULLSCREEN = 0x02 + } func; +} drm_radeon_fullscreen_t; + +#define CLEAR_X1 0 +#define CLEAR_Y1 1 +#define CLEAR_X2 2 +#define CLEAR_Y2 3 +#define CLEAR_DEPTH 4 + +typedef union drm_radeon_clear_rect { + float f[5]; + unsigned int ui[5]; +} drm_radeon_clear_rect_t; + +typedef struct drm_radeon_clear { + unsigned int flags; + unsigned int clear_color; + unsigned int clear_depth; + unsigned int color_mask; + unsigned int depth_mask; /* misnamed field: should be stencil */ + drm_radeon_clear_rect_t *depth_boxes; +} drm_radeon_clear_t; + +typedef struct drm_radeon_vertex { + int prim; + int idx; /* Index of vertex buffer */ + int count; /* Number of vertices in buffer */ + int discard; /* Client finished with buffer? */ +} drm_radeon_vertex_t; + +typedef struct drm_radeon_indices { + int prim; + int idx; + int start; + int end; + int discard; /* Client finished with buffer? */ +} drm_radeon_indices_t; + +/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices + * - allows multiple primitives and state changes in a single ioctl + * - supports driver change to emit native primitives + */ +typedef struct drm_radeon_vertex2 { + int idx; /* Index of vertex buffer */ + int discard; /* Client finished with buffer? */ + int nr_states; + drm_radeon_state_t *state; + int nr_prims; + drm_radeon_prim_t *prim; +} drm_radeon_vertex2_t; + +/* v1.3 - obsoletes drm_radeon_vertex2 + * - allows arbitarily large cliprect list + * - allows updating of tcl packet, vector and scalar state + * - allows memory-efficient description of state updates + * - allows state to be emitted without a primitive + * (for clears, ctx switches) + * - allows more than one dma buffer to be referenced per ioctl + * - supports tcl driver + * - may be extended in future versions with new cmd types, packets + */ +typedef struct drm_radeon_cmd_buffer { + int bufsz; + char *buf; + int nbox; + struct drm_clip_rect *boxes; +} drm_radeon_cmd_buffer_t; + +typedef struct drm_radeon_tex_image { + unsigned int x, y; /* Blit coordinates */ + unsigned int width, height; + const void *data; +} drm_radeon_tex_image_t; + +typedef struct drm_radeon_texture { + unsigned int offset; + int pitch; + int format; + int width; /* Texture image coordinates */ + int height; + drm_radeon_tex_image_t *image; +} drm_radeon_texture_t; + +typedef struct drm_radeon_stipple { + unsigned int *mask; +} drm_radeon_stipple_t; + +typedef struct drm_radeon_indirect { + int idx; + int start; + int end; + int discard; +} drm_radeon_indirect_t; + +/* enum for card type parameters */ +#define RADEON_CARD_PCI 0 +#define RADEON_CARD_AGP 1 +#define RADEON_CARD_PCIE 2 + +/* 1.3: An ioctl to get parameters that aren't available to the 3d + * client any other way. + */ +#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ +#define RADEON_PARAM_LAST_FRAME 2 +#define RADEON_PARAM_LAST_DISPATCH 3 +#define RADEON_PARAM_LAST_CLEAR 4 +/* Added with DRM version 1.6. */ +#define RADEON_PARAM_IRQ_NR 5 +#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ +/* Added with DRM version 1.8. */ +#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ +#define RADEON_PARAM_STATUS_HANDLE 8 +#define RADEON_PARAM_SAREA_HANDLE 9 +#define RADEON_PARAM_GART_TEX_HANDLE 10 +#define RADEON_PARAM_SCRATCH_OFFSET 11 +#define RADEON_PARAM_CARD_TYPE 12 +#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ +#define RADEON_PARAM_FB_LOCATION 14 /* FB location */ +#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ +#define RADEON_PARAM_DEVICE_ID 16 +#define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ + +typedef struct drm_radeon_getparam { + int param; + void *value; +} drm_radeon_getparam_t; + +/* 1.6: Set up a memory manager for regions of shared memory: + */ +#define RADEON_MEM_REGION_GART 1 +#define RADEON_MEM_REGION_FB 2 + +typedef struct drm_radeon_mem_alloc { + int region; + int alignment; + int size; + int *region_offset; /* offset from start of fb or GART */ +} drm_radeon_mem_alloc_t; + +typedef struct drm_radeon_mem_free { + int region; + int region_offset; +} drm_radeon_mem_free_t; + +typedef struct drm_radeon_mem_init_heap { + int region; + int size; + int start; +} drm_radeon_mem_init_heap_t; + +/* 1.6: Userspace can request & wait on irq's: + */ +typedef struct drm_radeon_irq_emit { + int *irq_seq; +} drm_radeon_irq_emit_t; + +typedef struct drm_radeon_irq_wait { + int irq_seq; +} drm_radeon_irq_wait_t; + +/* 1.10: Clients tell the DRM where they think the framebuffer is located in + * the card's address space, via a new generic ioctl to set parameters + */ + +typedef struct drm_radeon_setparam { + unsigned int param; + __s64 value; +} drm_radeon_setparam_t; + +#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ +#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ +#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ +#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ +#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ +#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ +/* 1.14: Clients can allocate/free a surface + */ +typedef struct drm_radeon_surface_alloc { + unsigned int address; + unsigned int size; + unsigned int flags; +} drm_radeon_surface_alloc_t; + +typedef struct drm_radeon_surface_free { + unsigned int address; +} drm_radeon_surface_free_t; + +#define DRM_RADEON_VBLANK_CRTC1 1 +#define DRM_RADEON_VBLANK_CRTC2 2 + +/* + * Kernel modesetting world below. + */ +#define RADEON_GEM_DOMAIN_CPU 0x1 +#define RADEON_GEM_DOMAIN_GTT 0x2 +#define RADEON_GEM_DOMAIN_VRAM 0x4 + +struct drm_radeon_gem_info { + uint64_t gart_size; + uint64_t vram_size; + uint64_t vram_visible; +}; + +#define RADEON_GEM_NO_BACKING_STORE 1 + +struct drm_radeon_gem_create { + uint64_t size; + uint64_t alignment; + uint32_t handle; + uint32_t initial_domain; + uint32_t flags; +}; + +#define RADEON_TILING_MACRO 0x1 +#define RADEON_TILING_MICRO 0x2 +#define RADEON_TILING_SWAP_16BIT 0x4 +#define RADEON_TILING_SWAP_32BIT 0x8 +/* this object requires a surface when mapped - i.e. front buffer */ +#define RADEON_TILING_SURFACE 0x10 +#define RADEON_TILING_MICRO_SQUARE 0x20 +#define RADEON_TILING_EG_BANKW_SHIFT 8 +#define RADEON_TILING_EG_BANKW_MASK 0xf +#define RADEON_TILING_EG_BANKH_SHIFT 12 +#define RADEON_TILING_EG_BANKH_MASK 0xf +#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 +#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf +#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 +#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf +#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 +#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf + +struct drm_radeon_gem_set_tiling { + uint32_t handle; + uint32_t tiling_flags; + uint32_t pitch; +}; + +struct drm_radeon_gem_get_tiling { + uint32_t handle; + uint32_t tiling_flags; + uint32_t pitch; +}; + +struct drm_radeon_gem_mmap { + uint32_t handle; + uint32_t pad; + uint64_t offset; + uint64_t size; + uint64_t addr_ptr; +}; + +struct drm_radeon_gem_set_domain { + uint32_t handle; + uint32_t read_domains; + uint32_t write_domain; +}; + +struct drm_radeon_gem_wait_idle { + uint32_t handle; + uint32_t pad; +}; + +struct drm_radeon_gem_busy { + uint32_t handle; + uint32_t domain; +}; + +struct drm_radeon_gem_pread { + /** Handle for the object being read. */ + uint32_t handle; + uint32_t pad; + /** Offset into the object to read from */ + uint64_t offset; + /** Length of data to read */ + uint64_t size; + /** Pointer to write the data into. */ + /* void *, but pointers are not 32/64 compatible */ + uint64_t data_ptr; +}; + +struct drm_radeon_gem_pwrite { + /** Handle for the object being written to. */ + uint32_t handle; + uint32_t pad; + /** Offset into the object to write to */ + uint64_t offset; + /** Length of data to write */ + uint64_t size; + /** Pointer to read the data from. */ + /* void *, but pointers are not 32/64 compatible */ + uint64_t data_ptr; +}; + +#define RADEON_CHUNK_ID_RELOCS 0x01 +#define RADEON_CHUNK_ID_IB 0x02 + +struct drm_radeon_cs_chunk { + uint32_t chunk_id; + uint32_t length_dw; + uint64_t chunk_data; +}; + +struct drm_radeon_cs_reloc { + uint32_t handle; + uint32_t read_domains; + uint32_t write_domain; + uint32_t flags; +}; + +struct drm_radeon_cs { + uint32_t num_chunks; + uint32_t cs_id; + /* this points to uint64_t * which point to cs chunks */ + uint64_t chunks; + /* updates to the limits after this CS ioctl */ + uint64_t gart_limit; + uint64_t vram_limit; +}; + +#define RADEON_INFO_DEVICE_ID 0x00 +#define RADEON_INFO_NUM_GB_PIPES 0x01 +#define RADEON_INFO_NUM_Z_PIPES 0x02 +#define RADEON_INFO_ACCEL_WORKING 0x03 +#define RADEON_INFO_CRTC_FROM_ID 0x04 +#define RADEON_INFO_ACCEL_WORKING2 0x05 +#define RADEON_INFO_TILING_CONFIG 0x06 +#define RADEON_INFO_WANT_HYPERZ 0x07 + +struct drm_radeon_info { + uint32_t request; + uint32_t pad; + uint64_t value; +}; + +#endif diff --git a/include/drm/savage_drm.h b/include/drm/savage_drm.h new file mode 100644 index 0000000..f7a75ef --- /dev/null +++ b/include/drm/savage_drm.h @@ -0,0 +1,210 @@ +/* savage_drm.h -- Public header for the savage driver + * + * Copyright 2004 Felix Kuehling + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __SAVAGE_DRM_H__ +#define __SAVAGE_DRM_H__ + +#ifndef __SAVAGE_SAREA_DEFINES__ +#define __SAVAGE_SAREA_DEFINES__ + +/* 2 heaps (1 for card, 1 for agp), each divided into upto 128 + * regions, subject to a minimum region size of (1<<16) == 64k. + * + * Clients may subdivide regions internally, but when sharing between + * clients, the region size is the minimum granularity. + */ + +#define SAVAGE_CARD_HEAP 0 +#define SAVAGE_AGP_HEAP 1 +#define SAVAGE_NR_TEX_HEAPS 2 +#define SAVAGE_NR_TEX_REGIONS 16 +#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16 + +#endif /* __SAVAGE_SAREA_DEFINES__ */ + +typedef struct _drm_savage_sarea { + /* LRU lists for texture memory in agp space and on the card. + */ + struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS + + 1]; + unsigned int texAge[SAVAGE_NR_TEX_HEAPS]; + + /* Mechanism to validate card state. + */ + int ctxOwner; +} drm_savage_sarea_t, *drm_savage_sarea_ptr; + +/* Savage-specific ioctls + */ +#define DRM_SAVAGE_BCI_INIT 0x00 +#define DRM_SAVAGE_BCI_CMDBUF 0x01 +#define DRM_SAVAGE_BCI_EVENT_EMIT 0x02 +#define DRM_SAVAGE_BCI_EVENT_WAIT 0x03 + +#define DRM_IOCTL_SAVAGE_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t) +#define DRM_IOCTL_SAVAGE_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t) +#define DRM_IOCTL_SAVAGE_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t) +#define DRM_IOCTL_SAVAGE_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t) + +#define SAVAGE_DMA_PCI 1 +#define SAVAGE_DMA_AGP 3 +typedef struct drm_savage_init { + enum { + SAVAGE_INIT_BCI = 1, + SAVAGE_CLEANUP_BCI = 2 + } func; + unsigned int sarea_priv_offset; + + /* some parameters */ + unsigned int cob_size; + unsigned int bci_threshold_lo, bci_threshold_hi; + unsigned int dma_type; + + /* frame buffer layout */ + unsigned int fb_bpp; + unsigned int front_offset, front_pitch; + unsigned int back_offset, back_pitch; + unsigned int depth_bpp; + unsigned int depth_offset, depth_pitch; + + /* local textures */ + unsigned int texture_offset; + unsigned int texture_size; + + /* physical locations of non-permanent maps */ + unsigned long status_offset; + unsigned long buffers_offset; + unsigned long agp_textures_offset; + unsigned long cmd_dma_offset; +} drm_savage_init_t; + +typedef union drm_savage_cmd_header drm_savage_cmd_header_t; +typedef struct drm_savage_cmdbuf { + /* command buffer in client's address space */ + drm_savage_cmd_header_t *cmd_addr; + unsigned int size; /* size of the command buffer in 64bit units */ + + unsigned int dma_idx; /* DMA buffer index to use */ + int discard; /* discard DMA buffer when done */ + /* vertex buffer in client's address space */ + unsigned int *vb_addr; + unsigned int vb_size; /* size of client vertex buffer in bytes */ + unsigned int vb_stride; /* stride of vertices in 32bit words */ + /* boxes in client's address space */ + struct drm_clip_rect *box_addr; + unsigned int nbox; /* number of clipping boxes */ +} drm_savage_cmdbuf_t; + +#define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */ +#define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */ +#define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */ +typedef struct drm_savage_event { + unsigned int count; + unsigned int flags; +} drm_savage_event_emit_t, drm_savage_event_wait_t; + +/* Commands for the cmdbuf ioctl + */ +#define SAVAGE_CMD_STATE 0 /* a range of state registers */ +#define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */ +#define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */ +#define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */ +#define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */ +#define SAVAGE_CMD_CLEAR 5 /* clear buffers */ +#define SAVAGE_CMD_SWAP 6 /* swap buffers */ + +/* Primitive types +*/ +#define SAVAGE_PRIM_TRILIST 0 /* triangle list */ +#define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */ +#define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */ +#define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat + * shading on s3d */ + +/* Skip flags (vertex format) + */ +#define SAVAGE_SKIP_Z 0x01 +#define SAVAGE_SKIP_W 0x02 +#define SAVAGE_SKIP_C0 0x04 +#define SAVAGE_SKIP_C1 0x08 +#define SAVAGE_SKIP_S0 0x10 +#define SAVAGE_SKIP_T0 0x20 +#define SAVAGE_SKIP_ST0 0x30 +#define SAVAGE_SKIP_S1 0x40 +#define SAVAGE_SKIP_T1 0x80 +#define SAVAGE_SKIP_ST1 0xc0 +#define SAVAGE_SKIP_ALL_S3D 0x3f +#define SAVAGE_SKIP_ALL_S4 0xff + +/* Buffer names for clear command + */ +#define SAVAGE_FRONT 0x1 +#define SAVAGE_BACK 0x2 +#define SAVAGE_DEPTH 0x4 + +/* 64-bit command header + */ +union drm_savage_cmd_header { + struct { + unsigned char cmd; /* command */ + unsigned char pad0; + unsigned short pad1; + unsigned short pad2; + unsigned short pad3; + } cmd; /* generic */ + struct { + unsigned char cmd; + unsigned char global; /* need idle engine? */ + unsigned short count; /* number of consecutive registers */ + unsigned short start; /* first register */ + unsigned short pad3; + } state; /* SAVAGE_CMD_STATE */ + struct { + unsigned char cmd; + unsigned char prim; /* primitive type */ + unsigned short skip; /* vertex format (skip flags) */ + unsigned short count; /* number of vertices */ + unsigned short start; /* first vertex in DMA/vertex buffer */ + } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */ + struct { + unsigned char cmd; + unsigned char prim; + unsigned short skip; + unsigned short count; /* number of indices that follow */ + unsigned short pad3; + } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */ + struct { + unsigned char cmd; + unsigned char pad0; + unsigned short pad1; + unsigned int flags; + } clear0; /* SAVAGE_CMD_CLEAR */ + struct { + unsigned int mask; + unsigned int value; + } clear1; /* SAVAGE_CMD_CLEAR data */ +}; + +#endif diff --git a/include/drm/sis_drm.h b/include/drm/sis_drm.h new file mode 100644 index 0000000..30f7b38 --- /dev/null +++ b/include/drm/sis_drm.h @@ -0,0 +1,67 @@ +/* sis_drv.h -- Private header for sis driver -*- linux-c -*- */ +/* + * Copyright 2005 Eric Anholt + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + */ + +#ifndef __SIS_DRM_H__ +#define __SIS_DRM_H__ + +/* SiS specific ioctls */ +#define NOT_USED_0_3 +#define DRM_SIS_FB_ALLOC 0x04 +#define DRM_SIS_FB_FREE 0x05 +#define NOT_USED_6_12 +#define DRM_SIS_AGP_INIT 0x13 +#define DRM_SIS_AGP_ALLOC 0x14 +#define DRM_SIS_AGP_FREE 0x15 +#define DRM_SIS_FB_INIT 0x16 + +#define DRM_IOCTL_SIS_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_FB_ALLOC, drm_sis_mem_t) +#define DRM_IOCTL_SIS_FB_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_FREE, drm_sis_mem_t) +#define DRM_IOCTL_SIS_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_INIT, drm_sis_agp_t) +#define DRM_IOCTL_SIS_AGP_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_ALLOC, drm_sis_mem_t) +#define DRM_IOCTL_SIS_AGP_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_AGP_FREE, drm_sis_mem_t) +#define DRM_IOCTL_SIS_FB_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_INIT, drm_sis_fb_t) +/* +#define DRM_IOCTL_SIS_FLIP DRM_IOW( 0x48, drm_sis_flip_t) +#define DRM_IOCTL_SIS_FLIP_INIT DRM_IO( 0x49) +#define DRM_IOCTL_SIS_FLIP_FINAL DRM_IO( 0x50) +*/ + +typedef struct { + int context; + unsigned int offset; + unsigned int size; + unsigned long free; +} drm_sis_mem_t; + +typedef struct { + unsigned int offset, size; +} drm_sis_agp_t; + +typedef struct { + unsigned int offset, size; +} drm_sis_fb_t; + +#endif /* __SIS_DRM_H__ */ diff --git a/include/drm/via_drm.h b/include/drm/via_drm.h new file mode 100644 index 0000000..182f879 --- /dev/null +++ b/include/drm/via_drm.h @@ -0,0 +1,275 @@ +/* + * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef _VIA_DRM_H_ +#define _VIA_DRM_H_ + +#include "drm.h" + +/* WARNING: These defines must be the same as what the Xserver uses. + * if you change them, you must change the defines in the Xserver. + */ + +#ifndef _VIA_DEFINES_ +#define _VIA_DEFINES_ + +#include "via_drmclient.h" + +#define VIA_NR_SAREA_CLIPRECTS 8 +#define VIA_NR_XVMC_PORTS 10 +#define VIA_NR_XVMC_LOCKS 5 +#define VIA_MAX_CACHELINE_SIZE 64 +#define XVMCLOCKPTR(saPriv,lockNo) \ + ((__volatile__ struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \ + (VIA_MAX_CACHELINE_SIZE - 1)) & \ + ~(VIA_MAX_CACHELINE_SIZE - 1)) + \ + VIA_MAX_CACHELINE_SIZE*(lockNo))) + +/* Each region is a minimum of 64k, and there are at most 64 of them. + */ +#define VIA_NR_TEX_REGIONS 64 +#define VIA_LOG_MIN_TEX_REGION_SIZE 16 +#endif + +#define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ +#define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ +#define VIA_UPLOAD_CTX 0x4 +#define VIA_UPLOAD_BUFFERS 0x8 +#define VIA_UPLOAD_TEX0 0x10 +#define VIA_UPLOAD_TEX1 0x20 +#define VIA_UPLOAD_CLIPRECTS 0x40 +#define VIA_UPLOAD_ALL 0xff + +/* VIA specific ioctls */ +#define DRM_VIA_ALLOCMEM 0x00 +#define DRM_VIA_FREEMEM 0x01 +#define DRM_VIA_AGP_INIT 0x02 +#define DRM_VIA_FB_INIT 0x03 +#define DRM_VIA_MAP_INIT 0x04 +#define DRM_VIA_DEC_FUTEX 0x05 +#define NOT_USED +#define DRM_VIA_DMA_INIT 0x07 +#define DRM_VIA_CMDBUFFER 0x08 +#define DRM_VIA_FLUSH 0x09 +#define DRM_VIA_PCICMD 0x0a +#define DRM_VIA_CMDBUF_SIZE 0x0b +#define NOT_USED +#define DRM_VIA_WAIT_IRQ 0x0d +#define DRM_VIA_DMA_BLIT 0x0e +#define DRM_VIA_BLIT_SYNC 0x0f + +#define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t) +#define DRM_IOCTL_VIA_FREEMEM DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t) +#define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t) +#define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t) +#define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t) +#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t) +#define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t) +#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t) +#define DRM_IOCTL_VIA_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_VIA_FLUSH) +#define DRM_IOCTL_VIA_PCICMD DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t) +#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \ + drm_via_cmdbuf_size_t) +#define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t) +#define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t) +#define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t) + +/* Indices into buf.Setup where various bits of state are mirrored per + * context and per buffer. These can be fired at the card as a unit, + * or in a piecewise fashion as required. + */ + +#define VIA_TEX_SETUP_SIZE 8 + +/* Flags for clear ioctl + */ +#define VIA_FRONT 0x1 +#define VIA_BACK 0x2 +#define VIA_DEPTH 0x4 +#define VIA_STENCIL 0x8 +#define VIA_MEM_VIDEO 0 /* matches drm constant */ +#define VIA_MEM_AGP 1 /* matches drm constant */ +#define VIA_MEM_SYSTEM 2 +#define VIA_MEM_MIXED 3 +#define VIA_MEM_UNKNOWN 4 + +typedef struct { + __u32 offset; + __u32 size; +} drm_via_agp_t; + +typedef struct { + __u32 offset; + __u32 size; +} drm_via_fb_t; + +typedef struct { + __u32 context; + __u32 type; + __u32 size; + unsigned long index; + unsigned long offset; +} drm_via_mem_t; + +typedef struct _drm_via_init { + enum { + VIA_INIT_MAP = 0x01, + VIA_CLEANUP_MAP = 0x02 + } func; + + unsigned long sarea_priv_offset; + unsigned long fb_offset; + unsigned long mmio_offset; + unsigned long agpAddr; +} drm_via_init_t; + +typedef struct _drm_via_futex { + enum { + VIA_FUTEX_WAIT = 0x00, + VIA_FUTEX_WAKE = 0X01 + } func; + __u32 ms; + __u32 lock; + __u32 val; +} drm_via_futex_t; + +typedef struct _drm_via_dma_init { + enum { + VIA_INIT_DMA = 0x01, + VIA_CLEANUP_DMA = 0x02, + VIA_DMA_INITIALIZED = 0x03 + } func; + + unsigned long offset; + unsigned long size; + unsigned long reg_pause_addr; +} drm_via_dma_init_t; + +typedef struct _drm_via_cmdbuffer { + char *buf; + unsigned long size; +} drm_via_cmdbuffer_t; + +/* Warning: If you change the SAREA structure you must change the Xserver + * structure as well */ + +typedef struct _drm_via_tex_region { + unsigned char next, prev; /* indices to form a circular LRU */ + unsigned char inUse; /* owned by a client, or free? */ + int age; /* tracked by clients to update local LRU's */ +} drm_via_tex_region_t; + +typedef struct _drm_via_sarea { + unsigned int dirty; + unsigned int nbox; + struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS]; + drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1]; + int texAge; /* last time texture was uploaded */ + int ctxOwner; /* last context to upload state */ + int vertexPrim; + + /* + * Below is for XvMC. + * We want the lock integers alone on, and aligned to, a cache line. + * Therefore this somewhat strange construct. + */ + + char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)]; + + unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS]; + unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS]; + unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */ + + /* Used by the 3d driver only at this point, for pageflipping: + */ + unsigned int pfCurrentOffset; +} drm_via_sarea_t; + +typedef struct _drm_via_cmdbuf_size { + enum { + VIA_CMDBUF_SPACE = 0x01, + VIA_CMDBUF_LAG = 0x02 + } func; + int wait; + __u32 size; +} drm_via_cmdbuf_size_t; + +typedef enum { + VIA_IRQ_ABSOLUTE = 0x0, + VIA_IRQ_RELATIVE = 0x1, + VIA_IRQ_SIGNAL = 0x10000000, + VIA_IRQ_FORCE_SEQUENCE = 0x20000000 +} via_irq_seq_type_t; + +#define VIA_IRQ_FLAGS_MASK 0xF0000000 + +enum drm_via_irqs { + drm_via_irq_hqv0 = 0, + drm_via_irq_hqv1, + drm_via_irq_dma0_dd, + drm_via_irq_dma0_td, + drm_via_irq_dma1_dd, + drm_via_irq_dma1_td, + drm_via_irq_num +}; + +struct drm_via_wait_irq_request { + unsigned irq; + via_irq_seq_type_t type; + __u32 sequence; + __u32 signal; +}; + +typedef union drm_via_irqwait { + struct drm_via_wait_irq_request request; + struct drm_wait_vblank_reply reply; +} drm_via_irqwait_t; + +typedef struct drm_via_blitsync { + __u32 sync_handle; + unsigned engine; +} drm_via_blitsync_t; + +/* - * Below,"flags" is currently unused but will be used for possible future + * extensions like kernel space bounce buffers for bad alignments and + * blit engine busy-wait polling for better latency in the absence of + * interrupts. + */ + +typedef struct drm_via_dmablit { + __u32 num_lines; + __u32 line_length; + + __u32 fb_addr; + __u32 fb_stride; + + unsigned char *mem_addr; + __u32 mem_stride; + + __u32 flags; + int to_fb; + + drm_via_blitsync_t sync; +} drm_via_dmablit_t; + +#endif /* _VIA_DRM_H_ */ diff --git a/include/drm/vmwgfx_drm.h b/include/drm/vmwgfx_drm.h new file mode 100644 index 0000000..4d08423 --- /dev/null +++ b/include/drm/vmwgfx_drm.h @@ -0,0 +1,614 @@ +/************************************************************************** + * + * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +#ifndef __VMWGFX_DRM_H__ +#define __VMWGFX_DRM_H__ + +#define DRM_VMW_MAX_SURFACE_FACES 6 +#define DRM_VMW_MAX_MIP_LEVELS 24 + +#define DRM_VMW_EXT_NAME_LEN 128 + +#define DRM_VMW_GET_PARAM 0 +#define DRM_VMW_ALLOC_DMABUF 1 +#define DRM_VMW_UNREF_DMABUF 2 +#define DRM_VMW_CURSOR_BYPASS 3 +/* guarded by DRM_VMW_PARAM_NUM_STREAMS != 0*/ +#define DRM_VMW_CONTROL_STREAM 4 +#define DRM_VMW_CLAIM_STREAM 5 +#define DRM_VMW_UNREF_STREAM 6 +/* guarded by DRM_VMW_PARAM_3D == 1 */ +#define DRM_VMW_CREATE_CONTEXT 7 +#define DRM_VMW_UNREF_CONTEXT 8 +#define DRM_VMW_CREATE_SURFACE 9 +#define DRM_VMW_UNREF_SURFACE 10 +#define DRM_VMW_REF_SURFACE 11 +#define DRM_VMW_EXECBUF 12 +#define DRM_VMW_FIFO_DEBUG 13 +#define DRM_VMW_FENCE_WAIT 14 +/* guarded by minor version >= 2 */ +#define DRM_VMW_UPDATE_LAYOUT 15 + + +/*************************************************************************/ +/** + * DRM_VMW_GET_PARAM - get device information. + * + * DRM_VMW_PARAM_FIFO_OFFSET: + * Offset to use to map the first page of the FIFO read-only. + * The fifo is mapped using the mmap() system call on the drm device. + * + * DRM_VMW_PARAM_OVERLAY_IOCTL: + * Does the driver support the overlay ioctl. + */ + +#define DRM_VMW_PARAM_NUM_STREAMS 0 +#define DRM_VMW_PARAM_NUM_FREE_STREAMS 1 +#define DRM_VMW_PARAM_3D 2 +#define DRM_VMW_PARAM_FIFO_OFFSET 3 +#define DRM_VMW_PARAM_HW_CAPS 4 +#define DRM_VMW_PARAM_FIFO_CAPS 5 + +/** + * struct drm_vmw_getparam_arg + * + * @value: Returned value. //Out + * @param: Parameter to query. //In. + * + * Argument to the DRM_VMW_GET_PARAM Ioctl. + */ + +struct drm_vmw_getparam_arg { + uint64_t value; + uint32_t param; + uint32_t pad64; +}; + +/*************************************************************************/ +/** + * DRM_VMW_EXTENSION - Query device extensions. + */ + +/** + * struct drm_vmw_extension_rep + * + * @exists: The queried extension exists. + * @driver_ioctl_offset: Ioctl number of the first ioctl in the extension. + * @driver_sarea_offset: Offset to any space in the DRI SAREA + * used by the extension. + * @major: Major version number of the extension. + * @minor: Minor version number of the extension. + * @pl: Patch level version number of the extension. + * + * Output argument to the DRM_VMW_EXTENSION Ioctl. + */ + +struct drm_vmw_extension_rep { + int32_t exists; + uint32_t driver_ioctl_offset; + uint32_t driver_sarea_offset; + uint32_t major; + uint32_t minor; + uint32_t pl; + uint32_t pad64; +}; + +/** + * union drm_vmw_extension_arg + * + * @extension - Ascii name of the extension to be queried. //In + * @rep - Reply as defined above. //Out + * + * Argument to the DRM_VMW_EXTENSION Ioctl. + */ + +union drm_vmw_extension_arg { + char extension[DRM_VMW_EXT_NAME_LEN]; + struct drm_vmw_extension_rep rep; +}; + +/*************************************************************************/ +/** + * DRM_VMW_CREATE_CONTEXT - Create a host context. + * + * Allocates a device unique context id, and queues a create context command + * for the host. Does not wait for host completion. + */ + +/** + * struct drm_vmw_context_arg + * + * @cid: Device unique context ID. + * + * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl. + * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl. + */ + +struct drm_vmw_context_arg { + int32_t cid; + uint32_t pad64; +}; + +/*************************************************************************/ +/** + * DRM_VMW_UNREF_CONTEXT - Create a host context. + * + * Frees a global context id, and queues a destroy host command for the host. + * Does not wait for host completion. The context ID can be used directly + * in the command stream and shows up as the same context ID on the host. + */ + +/*************************************************************************/ +/** + * DRM_VMW_CREATE_SURFACE - Create a host suface. + * + * Allocates a device unique surface id, and queues a create surface command + * for the host. Does not wait for host completion. The surface ID can be + * used directly in the command stream and shows up as the same surface + * ID on the host. + */ + +/** + * struct drm_wmv_surface_create_req + * + * @flags: Surface flags as understood by the host. + * @format: Surface format as understood by the host. + * @mip_levels: Number of mip levels for each face. + * An unused face should have 0 encoded. + * @size_addr: Address of a user-space array of sruct drm_vmw_size + * cast to an uint64_t for 32-64 bit compatibility. + * The size of the array should equal the total number of mipmap levels. + * @shareable: Boolean whether other clients (as identified by file descriptors) + * may reference this surface. + * @scanout: Boolean whether the surface is intended to be used as a + * scanout. + * + * Input data to the DRM_VMW_CREATE_SURFACE Ioctl. + * Output data from the DRM_VMW_REF_SURFACE Ioctl. + */ + +struct drm_vmw_surface_create_req { + uint32_t flags; + uint32_t format; + uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES]; + uint64_t size_addr; + int32_t shareable; + int32_t scanout; +}; + +/** + * struct drm_wmv_surface_arg + * + * @sid: Surface id of created surface or surface to destroy or reference. + * + * Output data from the DRM_VMW_CREATE_SURFACE Ioctl. + * Input argument to the DRM_VMW_UNREF_SURFACE Ioctl. + * Input argument to the DRM_VMW_REF_SURFACE Ioctl. + */ + +struct drm_vmw_surface_arg { + int32_t sid; + uint32_t pad64; +}; + +/** + * struct drm_vmw_size ioctl. + * + * @width - mip level width + * @height - mip level height + * @depth - mip level depth + * + * Description of a mip level. + * Input data to the DRM_WMW_CREATE_SURFACE Ioctl. + */ + +struct drm_vmw_size { + uint32_t width; + uint32_t height; + uint32_t depth; + uint32_t pad64; +}; + +/** + * union drm_vmw_surface_create_arg + * + * @rep: Output data as described above. + * @req: Input data as described above. + * + * Argument to the DRM_VMW_CREATE_SURFACE Ioctl. + */ + +union drm_vmw_surface_create_arg { + struct drm_vmw_surface_arg rep; + struct drm_vmw_surface_create_req req; +}; + +/*************************************************************************/ +/** + * DRM_VMW_REF_SURFACE - Reference a host surface. + * + * Puts a reference on a host surface with a give sid, as previously + * returned by the DRM_VMW_CREATE_SURFACE ioctl. + * A reference will make sure the surface isn't destroyed while we hold + * it and will allow the calling client to use the surface ID in the command + * stream. + * + * On successful return, the Ioctl returns the surface information given + * in the DRM_VMW_CREATE_SURFACE ioctl. + */ + +/** + * union drm_vmw_surface_reference_arg + * + * @rep: Output data as described above. + * @req: Input data as described above. + * + * Argument to the DRM_VMW_REF_SURFACE Ioctl. + */ + +union drm_vmw_surface_reference_arg { + struct drm_vmw_surface_create_req rep; + struct drm_vmw_surface_arg req; +}; + +/*************************************************************************/ +/** + * DRM_VMW_UNREF_SURFACE - Unreference a host surface. + * + * Clear a reference previously put on a host surface. + * When all references are gone, including the one implicitly placed + * on creation, + * a destroy surface command will be queued for the host. + * Does not wait for completion. + */ + +/*************************************************************************/ +/** + * DRM_VMW_EXECBUF + * + * Submit a command buffer for execution on the host, and return a + * fence sequence that when signaled, indicates that the command buffer has + * executed. + */ + +/** + * struct drm_vmw_execbuf_arg + * + * @commands: User-space address of a command buffer cast to an uint64_t. + * @command-size: Size in bytes of the command buffer. + * @throttle-us: Sleep until software is less than @throttle_us + * microseconds ahead of hardware. The driver may round this value + * to the nearest kernel tick. + * @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an + * uint64_t. + * @version: Allows expanding the execbuf ioctl parameters without breaking + * backwards compatibility, since user-space will always tell the kernel + * which version it uses. + * @flags: Execbuf flags. None currently. + * + * Argument to the DRM_VMW_EXECBUF Ioctl. + */ + +#define DRM_VMW_EXECBUF_VERSION 0 + +struct drm_vmw_execbuf_arg { + uint64_t commands; + uint32_t command_size; + uint32_t throttle_us; + uint64_t fence_rep; + uint32_t version; + uint32_t flags; +}; + +/** + * struct drm_vmw_fence_rep + * + * @fence_seq: Fence sequence associated with a command submission. + * @error: This member should've been set to -EFAULT on submission. + * The following actions should be take on completion: + * error == -EFAULT: Fence communication failed. The host is synchronized. + * Use the last fence id read from the FIFO fence register. + * error != 0 && error != -EFAULT: + * Fence submission failed. The host is synchronized. Use the fence_seq member. + * error == 0: All is OK, The host may not be synchronized. + * Use the fence_seq member. + * + * Input / Output data to the DRM_VMW_EXECBUF Ioctl. + */ + +struct drm_vmw_fence_rep { + uint64_t fence_seq; + int32_t error; + uint32_t pad64; +}; + +/*************************************************************************/ +/** + * DRM_VMW_ALLOC_DMABUF + * + * Allocate a DMA buffer that is visible also to the host. + * NOTE: The buffer is + * identified by a handle and an offset, which are private to the guest, but + * useable in the command stream. The guest kernel may translate these + * and patch up the command stream accordingly. In the future, the offset may + * be zero at all times, or it may disappear from the interface before it is + * fixed. + * + * The DMA buffer may stay user-space mapped in the guest at all times, + * and is thus suitable for sub-allocation. + * + * DMA buffers are mapped using the mmap() syscall on the drm device. + */ + +/** + * struct drm_vmw_alloc_dmabuf_req + * + * @size: Required minimum size of the buffer. + * + * Input data to the DRM_VMW_ALLOC_DMABUF Ioctl. + */ + +struct drm_vmw_alloc_dmabuf_req { + uint32_t size; + uint32_t pad64; +}; + +/** + * struct drm_vmw_dmabuf_rep + * + * @map_handle: Offset to use in the mmap() call used to map the buffer. + * @handle: Handle unique to this buffer. Used for unreferencing. + * @cur_gmr_id: GMR id to use in the command stream when this buffer is + * referenced. See not above. + * @cur_gmr_offset: Offset to use in the command stream when this buffer is + * referenced. See note above. + * + * Output data from the DRM_VMW_ALLOC_DMABUF Ioctl. + */ + +struct drm_vmw_dmabuf_rep { + uint64_t map_handle; + uint32_t handle; + uint32_t cur_gmr_id; + uint32_t cur_gmr_offset; + uint32_t pad64; +}; + +/** + * union drm_vmw_dmabuf_arg + * + * @req: Input data as described above. + * @rep: Output data as described above. + * + * Argument to the DRM_VMW_ALLOC_DMABUF Ioctl. + */ + +union drm_vmw_alloc_dmabuf_arg { + struct drm_vmw_alloc_dmabuf_req req; + struct drm_vmw_dmabuf_rep rep; +}; + +/*************************************************************************/ +/** + * DRM_VMW_UNREF_DMABUF - Free a DMA buffer. + * + */ + +/** + * struct drm_vmw_unref_dmabuf_arg + * + * @handle: Handle indicating what buffer to free. Obtained from the + * DRM_VMW_ALLOC_DMABUF Ioctl. + * + * Argument to the DRM_VMW_UNREF_DMABUF Ioctl. + */ + +struct drm_vmw_unref_dmabuf_arg { + uint32_t handle; + uint32_t pad64; +}; + +/*************************************************************************/ +/** + * DRM_VMW_FIFO_DEBUG - Get last FIFO submission. + * + * This IOCTL copies the last FIFO submission directly out of the FIFO buffer. + */ + +/** + * struct drm_vmw_fifo_debug_arg + * + * @debug_buffer: User space address of a debug_buffer cast to an uint64_t //In + * @debug_buffer_size: Size in bytes of debug buffer //In + * @used_size: Number of bytes copied to the buffer // Out + * @did_not_fit: Boolean indicating that the fifo contents did not fit. //Out + * + * Argument to the DRM_VMW_FIFO_DEBUG Ioctl. + */ + +struct drm_vmw_fifo_debug_arg { + uint64_t debug_buffer; + uint32_t debug_buffer_size; + uint32_t used_size; + int32_t did_not_fit; + uint32_t pad64; +}; + +struct drm_vmw_fence_wait_arg { + uint64_t sequence; + uint64_t kernel_cookie; + int32_t cookie_valid; + int32_t pad64; +}; + +/*************************************************************************/ +/** + * DRM_VMW_CONTROL_STREAM - Control overlays, aka streams. + * + * This IOCTL controls the overlay units of the svga device. + * The SVGA overlay units does not work like regular hardware units in + * that they do not automaticaly read back the contents of the given dma + * buffer. But instead only read back for each call to this ioctl, and + * at any point between this call being made and a following call that + * either changes the buffer or disables the stream. + */ + +/** + * struct drm_vmw_rect + * + * Defines a rectangle. Used in the overlay ioctl to define + * source and destination rectangle. + */ + +struct drm_vmw_rect { + int32_t x; + int32_t y; + uint32_t w; + uint32_t h; +}; + +/** + * struct drm_vmw_control_stream_arg + * + * @stream_id: Stearm to control + * @enabled: If false all following arguments are ignored. + * @handle: Handle to buffer for getting data from. + * @format: Format of the overlay as understood by the host. + * @width: Width of the overlay. + * @height: Height of the overlay. + * @size: Size of the overlay in bytes. + * @pitch: Array of pitches, the two last are only used for YUV12 formats. + * @offset: Offset from start of dma buffer to overlay. + * @src: Source rect, must be within the defined area above. + * @dst: Destination rect, x and y may be negative. + * + * Argument to the DRM_VMW_CONTROL_STREAM Ioctl. + */ + +struct drm_vmw_control_stream_arg { + uint32_t stream_id; + uint32_t enabled; + + uint32_t flags; + uint32_t color_key; + + uint32_t handle; + uint32_t offset; + int32_t format; + uint32_t size; + uint32_t width; + uint32_t height; + uint32_t pitch[3]; + + uint32_t pad64; + struct drm_vmw_rect src; + struct drm_vmw_rect dst; +}; + +/*************************************************************************/ +/** + * DRM_VMW_CURSOR_BYPASS - Give extra information about cursor bypass. + * + */ + +#define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0) +#define DRM_VMW_CURSOR_BYPASS_FLAGS (1) + +/** + * struct drm_vmw_cursor_bypass_arg + * + * @flags: Flags. + * @crtc_id: Crtc id, only used if DMR_CURSOR_BYPASS_ALL isn't passed. + * @xpos: X position of cursor. + * @ypos: Y position of cursor. + * @xhot: X hotspot. + * @yhot: Y hotspot. + * + * Argument to the DRM_VMW_CURSOR_BYPASS Ioctl. + */ + +struct drm_vmw_cursor_bypass_arg { + uint32_t flags; + uint32_t crtc_id; + int32_t xpos; + int32_t ypos; + int32_t xhot; + int32_t yhot; +}; + +/*************************************************************************/ +/** + * DRM_VMW_CLAIM_STREAM - Claim a single stream. + */ + +/** + * struct drm_vmw_context_arg + * + * @stream_id: Device unique context ID. + * + * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl. + * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl. + */ + +struct drm_vmw_stream_arg { + uint32_t stream_id; + uint32_t pad64; +}; + +/*************************************************************************/ +/** + * DRM_VMW_UNREF_STREAM - Unclaim a stream. + * + * Return a single stream that was claimed by this process. Also makes + * sure that the stream has been stopped. + */ + +/*************************************************************************/ +/** + * DRM_VMW_UPDATE_LAYOUT - Update layout + * + * Updates the prefered modes and connection status for connectors. The + * command conisits of one drm_vmw_update_layout_arg pointing out a array + * of num_outputs drm_vmw_rect's. + */ + +/** + * struct drm_vmw_update_layout_arg + * + * @num_outputs: number of active + * @rects: pointer to array of drm_vmw_rect + * + * Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl. + */ + +struct drm_vmw_update_layout_arg { + uint32_t num_outputs; + uint32_t pad64; + uint64_t rects; +}; + +#endif diff --git a/intel/.gitignore b/intel/.gitignore new file mode 100644 index 0000000..528b408 --- /dev/null +++ b/intel/.gitignore @@ -0,0 +1 @@ +test_decode diff --git a/intel/Makefile.am b/intel/Makefile.am new file mode 100644 index 0000000..dc01a96 --- /dev/null +++ b/intel/Makefile.am @@ -0,0 +1,82 @@ +# Copyright © 2008 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# Authors: +# Eric Anholt + +AM_CFLAGS = \ + $(WARN_CFLAGS) \ + -I$(top_srcdir) \ + -I$(top_srcdir)/intel \ + $(PTHREADSTUBS_CFLAGS) \ + $(PCIACCESS_CFLAGS) \ + $(VALGRIND_CFLAGS) \ + -I$(top_srcdir)/include/drm + +libdrm_intel_la_LTLIBRARIES = libdrm_intel.la +libdrm_intel_ladir = $(libdir) +libdrm_intel_la_LDFLAGS = -version-number 1:0:0 -no-undefined +libdrm_intel_la_LIBADD = ../libdrm.la \ + @PTHREADSTUBS_LIBS@ \ + @PCIACCESS_LIBS@ \ + @CLOCK_LIB@ + +libdrm_intel_la_SOURCES = \ + intel_bufmgr.c \ + intel_bufmgr_priv.h \ + intel_bufmgr_fake.c \ + intel_bufmgr_gem.c \ + intel_decode.c \ + intel_chipset.h \ + mm.c \ + mm.h + +intel_bufmgr_gem_o_CFLAGS = $(AM_CFLAGS) -c99 + +libdrm_intelincludedir = ${includedir}/libdrm +libdrm_intelinclude_HEADERS = intel_bufmgr.h \ + intel_aub.h \ + intel_debug.h + +# This may be interesting even outside of "make check", due to the -dump option. +noinst_PROGRAMS = test_decode + +BATCHES = \ + tests/gen4-3d.batch \ + tests/gm45-3d.batch \ + tests/gen5-3d.batch \ + tests/gen6-3d.batch \ + tests/gen7-2d-copy.batch \ + tests/gen7-3d.batch + +TESTS = \ + $(BATCHES:.batch=.batch.sh) + +EXTRA_DIST = \ + $(BATCHES) \ + $(BATCHES:.batch=.batch.sh) \ + $(BATCHES:.batch=.batch-ref.txt) \ + $(BATCHES:.batch=.batch-ref.txt) \ + tests/test-batch.sh + +test_decode_LDADD = libdrm_intel.la + +pkgconfig_DATA = libdrm_intel.pc diff --git a/intel/intel_aub.h b/intel/intel_aub.h new file mode 100644 index 0000000..a36fd53 --- /dev/null +++ b/intel/intel_aub.h @@ -0,0 +1,123 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +/** @file intel_aub.h + * + * The AUB file is a file format used by Intel's internal simulation + * and other validation tools. It can be used at various levels by a + * driver to input state to the simulated hardware or a replaying + * debugger. + * + * We choose to dump AUB files using the trace block format for ease + * of implementation -- dump out the blocks of memory as plain blobs + * and insert ring commands to execute the batchbuffer blob. + */ + +#ifndef _INTEL_AUB_H +#define _INTEL_AUB_H + +#define AUB_MI_NOOP (0) +#define AUB_MI_BATCH_BUFFER_START (0x31 << 23) +#define AUB_PIPE_CONTROL (0x7a000002) + +/* DW0: instruction type. */ + +#define CMD_AUB (7 << 29) + +#define CMD_AUB_HEADER (CMD_AUB | (1 << 23) | (0x05 << 16)) +/* DW1 */ +# define AUB_HEADER_MAJOR_SHIFT 24 +# define AUB_HEADER_MINOR_SHIFT 16 + +#define CMD_AUB_TRACE_HEADER_BLOCK (CMD_AUB | (1 << 23) | (0x41 << 16)) +#define CMD_AUB_DUMP_BMP (CMD_AUB | (1 << 23) | (0x9e << 16)) + +/* DW1 */ +#define AUB_TRACE_OPERATION_MASK 0x000000ff +#define AUB_TRACE_OP_COMMENT 0x00000000 +#define AUB_TRACE_OP_DATA_WRITE 0x00000001 +#define AUB_TRACE_OP_COMMAND_WRITE 0x00000002 +#define AUB_TRACE_OP_MMIO_WRITE 0x00000003 +// operation = TRACE_DATA_WRITE, Type +#define AUB_TRACE_TYPE_MASK 0x0000ff00 +#define AUB_TRACE_TYPE_NOTYPE (0 << 8) +#define AUB_TRACE_TYPE_BATCH (1 << 8) +#define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8) +#define AUB_TRACE_TYPE_2D_MAP (6 << 8) +#define AUB_TRACE_TYPE_CUBE_MAP (7 << 8) +#define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8) +#define AUB_TRACE_TYPE_1D_MAP (10 << 8) +#define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8) +#define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8) +#define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8) +#define AUB_TRACE_TYPE_GENERAL (14 << 8) +#define AUB_TRACE_TYPE_SURFACE (15 << 8) + + +// operation = TRACE_COMMAND_WRITE, Type = +#define AUB_TRACE_TYPE_RING_HWB (1 << 8) +#define AUB_TRACE_TYPE_RING_PRB0 (2 << 8) +#define AUB_TRACE_TYPE_RING_PRB1 (3 << 8) +#define AUB_TRACE_TYPE_RING_PRB2 (4 << 8) + +// Address space +#define AUB_TRACE_ADDRESS_SPACE_MASK 0x00ff0000 +#define AUB_TRACE_MEMTYPE_GTT (0 << 16) +#define AUB_TRACE_MEMTYPE_LOCAL (1 << 16) +#define AUB_TRACE_MEMTYPE_NONLOCAL (2 << 16) +#define AUB_TRACE_MEMTYPE_PCI (3 << 16) +#define AUB_TRACE_MEMTYPE_GTT_ENTRY (4 << 16) + +/* DW2 */ +// operation = TRACE_DATA_WRITE, Type = TRACE_DATA_WRITE_GENERAL_STATE +#define AUB_TRACE_GENERAL_STATE_MASK 0x000000ff + +#define AUB_TRACE_VS_STATE 0x00000001 +#define AUB_TRACE_GS_STATE 0x00000002 +#define AUB_TRACE_CL_STATE 0x00000003 +#define AUB_TRACE_SF_STATE 0x00000004 +#define AUB_TRACE_WM_STATE 0x00000005 +#define AUB_TRACE_CC_STATE 0x00000006 +#define AUB_TRACE_CL_VP 0x00000007 +#define AUB_TRACE_SF_VP 0x00000008 +#define AUB_TRACE_CC_VP 0x00000009 +#define AUB_TRACE_SAMPLER_STATE 0x0000000a +#define AUB_TRACE_KERNEL 0x0000000b +#define AUB_TRACE_SCRATCH 0x0000000c +#define AUB_TRACE_SDC 0x0000000d +#define AUB_TRACE_BLEND_STATE 0x00000016 +#define AUB_TRACE_DEPTH_STENCIL_STATE 0x00000017 + +// operation = TRACE_DATA_WRITE, Type = TRACE_DATA_WRITE_SURFACE_STATE +#define AUB_TRACE_SURFACE_STATE_MASK 0x00000ff00 +#define AUB_TRACE_BINDING_TABLE 0x000000100 +#define AUB_TRACE_SURFACE_STATE 0x000000200 + +/* DW3: address */ +/* DW4: len */ + +#endif /* _INTEL_AUB_H */ diff --git a/intel/intel_bufmgr.c b/intel/intel_bufmgr.c new file mode 100644 index 0000000..905556f --- /dev/null +++ b/intel/intel_bufmgr.c @@ -0,0 +1,321 @@ +/* + * Copyright © 2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include "intel_bufmgr.h" +#include "intel_bufmgr_priv.h" +#include "xf86drm.h" + +/** @file intel_bufmgr.c + * + * Convenience functions for buffer management methods. + */ + +drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, + unsigned long size, unsigned int alignment) +{ + return bufmgr->bo_alloc(bufmgr, name, size, alignment); +} + +drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, + const char *name, + unsigned long size, + unsigned int alignment) +{ + return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment); +} + +drm_intel_bo * +drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, + int x, int y, int cpp, uint32_t *tiling_mode, + unsigned long *pitch, unsigned long flags) +{ + return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp, + tiling_mode, pitch, flags); +} + +void drm_intel_bo_reference(drm_intel_bo *bo) +{ + bo->bufmgr->bo_reference(bo); +} + +void drm_intel_bo_unreference(drm_intel_bo *bo) +{ + if (bo == NULL) + return; + + bo->bufmgr->bo_unreference(bo); +} + +int drm_intel_bo_map(drm_intel_bo *buf, int write_enable) +{ + return buf->bufmgr->bo_map(buf, write_enable); +} + +int drm_intel_bo_unmap(drm_intel_bo *buf) +{ + return buf->bufmgr->bo_unmap(buf); +} + +int +drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset, + unsigned long size, const void *data) +{ + return bo->bufmgr->bo_subdata(bo, offset, size, data); +} + +int +drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset, + unsigned long size, void *data) +{ + int ret; + if (bo->bufmgr->bo_get_subdata) + return bo->bufmgr->bo_get_subdata(bo, offset, size, data); + + if (size == 0 || data == NULL) + return 0; + + ret = drm_intel_bo_map(bo, 0); + if (ret) + return ret; + memcpy(data, (unsigned char *)bo->virtual + offset, size); + drm_intel_bo_unmap(bo); + return 0; +} + +void drm_intel_bo_wait_rendering(drm_intel_bo *bo) +{ + bo->bufmgr->bo_wait_rendering(bo); +} + +void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr) +{ + bufmgr->destroy(bufmgr); +} + +int +drm_intel_bo_exec(drm_intel_bo *bo, int used, + drm_clip_rect_t * cliprects, int num_cliprects, int DR4) +{ + return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4); +} + +int +drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used, + drm_clip_rect_t *cliprects, int num_cliprects, int DR4, + unsigned int rings) +{ + if (bo->bufmgr->bo_mrb_exec) + return bo->bufmgr->bo_mrb_exec(bo, used, + cliprects, num_cliprects, DR4, + rings); + + switch (rings) { + case I915_EXEC_DEFAULT: + case I915_EXEC_RENDER: + return bo->bufmgr->bo_exec(bo, used, + cliprects, num_cliprects, DR4); + default: + return -ENODEV; + } +} + +void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug) +{ + bufmgr->debug = enable_debug; +} + +int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count) +{ + return bo_array[0]->bufmgr->check_aperture_space(bo_array, count); +} + +int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name) +{ + if (bo->bufmgr->bo_flink) + return bo->bufmgr->bo_flink(bo, name); + + return -ENODEV; +} + +int +drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, + drm_intel_bo *target_bo, uint32_t target_offset, + uint32_t read_domains, uint32_t write_domain) +{ + return bo->bufmgr->bo_emit_reloc(bo, offset, + target_bo, target_offset, + read_domains, write_domain); +} + +/* For fence registers, not GL fences */ +int +drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset, + drm_intel_bo *target_bo, uint32_t target_offset, + uint32_t read_domains, uint32_t write_domain) +{ + return bo->bufmgr->bo_emit_reloc_fence(bo, offset, + target_bo, target_offset, + read_domains, write_domain); +} + + +int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment) +{ + if (bo->bufmgr->bo_pin) + return bo->bufmgr->bo_pin(bo, alignment); + + return -ENODEV; +} + +int drm_intel_bo_unpin(drm_intel_bo *bo) +{ + if (bo->bufmgr->bo_unpin) + return bo->bufmgr->bo_unpin(bo); + + return -ENODEV; +} + +int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, + uint32_t stride) +{ + if (bo->bufmgr->bo_set_tiling) + return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride); + + *tiling_mode = I915_TILING_NONE; + return 0; +} + +int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, + uint32_t * swizzle_mode) +{ + if (bo->bufmgr->bo_get_tiling) + return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode); + + *tiling_mode = I915_TILING_NONE; + *swizzle_mode = I915_BIT_6_SWIZZLE_NONE; + return 0; +} + +int drm_intel_bo_disable_reuse(drm_intel_bo *bo) +{ + if (bo->bufmgr->bo_disable_reuse) + return bo->bufmgr->bo_disable_reuse(bo); + return 0; +} + +int drm_intel_bo_is_reusable(drm_intel_bo *bo) +{ + if (bo->bufmgr->bo_is_reusable) + return bo->bufmgr->bo_is_reusable(bo); + return 0; +} + +int drm_intel_bo_busy(drm_intel_bo *bo) +{ + if (bo->bufmgr->bo_busy) + return bo->bufmgr->bo_busy(bo); + return 0; +} + +int drm_intel_bo_madvise(drm_intel_bo *bo, int madv) +{ + if (bo->bufmgr->bo_madvise) + return bo->bufmgr->bo_madvise(bo, madv); + return -1; +} + +int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo) +{ + return bo->bufmgr->bo_references(bo, target_bo); +} + +int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id) +{ + if (bufmgr->get_pipe_from_crtc_id) + return bufmgr->get_pipe_from_crtc_id(bufmgr, crtc_id); + return -1; +} + +static size_t +drm_intel_probe_agp_aperture_size(int fd) +{ + struct pci_device *pci_dev; + size_t size = 0; + int ret; + + ret = pci_system_init(); + if (ret) + goto err; + + /* XXX handle multiple adaptors? */ + pci_dev = pci_device_find_by_slot(0, 0, 2, 0); + if (pci_dev == NULL) + goto err; + + ret = pci_device_probe(pci_dev); + if (ret) + goto err; + + size = pci_dev->regions[2].size; +err: + pci_system_cleanup (); + return size; +} + +int drm_intel_get_aperture_sizes(int fd, + size_t *mappable, + size_t *total) +{ + + struct drm_i915_gem_get_aperture aperture; + int ret; + + ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); + if (ret) + return ret; + + *mappable = 0; + /* XXX add a query for the kernel value? */ + if (*mappable == 0) + *mappable = drm_intel_probe_agp_aperture_size(fd); + if (*mappable == 0) + *mappable = 64 * 1024 * 1024; /* minimum possible value */ + *total = aperture.aper_size; + return 0; +} diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h new file mode 100644 index 0000000..c197abc --- /dev/null +++ b/intel/intel_bufmgr.h @@ -0,0 +1,275 @@ +/* + * Copyright © 2008-2012 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +/** + * @file intel_bufmgr.h + * + * Public definitions of Intel-specific bufmgr functions. + */ + +#ifndef INTEL_BUFMGR_H +#define INTEL_BUFMGR_H + +#include +#include +#include + +struct drm_clip_rect; + +typedef struct _drm_intel_bufmgr drm_intel_bufmgr; +typedef struct _drm_intel_bo drm_intel_bo; + +struct _drm_intel_bo { + /** + * Size in bytes of the buffer object. + * + * The size may be larger than the size originally requested for the + * allocation, such as being aligned to page size. + */ + unsigned long size; + + /** + * Alignment requirement for object + * + * Used for GTT mapping & pinning the object. + */ + unsigned long align; + + /** + * Last seen card virtual address (offset from the beginning of the + * aperture) for the object. This should be used to fill relocation + * entries when calling drm_intel_bo_emit_reloc() + */ + unsigned long offset; + + /** + * Virtual address for accessing the buffer data. Only valid while + * mapped. + */ +#ifdef __cplusplus + void *virt; +#else + void *virtual; +#endif + + /** Buffer manager context associated with this buffer object */ + drm_intel_bufmgr *bufmgr; + + /** + * MM-specific handle for accessing object + */ + int handle; +}; + +enum aub_dump_bmp_format { + AUB_DUMP_BMP_FORMAT_8BIT = 1, + AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4, + AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6, + AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7, +}; + +typedef struct _drm_intel_aub_annotation { + uint32_t type; + uint32_t subtype; + uint32_t ending_offset; +} drm_intel_aub_annotation; + +#define BO_ALLOC_FOR_RENDER (1<<0) + +drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, + unsigned long size, unsigned int alignment); +drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, + const char *name, + unsigned long size, + unsigned int alignment); +drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, + const char *name, + int x, int y, int cpp, + uint32_t *tiling_mode, + unsigned long *pitch, + unsigned long flags); +void drm_intel_bo_reference(drm_intel_bo *bo); +void drm_intel_bo_unreference(drm_intel_bo *bo); +int drm_intel_bo_map(drm_intel_bo *bo, int write_enable); +int drm_intel_bo_unmap(drm_intel_bo *bo); + +int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset, + unsigned long size, const void *data); +int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset, + unsigned long size, void *data); +void drm_intel_bo_wait_rendering(drm_intel_bo *bo); + +void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug); +void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr); +int drm_intel_bo_exec(drm_intel_bo *bo, int used, + struct drm_clip_rect *cliprects, int num_cliprects, int DR4); +int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used, + struct drm_clip_rect *cliprects, int num_cliprects, int DR4, + unsigned int flags); +int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count); + +int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, + drm_intel_bo *target_bo, uint32_t target_offset, + uint32_t read_domains, uint32_t write_domain); +int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset, + drm_intel_bo *target_bo, + uint32_t target_offset, + uint32_t read_domains, uint32_t write_domain); +int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment); +int drm_intel_bo_unpin(drm_intel_bo *bo); +int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, + uint32_t stride); +int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, + uint32_t * swizzle_mode); +int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name); +int drm_intel_bo_busy(drm_intel_bo *bo); +int drm_intel_bo_madvise(drm_intel_bo *bo, int madv); + +int drm_intel_bo_disable_reuse(drm_intel_bo *bo); +int drm_intel_bo_is_reusable(drm_intel_bo *bo); +int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo); + +/* drm_intel_bufmgr_gem.c */ +drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size); +drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, + const char *name, + unsigned int handle); +void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr); +void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr); +void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, + int limit); +int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo); +int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo); +int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo); + +int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo); +void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start); +void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable); + +void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable); +void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo, + int x1, int y1, int width, int height, + enum aub_dump_bmp_format format, + int pitch, int offset); +void +drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo, + drm_intel_aub_annotation *annotations, + unsigned count); + +int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id); + +int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total); +int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr); + +/* drm_intel_bufmgr_fake.c */ +drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd, + unsigned long low_offset, + void *low_virtual, + unsigned long size, + volatile unsigned int + *last_dispatch); +void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr, + volatile unsigned int + *last_dispatch); +void drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr, + int (*exec) (drm_intel_bo *bo, + unsigned int used, + void *priv), + void *priv); +void drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr, + unsigned int (*emit) (void *priv), + void (*wait) (unsigned int fence, + void *priv), + void *priv); +drm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr, + const char *name, + unsigned long offset, + unsigned long size, void *virt); +void drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo, + void (*invalidate_cb) (drm_intel_bo + * bo, + void *ptr), + void *ptr); + +void drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr); +void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr); + +struct drm_intel_decode *drm_intel_decode_context_alloc(uint32_t devid); +void drm_intel_decode_context_free(struct drm_intel_decode *ctx); +void drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx, + void *data, uint32_t hw_offset, + int count); +void drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx, + int dump_past_end); +void drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx, + uint32_t head, uint32_t tail); +void drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out); +void drm_intel_decode(struct drm_intel_decode *ctx); + + +/** @{ Compatibility defines to keep old code building despite the symbol rename + * from dri_* to drm_intel_* + */ +#define dri_bo drm_intel_bo +#define dri_bufmgr drm_intel_bufmgr +#define dri_bo_alloc drm_intel_bo_alloc +#define dri_bo_reference drm_intel_bo_reference +#define dri_bo_unreference drm_intel_bo_unreference +#define dri_bo_map drm_intel_bo_map +#define dri_bo_unmap drm_intel_bo_unmap +#define dri_bo_subdata drm_intel_bo_subdata +#define dri_bo_get_subdata drm_intel_bo_get_subdata +#define dri_bo_wait_rendering drm_intel_bo_wait_rendering +#define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug +#define dri_bufmgr_destroy drm_intel_bufmgr_destroy +#define dri_bo_exec drm_intel_bo_exec +#define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space +#define dri_bo_emit_reloc(reloc_bo, read, write, target_offset, \ + reloc_offset, target_bo) \ + drm_intel_bo_emit_reloc(reloc_bo, reloc_offset, \ + target_bo, target_offset, \ + read, write); +#define dri_bo_pin drm_intel_bo_pin +#define dri_bo_unpin drm_intel_bo_unpin +#define dri_bo_get_tiling drm_intel_bo_get_tiling +#define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0) +#define dri_bo_flink drm_intel_bo_flink +#define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init +#define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name +#define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse +#define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init +#define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch +#define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback +#define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback +#define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static +#define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store +#define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take +#define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all + +/** @{ */ + +#endif /* INTEL_BUFMGR_H */ diff --git a/intel/intel_bufmgr_fake.c b/intel/intel_bufmgr_fake.c new file mode 100644 index 0000000..d9b5cfd --- /dev/null +++ b/intel/intel_bufmgr_fake.c @@ -0,0 +1,1633 @@ +/************************************************************************** + * + * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +/* Originally a fake version of the buffer manager so that we can + * prototype the changes in a driver fairly quickly, has been fleshed + * out to a fully functional interim solution. + * + * Basically wraps the old style memory management in the new + * programming interface, but is more expressive and avoids many of + * the bugs in the old texture manager. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include +#include +#include +#include "intel_bufmgr.h" +#include "intel_bufmgr_priv.h" +#include "drm.h" +#include "i915_drm.h" +#include "mm.h" +#include "libdrm_lists.h" + +/* Support gcc's __FUNCTION__ for people using other compilers */ +#if !defined(__GNUC__) && !defined(__FUNCTION__) +# define __FUNCTION__ __func__ /* C99 */ +#endif + +#define DBG(...) do { \ + if (bufmgr_fake->bufmgr.debug) \ + drmMsg(__VA_ARGS__); \ +} while (0) + +/* Internal flags: + */ +#define BM_NO_BACKING_STORE 0x00000001 +#define BM_NO_FENCE_SUBDATA 0x00000002 +#define BM_PINNED 0x00000004 + +/* Wrapper around mm.c's mem_block, which understands that you must + * wait for fences to expire before memory can be freed. This is + * specific to our use of memcpy for uploads - an upload that was + * processed through the command queue wouldn't need to care about + * fences. + */ +#define MAX_RELOCS 4096 + +struct fake_buffer_reloc { + /** Buffer object that the relocation points at. */ + drm_intel_bo *target_buf; + /** Offset of the relocation entry within reloc_buf. */ + uint32_t offset; + /** + * Cached value of the offset when we last performed this relocation. + */ + uint32_t last_target_offset; + /** Value added to target_buf's offset to get the relocation entry. */ + uint32_t delta; + /** Cache domains the target buffer is read into. */ + uint32_t read_domains; + /** Cache domain the target buffer will have dirty cachelines in. */ + uint32_t write_domain; +}; + +struct block { + struct block *next, *prev; + struct mem_block *mem; /* BM_MEM_AGP */ + + /** + * Marks that the block is currently in the aperture and has yet to be + * fenced. + */ + unsigned on_hardware:1; + /** + * Marks that the block is currently fenced (being used by rendering) + * and can't be freed until @fence is passed. + */ + unsigned fenced:1; + + /** Fence cookie for the block. */ + unsigned fence; /* Split to read_fence, write_fence */ + + drm_intel_bo *bo; + void *virtual; +}; + +typedef struct _bufmgr_fake { + drm_intel_bufmgr bufmgr; + + pthread_mutex_t lock; + + unsigned long low_offset; + unsigned long size; + void *virtual; + + struct mem_block *heap; + + unsigned buf_nr; /* for generating ids */ + + /** + * List of blocks which are currently in the GART but haven't been + * fenced yet. + */ + struct block on_hardware; + /** + * List of blocks which are in the GART and have an active fence on + * them. + */ + struct block fenced; + /** + * List of blocks which have an expired fence and are ready to be + * evicted. + */ + struct block lru; + + unsigned int last_fence; + + unsigned fail:1; + unsigned need_fence:1; + int thrashing; + + /** + * Driver callback to emit a fence, returning the cookie. + * + * This allows the driver to hook in a replacement for the DRM usage in + * bufmgr_fake. + * + * Currently, this also requires that a write flush be emitted before + * emitting the fence, but this should change. + */ + unsigned int (*fence_emit) (void *private); + /** Driver callback to wait for a fence cookie to have passed. */ + void (*fence_wait) (unsigned int fence, void *private); + void *fence_priv; + + /** + * Driver callback to execute a buffer. + * + * This allows the driver to hook in a replacement for the DRM usage in + * bufmgr_fake. + */ + int (*exec) (drm_intel_bo *bo, unsigned int used, void *priv); + void *exec_priv; + + /** Driver-supplied argument to driver callbacks */ + void *driver_priv; + /** + * Pointer to kernel-updated sarea data for the last completed user irq + */ + volatile int *last_dispatch; + + int fd; + + int debug; + + int performed_rendering; +} drm_intel_bufmgr_fake; + +typedef struct _drm_intel_bo_fake { + drm_intel_bo bo; + + unsigned id; /* debug only */ + const char *name; + + unsigned dirty:1; + /** + * has the card written to this buffer - we make need to copy it back + */ + unsigned card_dirty:1; + unsigned int refcount; + /* Flags may consist of any of the DRM_BO flags, plus + * DRM_BO_NO_BACKING_STORE and BM_NO_FENCE_SUBDATA, which are the + * first two driver private flags. + */ + uint64_t flags; + /** Cache domains the target buffer is read into. */ + uint32_t read_domains; + /** Cache domain the target buffer will have dirty cachelines in. */ + uint32_t write_domain; + + unsigned int alignment; + int is_static, validated; + unsigned int map_count; + + /** relocation list */ + struct fake_buffer_reloc *relocs; + int nr_relocs; + /** + * Total size of the target_bos of this buffer. + * + * Used for estimation in check_aperture. + */ + unsigned int child_size; + + struct block *block; + void *backing_store; + void (*invalidate_cb) (drm_intel_bo *bo, void *ptr); + void *invalidate_ptr; +} drm_intel_bo_fake; + +static int clear_fenced(drm_intel_bufmgr_fake *bufmgr_fake, + unsigned int fence_cookie); + +#define MAXFENCE 0x7fffffff + +static int +FENCE_LTE(unsigned a, unsigned b) +{ + if (a == b) + return 1; + + if (a < b && b - a < (1 << 24)) + return 1; + + if (a > b && MAXFENCE - a + b < (1 << 24)) + return 1; + + return 0; +} + +void +drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr, + unsigned int (*emit) (void *priv), + void (*wait) (unsigned int fence, + void *priv), + void *priv) +{ + drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr; + + bufmgr_fake->fence_emit = emit; + bufmgr_fake->fence_wait = wait; + bufmgr_fake->fence_priv = priv; +} + +static unsigned int +_fence_emit_internal(drm_intel_bufmgr_fake *bufmgr_fake) +{ + struct drm_i915_irq_emit ie; + int ret, seq = 1; + + if (bufmgr_fake->fence_emit != NULL) { + seq = bufmgr_fake->fence_emit(bufmgr_fake->fence_priv); + return seq; + } + + ie.irq_seq = &seq; + ret = drmCommandWriteRead(bufmgr_fake->fd, DRM_I915_IRQ_EMIT, + &ie, sizeof(ie)); + if (ret) { + drmMsg("%s: drm_i915_irq_emit: %d\n", __FUNCTION__, ret); + abort(); + } + + DBG("emit 0x%08x\n", seq); + return seq; +} + +static void +_fence_wait_internal(drm_intel_bufmgr_fake *bufmgr_fake, int seq) +{ + struct drm_i915_irq_wait iw; + int hw_seq, busy_count = 0; + int ret; + int kernel_lied; + + if (bufmgr_fake->fence_wait != NULL) { + bufmgr_fake->fence_wait(seq, bufmgr_fake->fence_priv); + clear_fenced(bufmgr_fake, seq); + return; + } + + iw.irq_seq = seq; + + DBG("wait 0x%08x\n", iw.irq_seq); + + /* The kernel IRQ_WAIT implementation is all sorts of broken. + * 1) It returns 1 to 0x7fffffff instead of using the full 32-bit + * unsigned range. + * 2) It returns 0 if hw_seq >= seq, not seq - hw_seq < 0 on the 32-bit + * signed range. + * 3) It waits if seq < hw_seq, not seq - hw_seq > 0 on the 32-bit + * signed range. + * 4) It returns -EBUSY in 3 seconds even if the hardware is still + * successfully chewing through buffers. + * + * Assume that in userland we treat sequence numbers as ints, which + * makes some of the comparisons convenient, since the sequence + * numbers are all postive signed integers. + * + * From this we get several cases we need to handle. Here's a timeline. + * 0x2 0x7 0x7ffffff8 0x7ffffffd + * | | | | + * ------------------------------------------------------------ + * + * A) Normal wait for hw to catch up + * hw_seq seq + * | | + * ------------------------------------------------------------ + * seq - hw_seq = 5. If we call IRQ_WAIT, it will wait for hw to + * catch up. + * + * B) Normal wait for a sequence number that's already passed. + * seq hw_seq + * | | + * ------------------------------------------------------------ + * seq - hw_seq = -5. If we call IRQ_WAIT, it returns 0 quickly. + * + * C) Hardware has already wrapped around ahead of us + * hw_seq seq + * | | + * ------------------------------------------------------------ + * seq - hw_seq = 0x80000000 - 5. If we called IRQ_WAIT, it would wait + * for hw_seq >= seq, which may never occur. Thus, we want to catch + * this in userland and return 0. + * + * D) We've wrapped around ahead of the hardware. + * seq hw_seq + * | | + * ------------------------------------------------------------ + * seq - hw_seq = -(0x80000000 - 5). If we called IRQ_WAIT, it would + * return 0 quickly because hw_seq >= seq, even though the hardware + * isn't caught up. Thus, we need to catch this early return in + * userland and bother the kernel until the hardware really does + * catch up. + * + * E) Hardware might wrap after we test in userland. + * hw_seq seq + * | | + * ------------------------------------------------------------ + * seq - hw_seq = 5. If we call IRQ_WAIT, it will likely see seq >= + * hw_seq and wait. However, suppose hw_seq wraps before we make it + * into the kernel. The kernel sees hw_seq >= seq and waits for 3 + * seconds then returns -EBUSY. This is case C). We should catch + * this and then return successfully. + * + * F) Hardware might take a long time on a buffer. + * hw_seq seq + * | | + * ------------------------------------------------------------------- + * seq - hw_seq = 5. If we call IRQ_WAIT, if sequence 2 through 5 + * take too long, it will return -EBUSY. Batchbuffers in the + * gltestperf demo were seen to take up to 7 seconds. We should + * catch early -EBUSY return and keep trying. + */ + + do { + /* Keep a copy of last_dispatch so that if the wait -EBUSYs + * because the hardware didn't catch up in 3 seconds, we can + * see if it at least made progress and retry. + */ + hw_seq = *bufmgr_fake->last_dispatch; + + /* Catch case C */ + if (seq - hw_seq > 0x40000000) + return; + + ret = drmCommandWrite(bufmgr_fake->fd, DRM_I915_IRQ_WAIT, + &iw, sizeof(iw)); + /* Catch case D */ + kernel_lied = (ret == 0) && (seq - *bufmgr_fake->last_dispatch < + -0x40000000); + + /* Catch case E */ + if (ret == -EBUSY + && (seq - *bufmgr_fake->last_dispatch > 0x40000000)) + ret = 0; + + /* Catch case F: Allow up to 15 seconds chewing on one buffer. */ + if ((ret == -EBUSY) && (hw_seq != *bufmgr_fake->last_dispatch)) + busy_count = 0; + else + busy_count++; + } while (kernel_lied || ret == -EAGAIN || ret == -EINTR || + (ret == -EBUSY && busy_count < 5)); + + if (ret != 0) { + drmMsg("%s:%d: Error waiting for fence: %s.\n", __FILE__, + __LINE__, strerror(-ret)); + abort(); + } + clear_fenced(bufmgr_fake, seq); +} + +static int +_fence_test(drm_intel_bufmgr_fake *bufmgr_fake, unsigned fence) +{ + /* Slight problem with wrap-around: + */ + return fence == 0 || FENCE_LTE(fence, bufmgr_fake->last_fence); +} + +/** + * Allocate a memory manager block for the buffer. + */ +static int +alloc_block(drm_intel_bo *bo) +{ + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + struct block *block = (struct block *)calloc(sizeof *block, 1); + unsigned int align_log2 = ffs(bo_fake->alignment) - 1; + unsigned int sz; + + if (!block) + return 1; + + sz = (bo->size + bo_fake->alignment - 1) & ~(bo_fake->alignment - 1); + + block->mem = mmAllocMem(bufmgr_fake->heap, sz, align_log2, 0); + if (!block->mem) { + free(block); + return 0; + } + + DRMINITLISTHEAD(block); + + /* Insert at head or at tail??? */ + DRMLISTADDTAIL(block, &bufmgr_fake->lru); + + block->virtual = (uint8_t *) bufmgr_fake->virtual + + block->mem->ofs - bufmgr_fake->low_offset; + block->bo = bo; + + bo_fake->block = block; + + return 1; +} + +/* Release the card storage associated with buf: + */ +static void +free_block(drm_intel_bufmgr_fake *bufmgr_fake, struct block *block, + int skip_dirty_copy) +{ + drm_intel_bo_fake *bo_fake; + DBG("free block %p %08x %d %d\n", block, block->mem->ofs, + block->on_hardware, block->fenced); + + if (!block) + return; + + bo_fake = (drm_intel_bo_fake *) block->bo; + + if (bo_fake->flags & (BM_PINNED | BM_NO_BACKING_STORE)) + skip_dirty_copy = 1; + + if (!skip_dirty_copy && (bo_fake->card_dirty == 1)) { + memcpy(bo_fake->backing_store, block->virtual, block->bo->size); + bo_fake->card_dirty = 0; + bo_fake->dirty = 1; + } + + if (block->on_hardware) { + block->bo = NULL; + } else if (block->fenced) { + block->bo = NULL; + } else { + DBG(" - free immediately\n"); + DRMLISTDEL(block); + + mmFreeMem(block->mem); + free(block); + } +} + +static void +alloc_backing_store(drm_intel_bo *bo) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + assert(!bo_fake->backing_store); + assert(!(bo_fake->flags & (BM_PINNED | BM_NO_BACKING_STORE))); + + bo_fake->backing_store = malloc(bo->size); + + DBG("alloc_backing - buf %d %p %d\n", bo_fake->id, + bo_fake->backing_store, bo->size); + assert(bo_fake->backing_store); +} + +static void +free_backing_store(drm_intel_bo *bo) +{ + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + + if (bo_fake->backing_store) { + assert(!(bo_fake->flags & (BM_PINNED | BM_NO_BACKING_STORE))); + free(bo_fake->backing_store); + bo_fake->backing_store = NULL; + } +} + +static void +set_dirty(drm_intel_bo *bo) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + + if (bo_fake->flags & BM_NO_BACKING_STORE + && bo_fake->invalidate_cb != NULL) + bo_fake->invalidate_cb(bo, bo_fake->invalidate_ptr); + + assert(!(bo_fake->flags & BM_PINNED)); + + DBG("set_dirty - buf %d\n", bo_fake->id); + bo_fake->dirty = 1; +} + +static int +evict_lru(drm_intel_bufmgr_fake *bufmgr_fake, unsigned int max_fence) +{ + struct block *block, *tmp; + + DBG("%s\n", __FUNCTION__); + + DRMLISTFOREACHSAFE(block, tmp, &bufmgr_fake->lru) { + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) block->bo; + + if (bo_fake != NULL && (bo_fake->flags & BM_NO_FENCE_SUBDATA)) + continue; + + if (block->fence && max_fence && !FENCE_LTE(block->fence, + max_fence)) + return 0; + + set_dirty(&bo_fake->bo); + bo_fake->block = NULL; + + free_block(bufmgr_fake, block, 0); + return 1; + } + + return 0; +} + +static int +evict_mru(drm_intel_bufmgr_fake *bufmgr_fake) +{ + struct block *block, *tmp; + + DBG("%s\n", __FUNCTION__); + + DRMLISTFOREACHSAFEREVERSE(block, tmp, &bufmgr_fake->lru) { + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) block->bo; + + if (bo_fake && (bo_fake->flags & BM_NO_FENCE_SUBDATA)) + continue; + + set_dirty(&bo_fake->bo); + bo_fake->block = NULL; + + free_block(bufmgr_fake, block, 0); + return 1; + } + + return 0; +} + +/** + * Removes all objects from the fenced list older than the given fence. + */ +static int +clear_fenced(drm_intel_bufmgr_fake *bufmgr_fake, unsigned int fence_cookie) +{ + struct block *block, *tmp; + int ret = 0; + + bufmgr_fake->last_fence = fence_cookie; + DRMLISTFOREACHSAFE(block, tmp, &bufmgr_fake->fenced) { + assert(block->fenced); + + if (_fence_test(bufmgr_fake, block->fence)) { + + block->fenced = 0; + + if (!block->bo) { + DBG("delayed free: offset %x sz %x\n", + block->mem->ofs, block->mem->size); + DRMLISTDEL(block); + mmFreeMem(block->mem); + free(block); + } else { + DBG("return to lru: offset %x sz %x\n", + block->mem->ofs, block->mem->size); + DRMLISTDEL(block); + DRMLISTADDTAIL(block, &bufmgr_fake->lru); + } + + ret = 1; + } else { + /* Blocks are ordered by fence, so if one fails, all + * from here will fail also: + */ + DBG("fence not passed: offset %x sz %x %d %d \n", + block->mem->ofs, block->mem->size, block->fence, + bufmgr_fake->last_fence); + break; + } + } + + DBG("%s: %d\n", __FUNCTION__, ret); + return ret; +} + +static void +fence_blocks(drm_intel_bufmgr_fake *bufmgr_fake, unsigned fence) +{ + struct block *block, *tmp; + + DRMLISTFOREACHSAFE(block, tmp, &bufmgr_fake->on_hardware) { + DBG("Fence block %p (sz 0x%x ofs %x buf %p) with fence %d\n", + block, block->mem->size, block->mem->ofs, block->bo, fence); + block->fence = fence; + + block->on_hardware = 0; + block->fenced = 1; + + /* Move to tail of pending list here + */ + DRMLISTDEL(block); + DRMLISTADDTAIL(block, &bufmgr_fake->fenced); + } + + assert(DRMLISTEMPTY(&bufmgr_fake->on_hardware)); +} + +static int +evict_and_alloc_block(drm_intel_bo *bo) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + + assert(bo_fake->block == NULL); + + /* Search for already free memory: + */ + if (alloc_block(bo)) + return 1; + + /* If we're not thrashing, allow lru eviction to dig deeper into + * recently used textures. We'll probably be thrashing soon: + */ + if (!bufmgr_fake->thrashing) { + while (evict_lru(bufmgr_fake, 0)) + if (alloc_block(bo)) + return 1; + } + + /* Keep thrashing counter alive? + */ + if (bufmgr_fake->thrashing) + bufmgr_fake->thrashing = 20; + + /* Wait on any already pending fences - here we are waiting for any + * freed memory that has been submitted to hardware and fenced to + * become available: + */ + while (!DRMLISTEMPTY(&bufmgr_fake->fenced)) { + uint32_t fence = bufmgr_fake->fenced.next->fence; + _fence_wait_internal(bufmgr_fake, fence); + + if (alloc_block(bo)) + return 1; + } + + if (!DRMLISTEMPTY(&bufmgr_fake->on_hardware)) { + while (!DRMLISTEMPTY(&bufmgr_fake->fenced)) { + uint32_t fence = bufmgr_fake->fenced.next->fence; + _fence_wait_internal(bufmgr_fake, fence); + } + + if (!bufmgr_fake->thrashing) { + DBG("thrashing\n"); + } + bufmgr_fake->thrashing = 20; + + if (alloc_block(bo)) + return 1; + } + + while (evict_mru(bufmgr_fake)) + if (alloc_block(bo)) + return 1; + + DBG("%s 0x%x bytes failed\n", __FUNCTION__, bo->size); + + return 0; +} + +/*********************************************************************** + * Public functions + */ + +/** + * Wait for hardware idle by emitting a fence and waiting for it. + */ +static void +drm_intel_bufmgr_fake_wait_idle(drm_intel_bufmgr_fake *bufmgr_fake) +{ + unsigned int cookie; + + cookie = _fence_emit_internal(bufmgr_fake); + _fence_wait_internal(bufmgr_fake, cookie); +} + +/** + * Wait for rendering to a buffer to complete. + * + * It is assumed that the bathcbuffer which performed the rendering included + * the necessary flushing. + */ +static void +drm_intel_fake_bo_wait_rendering_locked(drm_intel_bo *bo) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + + if (bo_fake->block == NULL || !bo_fake->block->fenced) + return; + + _fence_wait_internal(bufmgr_fake, bo_fake->block->fence); +} + +static void +drm_intel_fake_bo_wait_rendering(drm_intel_bo *bo) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + + pthread_mutex_lock(&bufmgr_fake->lock); + drm_intel_fake_bo_wait_rendering_locked(bo); + pthread_mutex_unlock(&bufmgr_fake->lock); +} + +/* Specifically ignore texture memory sharing. + * -- just evict everything + * -- and wait for idle + */ +void +drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr) +{ + drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr; + struct block *block, *tmp; + + pthread_mutex_lock(&bufmgr_fake->lock); + + bufmgr_fake->need_fence = 1; + bufmgr_fake->fail = 0; + + /* Wait for hardware idle. We don't know where acceleration has been + * happening, so we'll need to wait anyway before letting anything get + * put on the card again. + */ + drm_intel_bufmgr_fake_wait_idle(bufmgr_fake); + + /* Check that we hadn't released the lock without having fenced the last + * set of buffers. + */ + assert(DRMLISTEMPTY(&bufmgr_fake->fenced)); + assert(DRMLISTEMPTY(&bufmgr_fake->on_hardware)); + + DRMLISTFOREACHSAFE(block, tmp, &bufmgr_fake->lru) { + assert(_fence_test(bufmgr_fake, block->fence)); + set_dirty(block->bo); + } + + pthread_mutex_unlock(&bufmgr_fake->lock); +} + +static drm_intel_bo * +drm_intel_fake_bo_alloc(drm_intel_bufmgr *bufmgr, + const char *name, + unsigned long size, + unsigned int alignment) +{ + drm_intel_bufmgr_fake *bufmgr_fake; + drm_intel_bo_fake *bo_fake; + + bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr; + + assert(size != 0); + + bo_fake = calloc(1, sizeof(*bo_fake)); + if (!bo_fake) + return NULL; + + bo_fake->bo.size = size; + bo_fake->bo.offset = -1; + bo_fake->bo.virtual = NULL; + bo_fake->bo.bufmgr = bufmgr; + bo_fake->refcount = 1; + + /* Alignment must be a power of two */ + assert((alignment & (alignment - 1)) == 0); + if (alignment == 0) + alignment = 1; + bo_fake->alignment = alignment; + bo_fake->id = ++bufmgr_fake->buf_nr; + bo_fake->name = name; + bo_fake->flags = 0; + bo_fake->is_static = 0; + + DBG("drm_bo_alloc: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name, + bo_fake->bo.size / 1024); + + return &bo_fake->bo; +} + +static drm_intel_bo * +drm_intel_fake_bo_alloc_tiled(drm_intel_bufmgr * bufmgr, + const char *name, + int x, int y, int cpp, + uint32_t *tiling_mode, + unsigned long *pitch, + unsigned long flags) +{ + unsigned long stride, aligned_y; + + /* No runtime tiling support for fake. */ + *tiling_mode = I915_TILING_NONE; + + /* Align it for being a render target. Shouldn't need anything else. */ + stride = x * cpp; + stride = ROUND_UP_TO(stride, 64); + + /* 965 subspan loading alignment */ + aligned_y = ALIGN(y, 2); + + *pitch = stride; + + return drm_intel_fake_bo_alloc(bufmgr, name, stride * aligned_y, + 4096); +} + +drm_intel_bo * +drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr, + const char *name, + unsigned long offset, + unsigned long size, void *virtual) +{ + drm_intel_bufmgr_fake *bufmgr_fake; + drm_intel_bo_fake *bo_fake; + + bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr; + + assert(size != 0); + + bo_fake = calloc(1, sizeof(*bo_fake)); + if (!bo_fake) + return NULL; + + bo_fake->bo.size = size; + bo_fake->bo.offset = offset; + bo_fake->bo.virtual = virtual; + bo_fake->bo.bufmgr = bufmgr; + bo_fake->refcount = 1; + bo_fake->id = ++bufmgr_fake->buf_nr; + bo_fake->name = name; + bo_fake->flags = BM_PINNED; + bo_fake->is_static = 1; + + DBG("drm_bo_alloc_static: (buf %d: %s, %d kb)\n", bo_fake->id, + bo_fake->name, bo_fake->bo.size / 1024); + + return &bo_fake->bo; +} + +static void +drm_intel_fake_bo_reference(drm_intel_bo *bo) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + + pthread_mutex_lock(&bufmgr_fake->lock); + bo_fake->refcount++; + pthread_mutex_unlock(&bufmgr_fake->lock); +} + +static void +drm_intel_fake_bo_reference_locked(drm_intel_bo *bo) +{ + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + + bo_fake->refcount++; +} + +static void +drm_intel_fake_bo_unreference_locked(drm_intel_bo *bo) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + int i; + + if (--bo_fake->refcount == 0) { + assert(bo_fake->map_count == 0); + /* No remaining references, so free it */ + if (bo_fake->block) + free_block(bufmgr_fake, bo_fake->block, 1); + free_backing_store(bo); + + for (i = 0; i < bo_fake->nr_relocs; i++) + drm_intel_fake_bo_unreference_locked(bo_fake->relocs[i]. + target_buf); + + DBG("drm_bo_unreference: free buf %d %s\n", bo_fake->id, + bo_fake->name); + + free(bo_fake->relocs); + free(bo); + } +} + +static void +drm_intel_fake_bo_unreference(drm_intel_bo *bo) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + + pthread_mutex_lock(&bufmgr_fake->lock); + drm_intel_fake_bo_unreference_locked(bo); + pthread_mutex_unlock(&bufmgr_fake->lock); +} + +/** + * Set the buffer as not requiring backing store, and instead get the callback + * invoked whenever it would be set dirty. + */ +void +drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo, + void (*invalidate_cb) (drm_intel_bo *bo, + void *ptr), + void *ptr) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + + pthread_mutex_lock(&bufmgr_fake->lock); + + if (bo_fake->backing_store) + free_backing_store(bo); + + bo_fake->flags |= BM_NO_BACKING_STORE; + + DBG("disable_backing_store set buf %d dirty\n", bo_fake->id); + bo_fake->dirty = 1; + bo_fake->invalidate_cb = invalidate_cb; + bo_fake->invalidate_ptr = ptr; + + /* Note that it is invalid right from the start. Also note + * invalidate_cb is called with the bufmgr locked, so cannot + * itself make bufmgr calls. + */ + if (invalidate_cb != NULL) + invalidate_cb(bo, ptr); + + pthread_mutex_unlock(&bufmgr_fake->lock); +} + +/** + * Map a buffer into bo->virtual, allocating either card memory space (If + * BM_NO_BACKING_STORE or BM_PINNED) or backing store, as necessary. + */ +static int + drm_intel_fake_bo_map_locked(drm_intel_bo *bo, int write_enable) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + + /* Static buffers are always mapped. */ + if (bo_fake->is_static) { + if (bo_fake->card_dirty) { + drm_intel_bufmgr_fake_wait_idle(bufmgr_fake); + bo_fake->card_dirty = 0; + } + return 0; + } + + /* Allow recursive mapping. Mesa may recursively map buffers with + * nested display loops, and it is used internally in bufmgr_fake + * for relocation. + */ + if (bo_fake->map_count++ != 0) + return 0; + + { + DBG("drm_bo_map: (buf %d: %s, %d kb)\n", bo_fake->id, + bo_fake->name, bo_fake->bo.size / 1024); + + if (bo->virtual != NULL) { + drmMsg("%s: already mapped\n", __FUNCTION__); + abort(); + } else if (bo_fake->flags & (BM_NO_BACKING_STORE | BM_PINNED)) { + + if (!bo_fake->block && !evict_and_alloc_block(bo)) { + DBG("%s: alloc failed\n", __FUNCTION__); + bufmgr_fake->fail = 1; + return 1; + } else { + assert(bo_fake->block); + bo_fake->dirty = 0; + + if (!(bo_fake->flags & BM_NO_FENCE_SUBDATA) && + bo_fake->block->fenced) { + drm_intel_fake_bo_wait_rendering_locked + (bo); + } + + bo->virtual = bo_fake->block->virtual; + } + } else { + if (write_enable) + set_dirty(bo); + + if (bo_fake->backing_store == 0) + alloc_backing_store(bo); + + if ((bo_fake->card_dirty == 1) && bo_fake->block) { + if (bo_fake->block->fenced) + drm_intel_fake_bo_wait_rendering_locked + (bo); + + memcpy(bo_fake->backing_store, + bo_fake->block->virtual, + bo_fake->block->bo->size); + bo_fake->card_dirty = 0; + } + + bo->virtual = bo_fake->backing_store; + } + } + + return 0; +} + +static int + drm_intel_fake_bo_map(drm_intel_bo *bo, int write_enable) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + int ret; + + pthread_mutex_lock(&bufmgr_fake->lock); + ret = drm_intel_fake_bo_map_locked(bo, write_enable); + pthread_mutex_unlock(&bufmgr_fake->lock); + + return ret; +} + +static int + drm_intel_fake_bo_unmap_locked(drm_intel_bo *bo) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + + /* Static buffers are always mapped. */ + if (bo_fake->is_static) + return 0; + + assert(bo_fake->map_count != 0); + if (--bo_fake->map_count != 0) + return 0; + + DBG("drm_bo_unmap: (buf %d: %s, %d kb)\n", bo_fake->id, bo_fake->name, + bo_fake->bo.size / 1024); + + bo->virtual = NULL; + + return 0; +} + +static int drm_intel_fake_bo_unmap(drm_intel_bo *bo) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + int ret; + + pthread_mutex_lock(&bufmgr_fake->lock); + ret = drm_intel_fake_bo_unmap_locked(bo); + pthread_mutex_unlock(&bufmgr_fake->lock); + + return ret; +} + +static int +drm_intel_fake_bo_subdata(drm_intel_bo *bo, unsigned long offset, + unsigned long size, const void *data) +{ + int ret; + + if (size == 0 || data == NULL) + return 0; + + ret = drm_intel_bo_map(bo, 1); + if (ret) + return ret; + memcpy((unsigned char *)bo->virtual + offset, data, size); + drm_intel_bo_unmap(bo); + return 0; +} + +static void + drm_intel_fake_kick_all_locked(drm_intel_bufmgr_fake *bufmgr_fake) +{ + struct block *block, *tmp; + + bufmgr_fake->performed_rendering = 0; + /* okay for ever BO that is on the HW kick it off. + seriously not afraid of the POLICE right now */ + DRMLISTFOREACHSAFE(block, tmp, &bufmgr_fake->on_hardware) { + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) block->bo; + + block->on_hardware = 0; + free_block(bufmgr_fake, block, 0); + bo_fake->block = NULL; + bo_fake->validated = 0; + if (!(bo_fake->flags & BM_NO_BACKING_STORE)) + bo_fake->dirty = 1; + } + +} + +static int + drm_intel_fake_bo_validate(drm_intel_bo *bo) +{ + drm_intel_bufmgr_fake *bufmgr_fake; + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + + bufmgr_fake = (drm_intel_bufmgr_fake *) bo->bufmgr; + + DBG("drm_bo_validate: (buf %d: %s, %d kb)\n", bo_fake->id, + bo_fake->name, bo_fake->bo.size / 1024); + + /* Sanity check: Buffers should be unmapped before being validated. + * This is not so much of a problem for bufmgr_fake, but TTM refuses, + * and the problem is harder to debug there. + */ + assert(bo_fake->map_count == 0); + + if (bo_fake->is_static) { + /* Add it to the needs-fence list */ + bufmgr_fake->need_fence = 1; + return 0; + } + + /* Allocate the card memory */ + if (!bo_fake->block && !evict_and_alloc_block(bo)) { + bufmgr_fake->fail = 1; + DBG("Failed to validate buf %d:%s\n", bo_fake->id, + bo_fake->name); + return -1; + } + + assert(bo_fake->block); + assert(bo_fake->block->bo == &bo_fake->bo); + + bo->offset = bo_fake->block->mem->ofs; + + /* Upload the buffer contents if necessary */ + if (bo_fake->dirty) { + DBG("Upload dirty buf %d:%s, sz %d offset 0x%x\n", bo_fake->id, + bo_fake->name, bo->size, bo_fake->block->mem->ofs); + + assert(!(bo_fake->flags & (BM_NO_BACKING_STORE | BM_PINNED))); + + /* Actually, should be able to just wait for a fence on the + * mmory, hich we would be tracking when we free it. Waiting + * for idle is a sufficiently large hammer for now. + */ + drm_intel_bufmgr_fake_wait_idle(bufmgr_fake); + + /* we may never have mapped this BO so it might not have any + * backing store if this happens it should be rare, but 0 the + * card memory in any case */ + if (bo_fake->backing_store) + memcpy(bo_fake->block->virtual, bo_fake->backing_store, + bo->size); + else + memset(bo_fake->block->virtual, 0, bo->size); + + bo_fake->dirty = 0; + } + + bo_fake->block->fenced = 0; + bo_fake->block->on_hardware = 1; + DRMLISTDEL(bo_fake->block); + DRMLISTADDTAIL(bo_fake->block, &bufmgr_fake->on_hardware); + + bo_fake->validated = 1; + bufmgr_fake->need_fence = 1; + + return 0; +} + +static void +drm_intel_fake_fence_validated(drm_intel_bufmgr *bufmgr) +{ + drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr; + unsigned int cookie; + + cookie = _fence_emit_internal(bufmgr_fake); + fence_blocks(bufmgr_fake, cookie); + + DBG("drm_fence_validated: 0x%08x cookie\n", cookie); +} + +static void +drm_intel_fake_destroy(drm_intel_bufmgr *bufmgr) +{ + drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr; + + pthread_mutex_destroy(&bufmgr_fake->lock); + mmDestroy(bufmgr_fake->heap); + free(bufmgr); +} + +static int +drm_intel_fake_emit_reloc(drm_intel_bo *bo, uint32_t offset, + drm_intel_bo *target_bo, uint32_t target_offset, + uint32_t read_domains, uint32_t write_domain) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + struct fake_buffer_reloc *r; + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + drm_intel_bo_fake *target_fake = (drm_intel_bo_fake *) target_bo; + int i; + + pthread_mutex_lock(&bufmgr_fake->lock); + + assert(bo); + assert(target_bo); + + if (bo_fake->relocs == NULL) { + bo_fake->relocs = + malloc(sizeof(struct fake_buffer_reloc) * MAX_RELOCS); + } + + r = &bo_fake->relocs[bo_fake->nr_relocs++]; + + assert(bo_fake->nr_relocs <= MAX_RELOCS); + + drm_intel_fake_bo_reference_locked(target_bo); + + if (!target_fake->is_static) { + bo_fake->child_size += + ALIGN(target_bo->size, target_fake->alignment); + bo_fake->child_size += target_fake->child_size; + } + r->target_buf = target_bo; + r->offset = offset; + r->last_target_offset = target_bo->offset; + r->delta = target_offset; + r->read_domains = read_domains; + r->write_domain = write_domain; + + if (bufmgr_fake->debug) { + /* Check that a conflicting relocation hasn't already been + * emitted. + */ + for (i = 0; i < bo_fake->nr_relocs - 1; i++) { + struct fake_buffer_reloc *r2 = &bo_fake->relocs[i]; + + assert(r->offset != r2->offset); + } + } + + pthread_mutex_unlock(&bufmgr_fake->lock); + + return 0; +} + +/** + * Incorporates the validation flags associated with each relocation into + * the combined validation flags for the buffer on this batchbuffer submission. + */ +static void +drm_intel_fake_calculate_domains(drm_intel_bo *bo) +{ + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + int i; + + for (i = 0; i < bo_fake->nr_relocs; i++) { + struct fake_buffer_reloc *r = &bo_fake->relocs[i]; + drm_intel_bo_fake *target_fake = + (drm_intel_bo_fake *) r->target_buf; + + /* Do the same for the tree of buffers we depend on */ + drm_intel_fake_calculate_domains(r->target_buf); + + target_fake->read_domains |= r->read_domains; + target_fake->write_domain |= r->write_domain; + } +} + +static int +drm_intel_fake_reloc_and_validate_buffer(drm_intel_bo *bo) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + int i, ret; + + assert(bo_fake->map_count == 0); + + for (i = 0; i < bo_fake->nr_relocs; i++) { + struct fake_buffer_reloc *r = &bo_fake->relocs[i]; + drm_intel_bo_fake *target_fake = + (drm_intel_bo_fake *) r->target_buf; + uint32_t reloc_data; + + /* Validate the target buffer if that hasn't been done. */ + if (!target_fake->validated) { + ret = + drm_intel_fake_reloc_and_validate_buffer(r->target_buf); + if (ret != 0) { + if (bo->virtual != NULL) + drm_intel_fake_bo_unmap_locked(bo); + return ret; + } + } + + /* Calculate the value of the relocation entry. */ + if (r->target_buf->offset != r->last_target_offset) { + reloc_data = r->target_buf->offset + r->delta; + + if (bo->virtual == NULL) + drm_intel_fake_bo_map_locked(bo, 1); + + *(uint32_t *) ((uint8_t *) bo->virtual + r->offset) = + reloc_data; + + r->last_target_offset = r->target_buf->offset; + } + } + + if (bo->virtual != NULL) + drm_intel_fake_bo_unmap_locked(bo); + + if (bo_fake->write_domain != 0) { + if (!(bo_fake->flags & (BM_NO_BACKING_STORE | BM_PINNED))) { + if (bo_fake->backing_store == 0) + alloc_backing_store(bo); + } + bo_fake->card_dirty = 1; + bufmgr_fake->performed_rendering = 1; + } + + return drm_intel_fake_bo_validate(bo); +} + +static void +drm_intel_bo_fake_post_submit(drm_intel_bo *bo) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo; + int i; + + for (i = 0; i < bo_fake->nr_relocs; i++) { + struct fake_buffer_reloc *r = &bo_fake->relocs[i]; + drm_intel_bo_fake *target_fake = + (drm_intel_bo_fake *) r->target_buf; + + if (target_fake->validated) + drm_intel_bo_fake_post_submit(r->target_buf); + + DBG("%s@0x%08x + 0x%08x -> %s@0x%08x + 0x%08x\n", + bo_fake->name, (uint32_t) bo->offset, r->offset, + target_fake->name, (uint32_t) r->target_buf->offset, + r->delta); + } + + assert(bo_fake->map_count == 0); + bo_fake->validated = 0; + bo_fake->read_domains = 0; + bo_fake->write_domain = 0; +} + +void +drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr, + int (*exec) (drm_intel_bo *bo, + unsigned int used, + void *priv), + void *priv) +{ + drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr; + + bufmgr_fake->exec = exec; + bufmgr_fake->exec_priv = priv; +} + +static int +drm_intel_fake_bo_exec(drm_intel_bo *bo, int used, + drm_clip_rect_t * cliprects, int num_cliprects, int DR4) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo->bufmgr; + drm_intel_bo_fake *batch_fake = (drm_intel_bo_fake *) bo; + struct drm_i915_batchbuffer batch; + int ret; + int retry_count = 0; + + pthread_mutex_lock(&bufmgr_fake->lock); + + bufmgr_fake->performed_rendering = 0; + + drm_intel_fake_calculate_domains(bo); + + batch_fake->read_domains = I915_GEM_DOMAIN_COMMAND; + + /* we've ran out of RAM so blow the whole lot away and retry */ +restart: + ret = drm_intel_fake_reloc_and_validate_buffer(bo); + if (bufmgr_fake->fail == 1) { + if (retry_count == 0) { + retry_count++; + drm_intel_fake_kick_all_locked(bufmgr_fake); + bufmgr_fake->fail = 0; + goto restart; + } else /* dump out the memory here */ + mmDumpMemInfo(bufmgr_fake->heap); + } + + assert(ret == 0); + + if (bufmgr_fake->exec != NULL) { + int ret = bufmgr_fake->exec(bo, used, bufmgr_fake->exec_priv); + if (ret != 0) { + pthread_mutex_unlock(&bufmgr_fake->lock); + return ret; + } + } else { + batch.start = bo->offset; + batch.used = used; + batch.cliprects = cliprects; + batch.num_cliprects = num_cliprects; + batch.DR1 = 0; + batch.DR4 = DR4; + + if (drmCommandWrite + (bufmgr_fake->fd, DRM_I915_BATCHBUFFER, &batch, + sizeof(batch))) { + drmMsg("DRM_I915_BATCHBUFFER: %d\n", -errno); + pthread_mutex_unlock(&bufmgr_fake->lock); + return -errno; + } + } + + drm_intel_fake_fence_validated(bo->bufmgr); + + drm_intel_bo_fake_post_submit(bo); + + pthread_mutex_unlock(&bufmgr_fake->lock); + + return 0; +} + +/** + * Return an error if the list of BOs will exceed the aperture size. + * + * This is a rough guess and likely to fail, as during the validate sequence we + * may place a buffer in an inopportune spot early on and then fail to fit + * a set smaller than the aperture. + */ +static int +drm_intel_fake_check_aperture_space(drm_intel_bo ** bo_array, int count) +{ + drm_intel_bufmgr_fake *bufmgr_fake = + (drm_intel_bufmgr_fake *) bo_array[0]->bufmgr; + unsigned int sz = 0; + int i; + + for (i = 0; i < count; i++) { + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) bo_array[i]; + + if (bo_fake == NULL) + continue; + + if (!bo_fake->is_static) + sz += ALIGN(bo_array[i]->size, bo_fake->alignment); + sz += bo_fake->child_size; + } + + if (sz > bufmgr_fake->size) { + DBG("check_space: overflowed bufmgr size, %dkb vs %dkb\n", + sz / 1024, bufmgr_fake->size / 1024); + return -1; + } + + DBG("drm_check_space: sz %dkb vs bufgr %dkb\n", sz / 1024, + bufmgr_fake->size / 1024); + return 0; +} + +/** + * Evicts all buffers, waiting for fences to pass and copying contents out + * as necessary. + * + * Used by the X Server on LeaveVT, when the card memory is no longer our + * own. + */ +void drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr) +{ + drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr; + struct block *block, *tmp; + + pthread_mutex_lock(&bufmgr_fake->lock); + + bufmgr_fake->need_fence = 1; + bufmgr_fake->fail = 0; + + /* Wait for hardware idle. We don't know where acceleration has been + * happening, so we'll need to wait anyway before letting anything get + * put on the card again. + */ + drm_intel_bufmgr_fake_wait_idle(bufmgr_fake); + + /* Check that we hadn't released the lock without having fenced the last + * set of buffers. + */ + assert(DRMLISTEMPTY(&bufmgr_fake->fenced)); + assert(DRMLISTEMPTY(&bufmgr_fake->on_hardware)); + + DRMLISTFOREACHSAFE(block, tmp, &bufmgr_fake->lru) { + drm_intel_bo_fake *bo_fake = (drm_intel_bo_fake *) block->bo; + /* Releases the memory, and memcpys dirty contents out if + * necessary. + */ + free_block(bufmgr_fake, block, 0); + bo_fake->block = NULL; + } + + pthread_mutex_unlock(&bufmgr_fake->lock); +} + +void drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr, + volatile unsigned int + *last_dispatch) +{ + drm_intel_bufmgr_fake *bufmgr_fake = (drm_intel_bufmgr_fake *) bufmgr; + + bufmgr_fake->last_dispatch = (volatile int *)last_dispatch; +} + +drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd, + unsigned long low_offset, + void *low_virtual, + unsigned long size, + volatile unsigned int + *last_dispatch) +{ + drm_intel_bufmgr_fake *bufmgr_fake; + + bufmgr_fake = calloc(1, sizeof(*bufmgr_fake)); + + if (pthread_mutex_init(&bufmgr_fake->lock, NULL) != 0) { + free(bufmgr_fake); + return NULL; + } + + /* Initialize allocator */ + DRMINITLISTHEAD(&bufmgr_fake->fenced); + DRMINITLISTHEAD(&bufmgr_fake->on_hardware); + DRMINITLISTHEAD(&bufmgr_fake->lru); + + bufmgr_fake->low_offset = low_offset; + bufmgr_fake->virtual = low_virtual; + bufmgr_fake->size = size; + bufmgr_fake->heap = mmInit(low_offset, size); + + /* Hook in methods */ + bufmgr_fake->bufmgr.bo_alloc = drm_intel_fake_bo_alloc; + bufmgr_fake->bufmgr.bo_alloc_for_render = drm_intel_fake_bo_alloc; + bufmgr_fake->bufmgr.bo_alloc_tiled = drm_intel_fake_bo_alloc_tiled; + bufmgr_fake->bufmgr.bo_reference = drm_intel_fake_bo_reference; + bufmgr_fake->bufmgr.bo_unreference = drm_intel_fake_bo_unreference; + bufmgr_fake->bufmgr.bo_map = drm_intel_fake_bo_map; + bufmgr_fake->bufmgr.bo_unmap = drm_intel_fake_bo_unmap; + bufmgr_fake->bufmgr.bo_subdata = drm_intel_fake_bo_subdata; + bufmgr_fake->bufmgr.bo_wait_rendering = + drm_intel_fake_bo_wait_rendering; + bufmgr_fake->bufmgr.bo_emit_reloc = drm_intel_fake_emit_reloc; + bufmgr_fake->bufmgr.destroy = drm_intel_fake_destroy; + bufmgr_fake->bufmgr.bo_exec = drm_intel_fake_bo_exec; + bufmgr_fake->bufmgr.check_aperture_space = + drm_intel_fake_check_aperture_space; + bufmgr_fake->bufmgr.debug = 0; + + bufmgr_fake->fd = fd; + bufmgr_fake->last_dispatch = (volatile int *)last_dispatch; + + return &bufmgr_fake->bufmgr; +} diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c new file mode 100644 index 0000000..b776d2f --- /dev/null +++ b/intel/intel_bufmgr_gem.c @@ -0,0 +1,2989 @@ +/************************************************************************** + * + * Copyright © 2007 Red Hat Inc. + * Copyright © 2007-2012 Intel Corporation + * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * + **************************************************************************/ +/* + * Authors: Thomas Hellström + * Keith Whitwell + * Eric Anholt + * Dave Airlie + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "errno.h" +#include "libdrm_lists.h" +#include "intel_bufmgr.h" +#include "intel_bufmgr_priv.h" +#include "intel_chipset.h" +#include "intel_aub.h" +#include "string.h" + +#include "i915_drm.h" + +#ifdef HAVE_VALGRIND +#include +#include +#define VG(x) x +#else +#define VG(x) +#endif + +#define VG_CLEAR(s) VG(memset(&s, 0, sizeof(s))) + +#define DBG(...) do { \ + if (bufmgr_gem->bufmgr.debug) \ + fprintf(stderr, __VA_ARGS__); \ +} while (0) + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +typedef struct _drm_intel_bo_gem drm_intel_bo_gem; + +struct drm_intel_gem_bo_bucket { + drmMMListHead head; + unsigned long size; +}; + +typedef struct _drm_intel_bufmgr_gem { + drm_intel_bufmgr bufmgr; + + int fd; + + int max_relocs; + + pthread_mutex_t lock; + + struct drm_i915_gem_exec_object *exec_objects; + struct drm_i915_gem_exec_object2 *exec2_objects; + drm_intel_bo **exec_bos; + int exec_size; + int exec_count; + + /** Array of lists of cached gem objects of power-of-two sizes */ + struct drm_intel_gem_bo_bucket cache_bucket[14 * 4]; + int num_buckets; + time_t time; + + drmMMListHead named; + drmMMListHead vma_cache; + int vma_count, vma_open, vma_max; + + uint64_t gtt_size; + int available_fences; + int pci_device; + int gen; + unsigned int has_bsd : 1; + unsigned int has_blt : 1; + unsigned int has_relaxed_fencing : 1; + unsigned int has_llc : 1; + unsigned int bo_reuse : 1; + unsigned int no_exec : 1; + bool fenced_relocs; + + FILE *aub_file; + uint32_t aub_offset; +} drm_intel_bufmgr_gem; + +#define DRM_INTEL_RELOC_FENCE (1<<0) + +typedef struct _drm_intel_reloc_target_info { + drm_intel_bo *bo; + int flags; +} drm_intel_reloc_target; + +struct _drm_intel_bo_gem { + drm_intel_bo bo; + + atomic_t refcount; + uint32_t gem_handle; + const char *name; + + /** + * Kenel-assigned global name for this object + */ + unsigned int global_name; + drmMMListHead name_list; + + /** + * Index of the buffer within the validation list while preparing a + * batchbuffer execution. + */ + int validate_index; + + /** + * Current tiling mode + */ + uint32_t tiling_mode; + uint32_t swizzle_mode; + unsigned long stride; + + time_t free_time; + + /** Array passed to the DRM containing relocation information. */ + struct drm_i915_gem_relocation_entry *relocs; + /** + * Array of info structs corresponding to relocs[i].target_handle etc + */ + drm_intel_reloc_target *reloc_target_info; + /** Number of entries in relocs */ + int reloc_count; + /** Mapped address for the buffer, saved across map/unmap cycles */ + void *mem_virtual; + /** GTT virtual address for the buffer, saved across map/unmap cycles */ + void *gtt_virtual; + int map_count; + drmMMListHead vma_list; + + /** BO cache list */ + drmMMListHead head; + + /** + * Boolean of whether this BO and its children have been included in + * the current drm_intel_bufmgr_check_aperture_space() total. + */ + bool included_in_check_aperture; + + /** + * Boolean of whether this buffer has been used as a relocation + * target and had its size accounted for, and thus can't have any + * further relocations added to it. + */ + bool used_as_reloc_target; + + /** + * Boolean of whether we have encountered an error whilst building the relocation tree. + */ + bool has_error; + + /** + * Boolean of whether this buffer can be re-used + */ + bool reusable; + + /** + * Size in bytes of this buffer and its relocation descendents. + * + * Used to avoid costly tree walking in + * drm_intel_bufmgr_check_aperture in the common case. + */ + int reloc_tree_size; + + /** + * Number of potential fence registers required by this buffer and its + * relocations. + */ + int reloc_tree_fences; + + /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */ + bool mapped_cpu_write; + + uint32_t aub_offset; + + drm_intel_aub_annotation *aub_annotations; + unsigned aub_annotation_count; +}; + +static unsigned int +drm_intel_gem_estimate_batch_space(drm_intel_bo ** bo_array, int count); + +static unsigned int +drm_intel_gem_compute_batch_space(drm_intel_bo ** bo_array, int count); + +static int +drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, + uint32_t * swizzle_mode); + +static int +drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo, + uint32_t tiling_mode, + uint32_t stride); + +static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo, + time_t time); + +static void drm_intel_gem_bo_unreference(drm_intel_bo *bo); + +static void drm_intel_gem_bo_free(drm_intel_bo *bo); + +static unsigned long +drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size, + uint32_t *tiling_mode) +{ + unsigned long min_size, max_size; + unsigned long i; + + if (*tiling_mode == I915_TILING_NONE) + return size; + + /* 965+ just need multiples of page size for tiling */ + if (bufmgr_gem->gen >= 4) + return ROUND_UP_TO(size, 4096); + + /* Older chips need powers of two, of at least 512k or 1M */ + if (bufmgr_gem->gen == 3) { + min_size = 1024*1024; + max_size = 128*1024*1024; + } else { + min_size = 512*1024; + max_size = 64*1024*1024; + } + + if (size > max_size) { + *tiling_mode = I915_TILING_NONE; + return size; + } + + /* Do we need to allocate every page for the fence? */ + if (bufmgr_gem->has_relaxed_fencing) + return ROUND_UP_TO(size, 4096); + + for (i = min_size; i < size; i <<= 1) + ; + + return i; +} + +/* + * Round a given pitch up to the minimum required for X tiling on a + * given chip. We use 512 as the minimum to allow for a later tiling + * change. + */ +static unsigned long +drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem, + unsigned long pitch, uint32_t *tiling_mode) +{ + unsigned long tile_width; + unsigned long i; + + /* If untiled, then just align it so that we can do rendering + * to it with the 3D engine. + */ + if (*tiling_mode == I915_TILING_NONE) + return ALIGN(pitch, 64); + + if (*tiling_mode == I915_TILING_X + || (IS_915(bufmgr_gem->pci_device) + && *tiling_mode == I915_TILING_Y)) + tile_width = 512; + else + tile_width = 128; + + /* 965 is flexible */ + if (bufmgr_gem->gen >= 4) + return ROUND_UP_TO(pitch, tile_width); + + /* The older hardware has a maximum pitch of 8192 with tiled + * surfaces, so fallback to untiled if it's too large. + */ + if (pitch > 8192) { + *tiling_mode = I915_TILING_NONE; + return ALIGN(pitch, 64); + } + + /* Pre-965 needs power of two tile width */ + for (i = tile_width; i < pitch; i <<= 1) + ; + + return i; +} + +static struct drm_intel_gem_bo_bucket * +drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem, + unsigned long size) +{ + int i; + + for (i = 0; i < bufmgr_gem->num_buckets; i++) { + struct drm_intel_gem_bo_bucket *bucket = + &bufmgr_gem->cache_bucket[i]; + if (bucket->size >= size) { + return bucket; + } + } + + return NULL; +} + +static void +drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem) +{ + int i, j; + + for (i = 0; i < bufmgr_gem->exec_count; i++) { + drm_intel_bo *bo = bufmgr_gem->exec_bos[i]; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + if (bo_gem->relocs == NULL) { + DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle, + bo_gem->name); + continue; + } + + for (j = 0; j < bo_gem->reloc_count; j++) { + drm_intel_bo *target_bo = bo_gem->reloc_target_info[j].bo; + drm_intel_bo_gem *target_gem = + (drm_intel_bo_gem *) target_bo; + + DBG("%2d: %d (%s)@0x%08llx -> " + "%d (%s)@0x%08lx + 0x%08x\n", + i, + bo_gem->gem_handle, bo_gem->name, + (unsigned long long)bo_gem->relocs[j].offset, + target_gem->gem_handle, + target_gem->name, + target_bo->offset, + bo_gem->relocs[j].delta); + } + } +} + +static inline void +drm_intel_gem_bo_reference(drm_intel_bo *bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + atomic_inc(&bo_gem->refcount); +} + +/** + * Adds the given buffer to the list of buffers to be validated (moved into the + * appropriate memory type) with the next batch submission. + * + * If a buffer is validated multiple times in a batch submission, it ends up + * with the intersection of the memory type flags and the union of the + * access flags. + */ +static void +drm_intel_add_validate_buffer(drm_intel_bo *bo) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + int index; + + if (bo_gem->validate_index != -1) + return; + + /* Extend the array of validation entries as necessary. */ + if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) { + int new_size = bufmgr_gem->exec_size * 2; + + if (new_size == 0) + new_size = 5; + + bufmgr_gem->exec_objects = + realloc(bufmgr_gem->exec_objects, + sizeof(*bufmgr_gem->exec_objects) * new_size); + bufmgr_gem->exec_bos = + realloc(bufmgr_gem->exec_bos, + sizeof(*bufmgr_gem->exec_bos) * new_size); + bufmgr_gem->exec_size = new_size; + } + + index = bufmgr_gem->exec_count; + bo_gem->validate_index = index; + /* Fill in array entry */ + bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle; + bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count; + bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t) bo_gem->relocs; + bufmgr_gem->exec_objects[index].alignment = 0; + bufmgr_gem->exec_objects[index].offset = 0; + bufmgr_gem->exec_bos[index] = bo; + bufmgr_gem->exec_count++; +} + +static void +drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; + int index; + + if (bo_gem->validate_index != -1) { + if (need_fence) + bufmgr_gem->exec2_objects[bo_gem->validate_index].flags |= + EXEC_OBJECT_NEEDS_FENCE; + return; + } + + /* Extend the array of validation entries as necessary. */ + if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) { + int new_size = bufmgr_gem->exec_size * 2; + + if (new_size == 0) + new_size = 5; + + bufmgr_gem->exec2_objects = + realloc(bufmgr_gem->exec2_objects, + sizeof(*bufmgr_gem->exec2_objects) * new_size); + bufmgr_gem->exec_bos = + realloc(bufmgr_gem->exec_bos, + sizeof(*bufmgr_gem->exec_bos) * new_size); + bufmgr_gem->exec_size = new_size; + } + + index = bufmgr_gem->exec_count; + bo_gem->validate_index = index; + /* Fill in array entry */ + bufmgr_gem->exec2_objects[index].handle = bo_gem->gem_handle; + bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count; + bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs; + bufmgr_gem->exec2_objects[index].alignment = 0; + bufmgr_gem->exec2_objects[index].offset = 0; + bufmgr_gem->exec_bos[index] = bo; + bufmgr_gem->exec2_objects[index].flags = 0; + bufmgr_gem->exec2_objects[index].rsvd1 = 0; + bufmgr_gem->exec2_objects[index].rsvd2 = 0; + if (need_fence) { + bufmgr_gem->exec2_objects[index].flags |= + EXEC_OBJECT_NEEDS_FENCE; + } + bufmgr_gem->exec_count++; +} + +#define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \ + sizeof(uint32_t)) + +static void +drm_intel_bo_gem_set_in_aperture_size(drm_intel_bufmgr_gem *bufmgr_gem, + drm_intel_bo_gem *bo_gem) +{ + int size; + + assert(!bo_gem->used_as_reloc_target); + + /* The older chipsets are far-less flexible in terms of tiling, + * and require tiled buffer to be size aligned in the aperture. + * This means that in the worst possible case we will need a hole + * twice as large as the object in order for it to fit into the + * aperture. Optimal packing is for wimps. + */ + size = bo_gem->bo.size; + if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) { + int min_size; + + if (bufmgr_gem->has_relaxed_fencing) { + if (bufmgr_gem->gen == 3) + min_size = 1024*1024; + else + min_size = 512*1024; + + while (min_size < size) + min_size *= 2; + } else + min_size = size; + + /* Account for worst-case alignment. */ + size = 2 * min_size; + } + + bo_gem->reloc_tree_size = size; +} + +static int +drm_intel_setup_reloc_list(drm_intel_bo *bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + unsigned int max_relocs = bufmgr_gem->max_relocs; + + if (bo->size / 4 < max_relocs) + max_relocs = bo->size / 4; + + bo_gem->relocs = malloc(max_relocs * + sizeof(struct drm_i915_gem_relocation_entry)); + bo_gem->reloc_target_info = malloc(max_relocs * + sizeof(drm_intel_reloc_target)); + if (bo_gem->relocs == NULL || bo_gem->reloc_target_info == NULL) { + bo_gem->has_error = true; + + free (bo_gem->relocs); + bo_gem->relocs = NULL; + + free (bo_gem->reloc_target_info); + bo_gem->reloc_target_info = NULL; + + return 1; + } + + return 0; +} + +static int +drm_intel_gem_bo_busy(drm_intel_bo *bo) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_busy busy; + int ret; + + VG_CLEAR(busy); + busy.handle = bo_gem->gem_handle; + + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy); + + return (ret == 0 && busy.busy); +} + +static int +drm_intel_gem_bo_madvise_internal(drm_intel_bufmgr_gem *bufmgr_gem, + drm_intel_bo_gem *bo_gem, int state) +{ + struct drm_i915_gem_madvise madv; + + VG_CLEAR(madv); + madv.handle = bo_gem->gem_handle; + madv.madv = state; + madv.retained = 1; + drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv); + + return madv.retained; +} + +static int +drm_intel_gem_bo_madvise(drm_intel_bo *bo, int madv) +{ + return drm_intel_gem_bo_madvise_internal + ((drm_intel_bufmgr_gem *) bo->bufmgr, + (drm_intel_bo_gem *) bo, + madv); +} + +/* drop the oldest entries that have been purged by the kernel */ +static void +drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem, + struct drm_intel_gem_bo_bucket *bucket) +{ + while (!DRMLISTEMPTY(&bucket->head)) { + drm_intel_bo_gem *bo_gem; + + bo_gem = DRMLISTENTRY(drm_intel_bo_gem, + bucket->head.next, head); + if (drm_intel_gem_bo_madvise_internal + (bufmgr_gem, bo_gem, I915_MADV_DONTNEED)) + break; + + DRMLISTDEL(&bo_gem->head); + drm_intel_gem_bo_free(&bo_gem->bo); + } +} + +static drm_intel_bo * +drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, + const char *name, + unsigned long size, + unsigned long flags, + uint32_t tiling_mode, + unsigned long stride) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; + drm_intel_bo_gem *bo_gem; + unsigned int page_size = getpagesize(); + int ret; + struct drm_intel_gem_bo_bucket *bucket; + bool alloc_from_cache; + unsigned long bo_size; + bool for_render = false; + + if (flags & BO_ALLOC_FOR_RENDER) + for_render = true; + + /* Round the allocated size up to a power of two number of pages. */ + bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, size); + + /* If we don't have caching at this size, don't actually round the + * allocation up. + */ + if (bucket == NULL) { + bo_size = size; + if (bo_size < page_size) + bo_size = page_size; + } else { + bo_size = bucket->size; + } + + pthread_mutex_lock(&bufmgr_gem->lock); + /* Get a buffer out of the cache if available */ +retry: + alloc_from_cache = false; + if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) { + if (for_render) { + /* Allocate new render-target BOs from the tail (MRU) + * of the list, as it will likely be hot in the GPU + * cache and in the aperture for us. + */ + bo_gem = DRMLISTENTRY(drm_intel_bo_gem, + bucket->head.prev, head); + DRMLISTDEL(&bo_gem->head); + alloc_from_cache = true; + } else { + /* For non-render-target BOs (where we're probably + * going to map it first thing in order to fill it + * with data), check if the last BO in the cache is + * unbusy, and only reuse in that case. Otherwise, + * allocating a new buffer is probably faster than + * waiting for the GPU to finish. + */ + bo_gem = DRMLISTENTRY(drm_intel_bo_gem, + bucket->head.next, head); + if (!drm_intel_gem_bo_busy(&bo_gem->bo)) { + alloc_from_cache = true; + DRMLISTDEL(&bo_gem->head); + } + } + + if (alloc_from_cache) { + if (!drm_intel_gem_bo_madvise_internal + (bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) { + drm_intel_gem_bo_free(&bo_gem->bo); + drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem, + bucket); + goto retry; + } + + if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo, + tiling_mode, + stride)) { + drm_intel_gem_bo_free(&bo_gem->bo); + goto retry; + } + } + } + pthread_mutex_unlock(&bufmgr_gem->lock); + + if (!alloc_from_cache) { + struct drm_i915_gem_create create; + + bo_gem = calloc(1, sizeof(*bo_gem)); + if (!bo_gem) + return NULL; + + bo_gem->bo.size = bo_size; + + VG_CLEAR(create); + create.size = bo_size; + + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_CREATE, + &create); + bo_gem->gem_handle = create.handle; + bo_gem->bo.handle = bo_gem->gem_handle; + if (ret != 0) { + free(bo_gem); + return NULL; + } + bo_gem->bo.bufmgr = bufmgr; + + bo_gem->tiling_mode = I915_TILING_NONE; + bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; + bo_gem->stride = 0; + + if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo, + tiling_mode, + stride)) { + drm_intel_gem_bo_free(&bo_gem->bo); + return NULL; + } + + DRMINITLISTHEAD(&bo_gem->name_list); + DRMINITLISTHEAD(&bo_gem->vma_list); + } + + bo_gem->name = name; + atomic_set(&bo_gem->refcount, 1); + bo_gem->validate_index = -1; + bo_gem->reloc_tree_fences = 0; + bo_gem->used_as_reloc_target = false; + bo_gem->has_error = false; + bo_gem->reusable = true; + bo_gem->aub_annotations = NULL; + bo_gem->aub_annotation_count = 0; + + drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem); + + DBG("bo_create: buf %d (%s) %ldb\n", + bo_gem->gem_handle, bo_gem->name, size); + + return &bo_gem->bo; +} + +static drm_intel_bo * +drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, + const char *name, + unsigned long size, + unsigned int alignment) +{ + return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, + BO_ALLOC_FOR_RENDER, + I915_TILING_NONE, 0); +} + +static drm_intel_bo * +drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, + const char *name, + unsigned long size, + unsigned int alignment) +{ + return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0, + I915_TILING_NONE, 0); +} + +static drm_intel_bo * +drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, + int x, int y, int cpp, uint32_t *tiling_mode, + unsigned long *pitch, unsigned long flags) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; + unsigned long size, stride; + uint32_t tiling; + + do { + unsigned long aligned_y, height_alignment; + + tiling = *tiling_mode; + + /* If we're tiled, our allocations are in 8 or 32-row blocks, + * so failure to align our height means that we won't allocate + * enough pages. + * + * If we're untiled, we still have to align to 2 rows high + * because the data port accesses 2x2 blocks even if the + * bottom row isn't to be rendered, so failure to align means + * we could walk off the end of the GTT and fault. This is + * documented on 965, and may be the case on older chipsets + * too so we try to be careful. + */ + aligned_y = y; + height_alignment = 2; + + if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE) + height_alignment = 16; + else if (tiling == I915_TILING_X + || (IS_915(bufmgr_gem->pci_device) + && tiling == I915_TILING_Y)) + height_alignment = 8; + else if (tiling == I915_TILING_Y) + height_alignment = 32; + aligned_y = ALIGN(y, height_alignment); + + stride = x * cpp; + stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode); + size = stride * aligned_y; + size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode); + } while (*tiling_mode != tiling); + *pitch = stride; + + if (tiling == I915_TILING_NONE) + stride = 0; + + return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags, + tiling, stride); +} + +/** + * Returns a drm_intel_bo wrapping the given buffer object handle. + * + * This can be used when one application needs to pass a buffer object + * to another. + */ +drm_intel_bo * +drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, + const char *name, + unsigned int handle) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; + drm_intel_bo_gem *bo_gem; + int ret; + struct drm_gem_open open_arg; + struct drm_i915_gem_get_tiling get_tiling; + drmMMListHead *list; + + /* At the moment most applications only have a few named bo. + * For instance, in a DRI client only the render buffers passed + * between X and the client are named. And since X returns the + * alternating names for the front/back buffer a linear search + * provides a sufficiently fast match. + */ + for (list = bufmgr_gem->named.next; + list != &bufmgr_gem->named; + list = list->next) { + bo_gem = DRMLISTENTRY(drm_intel_bo_gem, list, name_list); + if (bo_gem->global_name == handle) { + drm_intel_gem_bo_reference(&bo_gem->bo); + return &bo_gem->bo; + } + } + + bo_gem = calloc(1, sizeof(*bo_gem)); + if (!bo_gem) + return NULL; + + VG_CLEAR(open_arg); + open_arg.name = handle; + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_GEM_OPEN, + &open_arg); + if (ret != 0) { + DBG("Couldn't reference %s handle 0x%08x: %s\n", + name, handle, strerror(errno)); + free(bo_gem); + return NULL; + } + bo_gem->bo.size = open_arg.size; + bo_gem->bo.offset = 0; + bo_gem->bo.virtual = NULL; + bo_gem->bo.bufmgr = bufmgr; + bo_gem->name = name; + atomic_set(&bo_gem->refcount, 1); + bo_gem->validate_index = -1; + bo_gem->gem_handle = open_arg.handle; + bo_gem->bo.handle = open_arg.handle; + bo_gem->global_name = handle; + bo_gem->reusable = false; + + VG_CLEAR(get_tiling); + get_tiling.handle = bo_gem->gem_handle; + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_GET_TILING, + &get_tiling); + if (ret != 0) { + drm_intel_gem_bo_unreference(&bo_gem->bo); + return NULL; + } + bo_gem->tiling_mode = get_tiling.tiling_mode; + bo_gem->swizzle_mode = get_tiling.swizzle_mode; + /* XXX stride is unknown */ + drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem); + + DRMINITLISTHEAD(&bo_gem->vma_list); + DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named); + DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name); + + return &bo_gem->bo; +} + +static void +drm_intel_gem_bo_free(drm_intel_bo *bo) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_gem_close close; + int ret; + + DRMLISTDEL(&bo_gem->vma_list); + if (bo_gem->mem_virtual) { + VG(VALGRIND_FREELIKE_BLOCK(bo_gem->mem_virtual, 0)); + munmap(bo_gem->mem_virtual, bo_gem->bo.size); + bufmgr_gem->vma_count--; + } + if (bo_gem->gtt_virtual) { + munmap(bo_gem->gtt_virtual, bo_gem->bo.size); + bufmgr_gem->vma_count--; + } + + /* Close this object */ + VG_CLEAR(close); + close.handle = bo_gem->gem_handle; + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close); + if (ret != 0) { + DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n", + bo_gem->gem_handle, bo_gem->name, strerror(errno)); + } + free(bo_gem->aub_annotations); + free(bo); +} + +static void +drm_intel_gem_bo_mark_mmaps_incoherent(drm_intel_bo *bo) +{ +#if HAVE_VALGRIND + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + if (bo_gem->mem_virtual) + VALGRIND_MAKE_MEM_NOACCESS(bo_gem->mem_virtual, bo->size); + + if (bo_gem->gtt_virtual) + VALGRIND_MAKE_MEM_NOACCESS(bo_gem->gtt_virtual, bo->size); +#endif +} + +/** Frees all cached buffers significantly older than @time. */ +static void +drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time) +{ + int i; + + if (bufmgr_gem->time == time) + return; + + for (i = 0; i < bufmgr_gem->num_buckets; i++) { + struct drm_intel_gem_bo_bucket *bucket = + &bufmgr_gem->cache_bucket[i]; + + while (!DRMLISTEMPTY(&bucket->head)) { + drm_intel_bo_gem *bo_gem; + + bo_gem = DRMLISTENTRY(drm_intel_bo_gem, + bucket->head.next, head); + if (time - bo_gem->free_time <= 1) + break; + + DRMLISTDEL(&bo_gem->head); + + drm_intel_gem_bo_free(&bo_gem->bo); + } + } + + bufmgr_gem->time = time; +} + +static void drm_intel_gem_bo_purge_vma_cache(drm_intel_bufmgr_gem *bufmgr_gem) +{ + int limit; + + DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__, + bufmgr_gem->vma_count, bufmgr_gem->vma_open, bufmgr_gem->vma_max); + + if (bufmgr_gem->vma_max < 0) + return; + + /* We may need to evict a few entries in order to create new mmaps */ + limit = bufmgr_gem->vma_max - 2*bufmgr_gem->vma_open; + if (limit < 0) + limit = 0; + + while (bufmgr_gem->vma_count > limit) { + drm_intel_bo_gem *bo_gem; + + bo_gem = DRMLISTENTRY(drm_intel_bo_gem, + bufmgr_gem->vma_cache.next, + vma_list); + assert(bo_gem->map_count == 0); + DRMLISTDELINIT(&bo_gem->vma_list); + + if (bo_gem->mem_virtual) { + munmap(bo_gem->mem_virtual, bo_gem->bo.size); + bo_gem->mem_virtual = NULL; + bufmgr_gem->vma_count--; + } + if (bo_gem->gtt_virtual) { + munmap(bo_gem->gtt_virtual, bo_gem->bo.size); + bo_gem->gtt_virtual = NULL; + bufmgr_gem->vma_count--; + } + } +} + +static void drm_intel_gem_bo_close_vma(drm_intel_bufmgr_gem *bufmgr_gem, + drm_intel_bo_gem *bo_gem) +{ + bufmgr_gem->vma_open--; + DRMLISTADDTAIL(&bo_gem->vma_list, &bufmgr_gem->vma_cache); + if (bo_gem->mem_virtual) + bufmgr_gem->vma_count++; + if (bo_gem->gtt_virtual) + bufmgr_gem->vma_count++; + drm_intel_gem_bo_purge_vma_cache(bufmgr_gem); +} + +static void drm_intel_gem_bo_open_vma(drm_intel_bufmgr_gem *bufmgr_gem, + drm_intel_bo_gem *bo_gem) +{ + bufmgr_gem->vma_open++; + DRMLISTDEL(&bo_gem->vma_list); + if (bo_gem->mem_virtual) + bufmgr_gem->vma_count--; + if (bo_gem->gtt_virtual) + bufmgr_gem->vma_count--; + drm_intel_gem_bo_purge_vma_cache(bufmgr_gem); +} + +static void +drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_intel_gem_bo_bucket *bucket; + int i; + + /* Unreference all the target buffers */ + for (i = 0; i < bo_gem->reloc_count; i++) { + if (bo_gem->reloc_target_info[i].bo != bo) { + drm_intel_gem_bo_unreference_locked_timed(bo_gem-> + reloc_target_info[i].bo, + time); + } + } + bo_gem->reloc_count = 0; + bo_gem->used_as_reloc_target = false; + + DBG("bo_unreference final: %d (%s)\n", + bo_gem->gem_handle, bo_gem->name); + + /* release memory associated with this object */ + if (bo_gem->reloc_target_info) { + free(bo_gem->reloc_target_info); + bo_gem->reloc_target_info = NULL; + } + if (bo_gem->relocs) { + free(bo_gem->relocs); + bo_gem->relocs = NULL; + } + + /* Clear any left-over mappings */ + if (bo_gem->map_count) { + DBG("bo freed with non-zero map-count %d\n", bo_gem->map_count); + bo_gem->map_count = 0; + drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); + drm_intel_gem_bo_mark_mmaps_incoherent(bo); + } + + DRMLISTDEL(&bo_gem->name_list); + + bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size); + /* Put the buffer into our internal cache for reuse if we can. */ + if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL && + drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem, + I915_MADV_DONTNEED)) { + bo_gem->free_time = time; + + bo_gem->name = NULL; + bo_gem->validate_index = -1; + + DRMLISTADDTAIL(&bo_gem->head, &bucket->head); + } else { + drm_intel_gem_bo_free(bo); + } +} + +static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo, + time_t time) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + assert(atomic_read(&bo_gem->refcount) > 0); + if (atomic_dec_and_test(&bo_gem->refcount)) + drm_intel_gem_bo_unreference_final(bo, time); +} + +static void drm_intel_gem_bo_unreference(drm_intel_bo *bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + assert(atomic_read(&bo_gem->refcount) > 0); + if (atomic_dec_and_test(&bo_gem->refcount)) { + drm_intel_bufmgr_gem *bufmgr_gem = + (drm_intel_bufmgr_gem *) bo->bufmgr; + struct timespec time; + + clock_gettime(CLOCK_MONOTONIC, &time); + + pthread_mutex_lock(&bufmgr_gem->lock); + drm_intel_gem_bo_unreference_final(bo, time.tv_sec); + drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec); + pthread_mutex_unlock(&bufmgr_gem->lock); + } +} + +static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_set_domain set_domain; + int ret; + + pthread_mutex_lock(&bufmgr_gem->lock); + + if (bo_gem->map_count++ == 0) + drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem); + + if (!bo_gem->mem_virtual) { + struct drm_i915_gem_mmap mmap_arg; + + DBG("bo_map: %d (%s), map_count=%d\n", + bo_gem->gem_handle, bo_gem->name, bo_gem->map_count); + + VG_CLEAR(mmap_arg); + mmap_arg.handle = bo_gem->gem_handle; + mmap_arg.offset = 0; + mmap_arg.size = bo->size; + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_MMAP, + &mmap_arg); + if (ret != 0) { + ret = -errno; + DBG("%s:%d: Error mapping buffer %d (%s): %s .\n", + __FILE__, __LINE__, bo_gem->gem_handle, + bo_gem->name, strerror(errno)); + if (--bo_gem->map_count == 0) + drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); + pthread_mutex_unlock(&bufmgr_gem->lock); + return ret; + } + VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1)); + bo_gem->mem_virtual = (void *)(uintptr_t) mmap_arg.addr_ptr; + } + DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, + bo_gem->mem_virtual); + bo->virtual = bo_gem->mem_virtual; + + VG_CLEAR(set_domain); + set_domain.handle = bo_gem->gem_handle; + set_domain.read_domains = I915_GEM_DOMAIN_CPU; + if (write_enable) + set_domain.write_domain = I915_GEM_DOMAIN_CPU; + else + set_domain.write_domain = 0; + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_SET_DOMAIN, + &set_domain); + if (ret != 0) { + DBG("%s:%d: Error setting to CPU domain %d: %s\n", + __FILE__, __LINE__, bo_gem->gem_handle, + strerror(errno)); + } + + if (write_enable) + bo_gem->mapped_cpu_write = true; + + drm_intel_gem_bo_mark_mmaps_incoherent(bo); + VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->mem_virtual, bo->size)); + pthread_mutex_unlock(&bufmgr_gem->lock); + + return 0; +} + +static int +map_gtt(drm_intel_bo *bo) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + int ret; + + if (bo_gem->map_count++ == 0) + drm_intel_gem_bo_open_vma(bufmgr_gem, bo_gem); + + /* Get a mapping of the buffer if we haven't before. */ + if (bo_gem->gtt_virtual == NULL) { + struct drm_i915_gem_mmap_gtt mmap_arg; + + DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n", + bo_gem->gem_handle, bo_gem->name, bo_gem->map_count); + + VG_CLEAR(mmap_arg); + mmap_arg.handle = bo_gem->gem_handle; + + /* Get the fake offset back... */ + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_MMAP_GTT, + &mmap_arg); + if (ret != 0) { + ret = -errno; + DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n", + __FILE__, __LINE__, + bo_gem->gem_handle, bo_gem->name, + strerror(errno)); + if (--bo_gem->map_count == 0) + drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); + return ret; + } + + /* and mmap it */ + bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE, + MAP_SHARED, bufmgr_gem->fd, + mmap_arg.offset); + if (bo_gem->gtt_virtual == MAP_FAILED) { + bo_gem->gtt_virtual = NULL; + ret = -errno; + DBG("%s:%d: Error mapping buffer %d (%s): %s .\n", + __FILE__, __LINE__, + bo_gem->gem_handle, bo_gem->name, + strerror(errno)); + if (--bo_gem->map_count == 0) + drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); + return ret; + } + } + + bo->virtual = bo_gem->gtt_virtual; + + DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, + bo_gem->gtt_virtual); + + return 0; +} + +int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_set_domain set_domain; + int ret; + + pthread_mutex_lock(&bufmgr_gem->lock); + + ret = map_gtt(bo); + if (ret) { + pthread_mutex_unlock(&bufmgr_gem->lock); + return ret; + } + + /* Now move it to the GTT domain so that the GPU and CPU + * caches are flushed and the GPU isn't actively using the + * buffer. + * + * The pagefault handler does this domain change for us when + * it has unbound the BO from the GTT, but it's up to us to + * tell it when we're about to use things if we had done + * rendering and it still happens to be bound to the GTT. + */ + VG_CLEAR(set_domain); + set_domain.handle = bo_gem->gem_handle; + set_domain.read_domains = I915_GEM_DOMAIN_GTT; + set_domain.write_domain = I915_GEM_DOMAIN_GTT; + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_SET_DOMAIN, + &set_domain); + if (ret != 0) { + DBG("%s:%d: Error setting domain %d: %s\n", + __FILE__, __LINE__, bo_gem->gem_handle, + strerror(errno)); + } + + drm_intel_gem_bo_mark_mmaps_incoherent(bo); + VG(VALGRIND_MAKE_MEM_DEFINED(bo_gem->gtt_virtual, bo->size)); + pthread_mutex_unlock(&bufmgr_gem->lock); + + return 0; +} + +/** + * Performs a mapping of the buffer object like the normal GTT + * mapping, but avoids waiting for the GPU to be done reading from or + * rendering to the buffer. + * + * This is used in the implementation of GL_ARB_map_buffer_range: The + * user asks to create a buffer, then does a mapping, fills some + * space, runs a drawing command, then asks to map it again without + * synchronizing because it guarantees that it won't write over the + * data that the GPU is busy using (or, more specifically, that if it + * does write over the data, it acknowledges that rendering is + * undefined). + */ + +int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + int ret; + + /* If the CPU cache isn't coherent with the GTT, then use a + * regular synchronized mapping. The problem is that we don't + * track where the buffer was last used on the CPU side in + * terms of drm_intel_bo_map vs drm_intel_gem_bo_map_gtt, so + * we would potentially corrupt the buffer even when the user + * does reasonable things. + */ + if (!bufmgr_gem->has_llc) + return drm_intel_gem_bo_map_gtt(bo); + + pthread_mutex_lock(&bufmgr_gem->lock); + ret = map_gtt(bo); + pthread_mutex_unlock(&bufmgr_gem->lock); + + return ret; +} + +static int drm_intel_gem_bo_unmap(drm_intel_bo *bo) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + int ret = 0; + + if (bo == NULL) + return 0; + + pthread_mutex_lock(&bufmgr_gem->lock); + + if (bo_gem->map_count <= 0) { + DBG("attempted to unmap an unmapped bo\n"); + pthread_mutex_unlock(&bufmgr_gem->lock); + /* Preserve the old behaviour of just treating this as a + * no-op rather than reporting the error. + */ + return 0; + } + + if (bo_gem->mapped_cpu_write) { + struct drm_i915_gem_sw_finish sw_finish; + + /* Cause a flush to happen if the buffer's pinned for + * scanout, so the results show up in a timely manner. + * Unlike GTT set domains, this only does work if the + * buffer should be scanout-related. + */ + VG_CLEAR(sw_finish); + sw_finish.handle = bo_gem->gem_handle; + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_SW_FINISH, + &sw_finish); + ret = ret == -1 ? -errno : 0; + + bo_gem->mapped_cpu_write = false; + } + + /* We need to unmap after every innovation as we cannot track + * an open vma for every bo as that will exhaasut the system + * limits and cause later failures. + */ + if (--bo_gem->map_count == 0) { + drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); + drm_intel_gem_bo_mark_mmaps_incoherent(bo); + bo->virtual = NULL; + } + pthread_mutex_unlock(&bufmgr_gem->lock); + + return ret; +} + +int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo) +{ + return drm_intel_gem_bo_unmap(bo); +} + +static int +drm_intel_gem_bo_subdata(drm_intel_bo *bo, unsigned long offset, + unsigned long size, const void *data) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_pwrite pwrite; + int ret; + + VG_CLEAR(pwrite); + pwrite.handle = bo_gem->gem_handle; + pwrite.offset = offset; + pwrite.size = size; + pwrite.data_ptr = (uint64_t) (uintptr_t) data; + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_PWRITE, + &pwrite); + if (ret != 0) { + ret = -errno; + DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n", + __FILE__, __LINE__, bo_gem->gem_handle, (int)offset, + (int)size, strerror(errno)); + } + + return ret; +} + +static int +drm_intel_gem_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; + struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id; + int ret; + + VG_CLEAR(get_pipe_from_crtc_id); + get_pipe_from_crtc_id.crtc_id = crtc_id; + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID, + &get_pipe_from_crtc_id); + if (ret != 0) { + /* We return -1 here to signal that we don't + * know which pipe is associated with this crtc. + * This lets the caller know that this information + * isn't available; using the wrong pipe for + * vblank waiting can cause the chipset to lock up + */ + return -1; + } + + return get_pipe_from_crtc_id.pipe; +} + +static int +drm_intel_gem_bo_get_subdata(drm_intel_bo *bo, unsigned long offset, + unsigned long size, void *data) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_pread pread; + int ret; + + VG_CLEAR(pread); + pread.handle = bo_gem->gem_handle; + pread.offset = offset; + pread.size = size; + pread.data_ptr = (uint64_t) (uintptr_t) data; + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_PREAD, + &pread); + if (ret != 0) { + ret = -errno; + DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n", + __FILE__, __LINE__, bo_gem->gem_handle, (int)offset, + (int)size, strerror(errno)); + } + + return ret; +} + +/** Waits for all GPU rendering with the object to have completed. */ +static void +drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo) +{ + drm_intel_gem_bo_start_gtt_access(bo, 1); +} + +/** + * Sets the object to the GTT read and possibly write domain, used by the X + * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt(). + * + * In combination with drm_intel_gem_bo_pin() and manual fence management, we + * can do tiled pixmaps this way. + */ +void +drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_set_domain set_domain; + int ret; + + VG_CLEAR(set_domain); + set_domain.handle = bo_gem->gem_handle; + set_domain.read_domains = I915_GEM_DOMAIN_GTT; + set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0; + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_SET_DOMAIN, + &set_domain); + if (ret != 0) { + DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n", + __FILE__, __LINE__, bo_gem->gem_handle, + set_domain.read_domains, set_domain.write_domain, + strerror(errno)); + } +} + +static void +drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; + int i; + + free(bufmgr_gem->exec2_objects); + free(bufmgr_gem->exec_objects); + free(bufmgr_gem->exec_bos); + + pthread_mutex_destroy(&bufmgr_gem->lock); + + /* Free any cached buffer objects we were going to reuse */ + for (i = 0; i < bufmgr_gem->num_buckets; i++) { + struct drm_intel_gem_bo_bucket *bucket = + &bufmgr_gem->cache_bucket[i]; + drm_intel_bo_gem *bo_gem; + + while (!DRMLISTEMPTY(&bucket->head)) { + bo_gem = DRMLISTENTRY(drm_intel_bo_gem, + bucket->head.next, head); + DRMLISTDEL(&bo_gem->head); + + drm_intel_gem_bo_free(&bo_gem->bo); + } + } + + free(bufmgr); +} + +/** + * Adds the target buffer to the validation list and adds the relocation + * to the reloc_buffer's relocation list. + * + * The relocation entry at the given offset must already contain the + * precomputed relocation value, because the kernel will optimize out + * the relocation entry write when the buffer hasn't moved from the + * last known offset in target_bo. + */ +static int +do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, + drm_intel_bo *target_bo, uint32_t target_offset, + uint32_t read_domains, uint32_t write_domain, + bool need_fence) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo; + bool fenced_command; + + if (bo_gem->has_error) + return -ENOMEM; + + if (target_bo_gem->has_error) { + bo_gem->has_error = true; + return -ENOMEM; + } + + /* We never use HW fences for rendering on 965+ */ + if (bufmgr_gem->gen >= 4) + need_fence = false; + + fenced_command = need_fence; + if (target_bo_gem->tiling_mode == I915_TILING_NONE) + need_fence = false; + + /* Create a new relocation list if needed */ + if (bo_gem->relocs == NULL && drm_intel_setup_reloc_list(bo)) + return -ENOMEM; + + /* Check overflow */ + assert(bo_gem->reloc_count < bufmgr_gem->max_relocs); + + /* Check args */ + assert(offset <= bo->size - 4); + assert((write_domain & (write_domain - 1)) == 0); + + /* Make sure that we're not adding a reloc to something whose size has + * already been accounted for. + */ + assert(!bo_gem->used_as_reloc_target); + if (target_bo_gem != bo_gem) { + target_bo_gem->used_as_reloc_target = true; + bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size; + } + /* An object needing a fence is a tiled buffer, so it won't have + * relocs to other buffers. + */ + if (need_fence) + target_bo_gem->reloc_tree_fences = 1; + bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences; + + bo_gem->relocs[bo_gem->reloc_count].offset = offset; + bo_gem->relocs[bo_gem->reloc_count].delta = target_offset; + bo_gem->relocs[bo_gem->reloc_count].target_handle = + target_bo_gem->gem_handle; + bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains; + bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain; + bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset; + + bo_gem->reloc_target_info[bo_gem->reloc_count].bo = target_bo; + if (target_bo != bo) + drm_intel_gem_bo_reference(target_bo); + if (fenced_command) + bo_gem->reloc_target_info[bo_gem->reloc_count].flags = + DRM_INTEL_RELOC_FENCE; + else + bo_gem->reloc_target_info[bo_gem->reloc_count].flags = 0; + + bo_gem->reloc_count++; + + return 0; +} + +static int +drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, + drm_intel_bo *target_bo, uint32_t target_offset, + uint32_t read_domains, uint32_t write_domain) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; + + return do_bo_emit_reloc(bo, offset, target_bo, target_offset, + read_domains, write_domain, + !bufmgr_gem->fenced_relocs); +} + +static int +drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset, + drm_intel_bo *target_bo, + uint32_t target_offset, + uint32_t read_domains, uint32_t write_domain) +{ + return do_bo_emit_reloc(bo, offset, target_bo, target_offset, + read_domains, write_domain, true); +} + +int +drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + return bo_gem->reloc_count; +} + +/** + * Removes existing relocation entries in the BO after "start". + * + * This allows a user to avoid a two-step process for state setup with + * counting up all the buffer objects and doing a + * drm_intel_bufmgr_check_aperture_space() before emitting any of the + * relocations for the state setup. Instead, save the state of the + * batchbuffer including drm_intel_gem_get_reloc_count(), emit all the + * state, and then check if it still fits in the aperture. + * + * Any further drm_intel_bufmgr_check_aperture_space() queries + * involving this buffer in the tree are undefined after this call. + */ +void +drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + int i; + struct timespec time; + + clock_gettime(CLOCK_MONOTONIC, &time); + + assert(bo_gem->reloc_count >= start); + /* Unreference the cleared target buffers */ + for (i = start; i < bo_gem->reloc_count; i++) { + if (bo_gem->reloc_target_info[i].bo != bo) { + drm_intel_gem_bo_unreference_locked_timed(bo_gem-> + reloc_target_info[i].bo, + time.tv_sec); + } + } + bo_gem->reloc_count = start; +} + +/** + * Walk the tree of relocations rooted at BO and accumulate the list of + * validations to be performed and update the relocation buffers with + * index values into the validation list. + */ +static void +drm_intel_gem_bo_process_reloc(drm_intel_bo *bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + int i; + + if (bo_gem->relocs == NULL) + return; + + for (i = 0; i < bo_gem->reloc_count; i++) { + drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo; + + if (target_bo == bo) + continue; + + drm_intel_gem_bo_mark_mmaps_incoherent(bo); + + /* Continue walking the tree depth-first. */ + drm_intel_gem_bo_process_reloc(target_bo); + + /* Add the target to the validate list */ + drm_intel_add_validate_buffer(target_bo); + } +} + +static void +drm_intel_gem_bo_process_reloc2(drm_intel_bo *bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; + int i; + + if (bo_gem->relocs == NULL) + return; + + for (i = 0; i < bo_gem->reloc_count; i++) { + drm_intel_bo *target_bo = bo_gem->reloc_target_info[i].bo; + int need_fence; + + if (target_bo == bo) + continue; + + drm_intel_gem_bo_mark_mmaps_incoherent(bo); + + /* Continue walking the tree depth-first. */ + drm_intel_gem_bo_process_reloc2(target_bo); + + need_fence = (bo_gem->reloc_target_info[i].flags & + DRM_INTEL_RELOC_FENCE); + + /* Add the target to the validate list */ + drm_intel_add_validate_buffer2(target_bo, need_fence); + } +} + + +static void +drm_intel_update_buffer_offsets(drm_intel_bufmgr_gem *bufmgr_gem) +{ + int i; + + for (i = 0; i < bufmgr_gem->exec_count; i++) { + drm_intel_bo *bo = bufmgr_gem->exec_bos[i]; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + /* Update the buffer offset */ + if (bufmgr_gem->exec_objects[i].offset != bo->offset) { + DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n", + bo_gem->gem_handle, bo_gem->name, bo->offset, + (unsigned long long)bufmgr_gem->exec_objects[i]. + offset); + bo->offset = bufmgr_gem->exec_objects[i].offset; + } + } +} + +static void +drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem) +{ + int i; + + for (i = 0; i < bufmgr_gem->exec_count; i++) { + drm_intel_bo *bo = bufmgr_gem->exec_bos[i]; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; + + /* Update the buffer offset */ + if (bufmgr_gem->exec2_objects[i].offset != bo->offset) { + DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n", + bo_gem->gem_handle, bo_gem->name, bo->offset, + (unsigned long long)bufmgr_gem->exec2_objects[i].offset); + bo->offset = bufmgr_gem->exec2_objects[i].offset; + } + } +} + +static void +aub_out(drm_intel_bufmgr_gem *bufmgr_gem, uint32_t data) +{ + fwrite(&data, 1, 4, bufmgr_gem->aub_file); +} + +static void +aub_out_data(drm_intel_bufmgr_gem *bufmgr_gem, void *data, size_t size) +{ + fwrite(data, 1, size, bufmgr_gem->aub_file); +} + +static void +aub_write_bo_data(drm_intel_bo *bo, uint32_t offset, uint32_t size) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + uint32_t *data; + unsigned int i; + + data = malloc(bo->size); + drm_intel_bo_get_subdata(bo, offset, size, data); + + /* Easy mode: write out bo with no relocations */ + if (!bo_gem->reloc_count) { + aub_out_data(bufmgr_gem, data, size); + free(data); + return; + } + + /* Otherwise, handle the relocations while writing. */ + for (i = 0; i < size / 4; i++) { + int r; + for (r = 0; r < bo_gem->reloc_count; r++) { + struct drm_i915_gem_relocation_entry *reloc; + drm_intel_reloc_target *info; + + reloc = &bo_gem->relocs[r]; + info = &bo_gem->reloc_target_info[r]; + + if (reloc->offset == offset + i * 4) { + drm_intel_bo_gem *target_gem; + uint32_t val; + + target_gem = (drm_intel_bo_gem *)info->bo; + + val = reloc->delta; + val += target_gem->aub_offset; + + aub_out(bufmgr_gem, val); + data[i] = val; + break; + } + } + if (r == bo_gem->reloc_count) { + /* no relocation, just the data */ + aub_out(bufmgr_gem, data[i]); + } + } + + free(data); +} + +static void +aub_bo_get_address(drm_intel_bo *bo) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + /* Give the object a graphics address in the AUB file. We + * don't just use the GEM object address because we do AUB + * dumping before execution -- we want to successfully log + * when the hardware might hang, and we might even want to aub + * capture for a driver trying to execute on a different + * generation of hardware by disabling the actual kernel exec + * call. + */ + bo_gem->aub_offset = bufmgr_gem->aub_offset; + bufmgr_gem->aub_offset += bo->size; + /* XXX: Handle aperture overflow. */ + assert(bufmgr_gem->aub_offset < 256 * 1024 * 1024); +} + +static void +aub_write_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype, + uint32_t offset, uint32_t size) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + aub_out(bufmgr_gem, + CMD_AUB_TRACE_HEADER_BLOCK | + (5 - 2)); + aub_out(bufmgr_gem, + AUB_TRACE_MEMTYPE_GTT | type | AUB_TRACE_OP_DATA_WRITE); + aub_out(bufmgr_gem, subtype); + aub_out(bufmgr_gem, bo_gem->aub_offset + offset); + aub_out(bufmgr_gem, size); + aub_write_bo_data(bo, offset, size); +} + +/** + * Break up large objects into multiple writes. Otherwise a 128kb VBO + * would overflow the 16 bits of size field in the packet header and + * everything goes badly after that. + */ +static void +aub_write_large_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype, + uint32_t offset, uint32_t size) +{ + uint32_t block_size; + uint32_t sub_offset; + + for (sub_offset = 0; sub_offset < size; sub_offset += block_size) { + block_size = size - sub_offset; + + if (block_size > 8 * 4096) + block_size = 8 * 4096; + + aub_write_trace_block(bo, type, subtype, offset + sub_offset, + block_size); + } +} + +static void +aub_write_bo(drm_intel_bo *bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + uint32_t offset = 0; + unsigned i; + + aub_bo_get_address(bo); + + /* Write out each annotated section separately. */ + for (i = 0; i < bo_gem->aub_annotation_count; ++i) { + drm_intel_aub_annotation *annotation = + &bo_gem->aub_annotations[i]; + uint32_t ending_offset = annotation->ending_offset; + if (ending_offset > bo->size) + ending_offset = bo->size; + if (ending_offset > offset) { + aub_write_large_trace_block(bo, annotation->type, + annotation->subtype, + offset, + ending_offset - offset); + offset = ending_offset; + } + } + + /* Write out any remaining unannotated data */ + if (offset < bo->size) { + aub_write_large_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0, + offset, bo->size - offset); + } +} + +/* + * Make a ringbuffer on fly and dump it + */ +static void +aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem, + uint32_t batch_buffer, int ring_flag) +{ + uint32_t ringbuffer[4096]; + int ring = AUB_TRACE_TYPE_RING_PRB0; /* The default ring */ + int ring_count = 0; + + if (ring_flag == I915_EXEC_BSD) + ring = AUB_TRACE_TYPE_RING_PRB1; + + /* Make a ring buffer to execute our batchbuffer. */ + memset(ringbuffer, 0, sizeof(ringbuffer)); + ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START; + ringbuffer[ring_count++] = batch_buffer; + + /* Write out the ring. This appears to trigger execution of + * the ring in the simulator. + */ + aub_out(bufmgr_gem, + CMD_AUB_TRACE_HEADER_BLOCK | + (5 - 2)); + aub_out(bufmgr_gem, + AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE); + aub_out(bufmgr_gem, 0); /* general/surface subtype */ + aub_out(bufmgr_gem, bufmgr_gem->aub_offset); + aub_out(bufmgr_gem, ring_count * 4); + + /* FIXME: Need some flush operations here? */ + aub_out_data(bufmgr_gem, ringbuffer, ring_count * 4); + + /* Update offset pointer */ + bufmgr_gem->aub_offset += 4096; +} + +void +drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo, + int x1, int y1, int width, int height, + enum aub_dump_bmp_format format, + int pitch, int offset) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; + uint32_t cpp; + + switch (format) { + case AUB_DUMP_BMP_FORMAT_8BIT: + cpp = 1; + break; + case AUB_DUMP_BMP_FORMAT_ARGB_4444: + cpp = 2; + break; + case AUB_DUMP_BMP_FORMAT_ARGB_0888: + case AUB_DUMP_BMP_FORMAT_ARGB_8888: + cpp = 4; + break; + default: + printf("Unknown AUB dump format %d\n", format); + return; + } + + if (!bufmgr_gem->aub_file) + return; + + aub_out(bufmgr_gem, CMD_AUB_DUMP_BMP | 4); + aub_out(bufmgr_gem, (y1 << 16) | x1); + aub_out(bufmgr_gem, + (format << 24) | + (cpp << 19) | + pitch / 4); + aub_out(bufmgr_gem, (height << 16) | width); + aub_out(bufmgr_gem, bo_gem->aub_offset + offset); + aub_out(bufmgr_gem, + ((bo_gem->tiling_mode != I915_TILING_NONE) ? (1 << 2) : 0) | + ((bo_gem->tiling_mode == I915_TILING_Y) ? (1 << 3) : 0)); +} + +static void +aub_exec(drm_intel_bo *bo, int ring_flag, int used) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + int i; + bool batch_buffer_needs_annotations; + + if (!bufmgr_gem->aub_file) + return; + + /* If batch buffer is not annotated, annotate it the best we + * can. + */ + batch_buffer_needs_annotations = bo_gem->aub_annotation_count == 0; + if (batch_buffer_needs_annotations) { + drm_intel_aub_annotation annotations[2] = { + { AUB_TRACE_TYPE_BATCH, 0, used }, + { AUB_TRACE_TYPE_NOTYPE, 0, bo->size } + }; + drm_intel_bufmgr_gem_set_aub_annotations(bo, annotations, 2); + } + + /* Write out all buffers to AUB memory */ + for (i = 0; i < bufmgr_gem->exec_count; i++) { + aub_write_bo(bufmgr_gem->exec_bos[i]); + } + + /* Remove any annotations we added */ + if (batch_buffer_needs_annotations) + drm_intel_bufmgr_gem_set_aub_annotations(bo, NULL, 0); + + /* Dump ring buffer */ + aub_build_dump_ringbuffer(bufmgr_gem, bo_gem->aub_offset, ring_flag); + + fflush(bufmgr_gem->aub_file); + + /* + * One frame has been dumped. So reset the aub_offset for the next frame. + * + * FIXME: Can we do this? + */ + bufmgr_gem->aub_offset = 0x10000; +} + +static int +drm_intel_gem_bo_exec(drm_intel_bo *bo, int used, + drm_clip_rect_t * cliprects, int num_cliprects, int DR4) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_execbuffer execbuf; + int ret, i; + + if (bo_gem->has_error) + return -ENOMEM; + + pthread_mutex_lock(&bufmgr_gem->lock); + /* Update indices and set up the validate list. */ + drm_intel_gem_bo_process_reloc(bo); + + /* Add the batch buffer to the validation list. There are no + * relocations pointing to it. + */ + drm_intel_add_validate_buffer(bo); + + VG_CLEAR(execbuf); + execbuf.buffers_ptr = (uintptr_t) bufmgr_gem->exec_objects; + execbuf.buffer_count = bufmgr_gem->exec_count; + execbuf.batch_start_offset = 0; + execbuf.batch_len = used; + execbuf.cliprects_ptr = (uintptr_t) cliprects; + execbuf.num_cliprects = num_cliprects; + execbuf.DR1 = 0; + execbuf.DR4 = DR4; + + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_EXECBUFFER, + &execbuf); + if (ret != 0) { + ret = -errno; + if (errno == ENOSPC) { + DBG("Execbuffer fails to pin. " + "Estimate: %u. Actual: %u. Available: %u\n", + drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos, + bufmgr_gem-> + exec_count), + drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos, + bufmgr_gem-> + exec_count), + (unsigned int)bufmgr_gem->gtt_size); + } + } + drm_intel_update_buffer_offsets(bufmgr_gem); + + if (bufmgr_gem->bufmgr.debug) + drm_intel_gem_dump_validation_list(bufmgr_gem); + + for (i = 0; i < bufmgr_gem->exec_count; i++) { + drm_intel_bo *bo = bufmgr_gem->exec_bos[i]; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + /* Disconnect the buffer from the validate list */ + bo_gem->validate_index = -1; + bufmgr_gem->exec_bos[i] = NULL; + } + bufmgr_gem->exec_count = 0; + pthread_mutex_unlock(&bufmgr_gem->lock); + + return ret; +} + +static int +drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used, + drm_clip_rect_t *cliprects, int num_cliprects, int DR4, + unsigned int flags) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; + struct drm_i915_gem_execbuffer2 execbuf; + int ret = 0; + int i; + + switch (flags & 0x7) { + default: + return -EINVAL; + case I915_EXEC_BLT: + if (!bufmgr_gem->has_blt) + return -EINVAL; + break; + case I915_EXEC_BSD: + if (!bufmgr_gem->has_bsd) + return -EINVAL; + break; + case I915_EXEC_RENDER: + case I915_EXEC_DEFAULT: + break; + } + + pthread_mutex_lock(&bufmgr_gem->lock); + /* Update indices and set up the validate list. */ + drm_intel_gem_bo_process_reloc2(bo); + + /* Add the batch buffer to the validation list. There are no relocations + * pointing to it. + */ + drm_intel_add_validate_buffer2(bo, 0); + + VG_CLEAR(execbuf); + execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec2_objects; + execbuf.buffer_count = bufmgr_gem->exec_count; + execbuf.batch_start_offset = 0; + execbuf.batch_len = used; + execbuf.cliprects_ptr = (uintptr_t)cliprects; + execbuf.num_cliprects = num_cliprects; + execbuf.DR1 = 0; + execbuf.DR4 = DR4; + execbuf.flags = flags; + execbuf.rsvd1 = 0; + execbuf.rsvd2 = 0; + + aub_exec(bo, flags, used); + + if (bufmgr_gem->no_exec) + goto skip_execution; + + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_EXECBUFFER2, + &execbuf); + if (ret != 0) { + ret = -errno; + if (ret == -ENOSPC) { + DBG("Execbuffer fails to pin. " + "Estimate: %u. Actual: %u. Available: %u\n", + drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos, + bufmgr_gem->exec_count), + drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos, + bufmgr_gem->exec_count), + (unsigned int) bufmgr_gem->gtt_size); + } + } + drm_intel_update_buffer_offsets2(bufmgr_gem); + +skip_execution: + if (bufmgr_gem->bufmgr.debug) + drm_intel_gem_dump_validation_list(bufmgr_gem); + + for (i = 0; i < bufmgr_gem->exec_count; i++) { + drm_intel_bo *bo = bufmgr_gem->exec_bos[i]; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; + + /* Disconnect the buffer from the validate list */ + bo_gem->validate_index = -1; + bufmgr_gem->exec_bos[i] = NULL; + } + bufmgr_gem->exec_count = 0; + pthread_mutex_unlock(&bufmgr_gem->lock); + + return ret; +} + +static int +drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used, + drm_clip_rect_t *cliprects, int num_cliprects, + int DR4) +{ + return drm_intel_gem_bo_mrb_exec2(bo, used, + cliprects, num_cliprects, DR4, + I915_EXEC_RENDER); +} + +static int +drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_pin pin; + int ret; + + VG_CLEAR(pin); + pin.handle = bo_gem->gem_handle; + pin.alignment = alignment; + + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_PIN, + &pin); + if (ret != 0) + return -errno; + + bo->offset = pin.offset; + return 0; +} + +static int +drm_intel_gem_bo_unpin(drm_intel_bo *bo) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_unpin unpin; + int ret; + + VG_CLEAR(unpin); + unpin.handle = bo_gem->gem_handle; + + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin); + if (ret != 0) + return -errno; + + return 0; +} + +static int +drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo, + uint32_t tiling_mode, + uint32_t stride) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + struct drm_i915_gem_set_tiling set_tiling; + int ret; + + if (bo_gem->global_name == 0 && + tiling_mode == bo_gem->tiling_mode && + stride == bo_gem->stride) + return 0; + + memset(&set_tiling, 0, sizeof(set_tiling)); + do { + /* set_tiling is slightly broken and overwrites the + * input on the error path, so we have to open code + * rmIoctl. + */ + set_tiling.handle = bo_gem->gem_handle; + set_tiling.tiling_mode = tiling_mode; + set_tiling.stride = stride; + + ret = ioctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_SET_TILING, + &set_tiling); + } while (ret == -1 && (errno == EINTR || errno == EAGAIN)); + if (ret == -1) + return -errno; + + bo_gem->tiling_mode = set_tiling.tiling_mode; + bo_gem->swizzle_mode = set_tiling.swizzle_mode; + bo_gem->stride = set_tiling.stride; + return 0; +} + +static int +drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, + uint32_t stride) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + int ret; + + /* Linear buffers have no stride. By ensuring that we only ever use + * stride 0 with linear buffers, we simplify our code. + */ + if (*tiling_mode == I915_TILING_NONE) + stride = 0; + + ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride); + if (ret == 0) + drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem); + + *tiling_mode = bo_gem->tiling_mode; + return ret; +} + +static int +drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, + uint32_t * swizzle_mode) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + *tiling_mode = bo_gem->tiling_mode; + *swizzle_mode = bo_gem->swizzle_mode; + return 0; +} + +static int +drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t * name) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + int ret; + + if (!bo_gem->global_name) { + struct drm_gem_flink flink; + + VG_CLEAR(flink); + flink.handle = bo_gem->gem_handle; + + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink); + if (ret != 0) + return -errno; + + bo_gem->global_name = flink.name; + bo_gem->reusable = false; + + DRMLISTADDTAIL(&bo_gem->name_list, &bufmgr_gem->named); + } + + *name = bo_gem->global_name; + return 0; +} + +/** + * Enables unlimited caching of buffer objects for reuse. + * + * This is potentially very memory expensive, as the cache at each bucket + * size is only bounded by how many buffers of that size we've managed to have + * in flight at once. + */ +void +drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; + + bufmgr_gem->bo_reuse = true; +} + +/** + * Enable use of fenced reloc type. + * + * New code should enable this to avoid unnecessary fence register + * allocation. If this option is not enabled, all relocs will have fence + * register allocated. + */ +void +drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; + + if (bufmgr_gem->bufmgr.bo_exec == drm_intel_gem_bo_exec2) + bufmgr_gem->fenced_relocs = true; +} + +/** + * Return the additional aperture space required by the tree of buffer objects + * rooted at bo. + */ +static int +drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + int i; + int total = 0; + + if (bo == NULL || bo_gem->included_in_check_aperture) + return 0; + + total += bo->size; + bo_gem->included_in_check_aperture = true; + + for (i = 0; i < bo_gem->reloc_count; i++) + total += + drm_intel_gem_bo_get_aperture_space(bo_gem-> + reloc_target_info[i].bo); + + return total; +} + +/** + * Count the number of buffers in this list that need a fence reg + * + * If the count is greater than the number of available regs, we'll have + * to ask the caller to resubmit a batch with fewer tiled buffers. + * + * This function over-counts if the same buffer is used multiple times. + */ +static unsigned int +drm_intel_gem_total_fences(drm_intel_bo ** bo_array, int count) +{ + int i; + unsigned int total = 0; + + for (i = 0; i < count; i++) { + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i]; + + if (bo_gem == NULL) + continue; + + total += bo_gem->reloc_tree_fences; + } + return total; +} + +/** + * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready + * for the next drm_intel_bufmgr_check_aperture_space() call. + */ +static void +drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + int i; + + if (bo == NULL || !bo_gem->included_in_check_aperture) + return; + + bo_gem->included_in_check_aperture = false; + + for (i = 0; i < bo_gem->reloc_count; i++) + drm_intel_gem_bo_clear_aperture_space_flag(bo_gem-> + reloc_target_info[i].bo); +} + +/** + * Return a conservative estimate for the amount of aperture required + * for a collection of buffers. This may double-count some buffers. + */ +static unsigned int +drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count) +{ + int i; + unsigned int total = 0; + + for (i = 0; i < count; i++) { + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo_array[i]; + if (bo_gem != NULL) + total += bo_gem->reloc_tree_size; + } + return total; +} + +/** + * Return the amount of aperture needed for a collection of buffers. + * This avoids double counting any buffers, at the cost of looking + * at every buffer in the set. + */ +static unsigned int +drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count) +{ + int i; + unsigned int total = 0; + + for (i = 0; i < count; i++) { + total += drm_intel_gem_bo_get_aperture_space(bo_array[i]); + /* For the first buffer object in the array, we get an + * accurate count back for its reloc_tree size (since nothing + * had been flagged as being counted yet). We can save that + * value out as a more conservative reloc_tree_size that + * avoids double-counting target buffers. Since the first + * buffer happens to usually be the batch buffer in our + * callers, this can pull us back from doing the tree + * walk on every new batch emit. + */ + if (i == 0) { + drm_intel_bo_gem *bo_gem = + (drm_intel_bo_gem *) bo_array[i]; + bo_gem->reloc_tree_size = total; + } + } + + for (i = 0; i < count; i++) + drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]); + return total; +} + +/** + * Return -1 if the batchbuffer should be flushed before attempting to + * emit rendering referencing the buffers pointed to by bo_array. + * + * This is required because if we try to emit a batchbuffer with relocations + * to a tree of buffers that won't simultaneously fit in the aperture, + * the rendering will return an error at a point where the software is not + * prepared to recover from it. + * + * However, we also want to emit the batchbuffer significantly before we reach + * the limit, as a series of batchbuffers each of which references buffers + * covering almost all of the aperture means that at each emit we end up + * waiting to evict a buffer from the last rendering, and we get synchronous + * performance. By emitting smaller batchbuffers, we eat some CPU overhead to + * get better parallelism. + */ +static int +drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count) +{ + drm_intel_bufmgr_gem *bufmgr_gem = + (drm_intel_bufmgr_gem *) bo_array[0]->bufmgr; + unsigned int total = 0; + unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4; + int total_fences; + + /* Check for fence reg constraints if necessary */ + if (bufmgr_gem->available_fences) { + total_fences = drm_intel_gem_total_fences(bo_array, count); + if (total_fences > bufmgr_gem->available_fences) + return -ENOSPC; + } + + total = drm_intel_gem_estimate_batch_space(bo_array, count); + + if (total > threshold) + total = drm_intel_gem_compute_batch_space(bo_array, count); + + if (total > threshold) { + DBG("check_space: overflowed available aperture, " + "%dkb vs %dkb\n", + total / 1024, (int)bufmgr_gem->gtt_size / 1024); + return -ENOSPC; + } else { + DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024, + (int)bufmgr_gem->gtt_size / 1024); + return 0; + } +} + +/* + * Disable buffer reuse for objects which are shared with the kernel + * as scanout buffers + */ +static int +drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + bo_gem->reusable = false; + return 0; +} + +static int +drm_intel_gem_bo_is_reusable(drm_intel_bo *bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + return bo_gem->reusable; +} + +static int +_drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + int i; + + for (i = 0; i < bo_gem->reloc_count; i++) { + if (bo_gem->reloc_target_info[i].bo == target_bo) + return 1; + if (bo == bo_gem->reloc_target_info[i].bo) + continue; + if (_drm_intel_gem_bo_references(bo_gem->reloc_target_info[i].bo, + target_bo)) + return 1; + } + + return 0; +} + +/** Return true if target_bo is referenced by bo's relocation tree. */ +static int +drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo) +{ + drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *) target_bo; + + if (bo == NULL || target_bo == NULL) + return 0; + if (target_bo_gem->used_as_reloc_target) + return _drm_intel_gem_bo_references(bo, target_bo); + return 0; +} + +static void +add_bucket(drm_intel_bufmgr_gem *bufmgr_gem, int size) +{ + unsigned int i = bufmgr_gem->num_buckets; + + assert(i < ARRAY_SIZE(bufmgr_gem->cache_bucket)); + + DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head); + bufmgr_gem->cache_bucket[i].size = size; + bufmgr_gem->num_buckets++; +} + +static void +init_cache_buckets(drm_intel_bufmgr_gem *bufmgr_gem) +{ + unsigned long size, cache_max_size = 64 * 1024 * 1024; + + /* OK, so power of two buckets was too wasteful of memory. + * Give 3 other sizes between each power of two, to hopefully + * cover things accurately enough. (The alternative is + * probably to just go for exact matching of sizes, and assume + * that for things like composited window resize the tiled + * width/height alignment and rounding of sizes to pages will + * get us useful cache hit rates anyway) + */ + add_bucket(bufmgr_gem, 4096); + add_bucket(bufmgr_gem, 4096 * 2); + add_bucket(bufmgr_gem, 4096 * 3); + + /* Initialize the linked lists for BO reuse cache. */ + for (size = 4 * 4096; size <= cache_max_size; size *= 2) { + add_bucket(bufmgr_gem, size); + + add_bucket(bufmgr_gem, size + size * 1 / 4); + add_bucket(bufmgr_gem, size + size * 2 / 4); + add_bucket(bufmgr_gem, size + size * 3 / 4); + } +} + +void +drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; + + bufmgr_gem->vma_max = limit; + + drm_intel_gem_bo_purge_vma_cache(bufmgr_gem); +} + +/** + * Get the PCI ID for the device. This can be overridden by setting the + * INTEL_DEVID_OVERRIDE environment variable to the desired ID. + */ +static int +get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem) +{ + char *devid_override; + int devid; + int ret; + drm_i915_getparam_t gp; + + if (geteuid() == getuid()) { + devid_override = getenv("INTEL_DEVID_OVERRIDE"); + if (devid_override) { + bufmgr_gem->no_exec = true; + return strtod(devid_override, NULL); + } + } + + VG_CLEAR(devid); + VG_CLEAR(gp); + gp.param = I915_PARAM_CHIPSET_ID; + gp.value = &devid; + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); + if (ret) { + fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno); + fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value); + } + return devid; +} + +int +drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; + + return bufmgr_gem->pci_device; +} + +/** + * Sets up AUB dumping. + * + * This is a trace file format that can be used with the simulator. + * Packets are emitted in a format somewhat like GPU command packets. + * You can set up a GTT and upload your objects into the referenced + * space, then send off batchbuffers and get BMPs out the other end. + */ +void +drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; + int entry = 0x200003; + int i; + int gtt_size = 0x10000; + + if (!enable) { + if (bufmgr_gem->aub_file) { + fclose(bufmgr_gem->aub_file); + bufmgr_gem->aub_file = NULL; + } + } + + if (geteuid() != getuid()) + return; + + bufmgr_gem->aub_file = fopen("intel.aub", "w+"); + if (!bufmgr_gem->aub_file) + return; + + /* Start allocating objects from just after the GTT. */ + bufmgr_gem->aub_offset = gtt_size; + + /* Start with a (required) version packet. */ + aub_out(bufmgr_gem, CMD_AUB_HEADER | (13 - 2)); + aub_out(bufmgr_gem, + (4 << AUB_HEADER_MAJOR_SHIFT) | + (0 << AUB_HEADER_MINOR_SHIFT)); + for (i = 0; i < 8; i++) { + aub_out(bufmgr_gem, 0); /* app name */ + } + aub_out(bufmgr_gem, 0); /* timestamp */ + aub_out(bufmgr_gem, 0); /* timestamp */ + aub_out(bufmgr_gem, 0); /* comment len */ + + /* Set up the GTT. The max we can handle is 256M */ + aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | (5 - 2)); + aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_NONLOCAL | 0 | AUB_TRACE_OP_DATA_WRITE); + aub_out(bufmgr_gem, 0); /* subtype */ + aub_out(bufmgr_gem, 0); /* offset */ + aub_out(bufmgr_gem, gtt_size); /* size */ + for (i = 0x000; i < gtt_size; i += 4, entry += 0x1000) { + aub_out(bufmgr_gem, entry); + } +} + +/** + * Annotate the given bo for use in aub dumping. + * + * \param annotations is an array of drm_intel_aub_annotation objects + * describing the type of data in various sections of the bo. Each + * element of the array specifies the type and subtype of a section of + * the bo, and the past-the-end offset of that section. The elements + * of \c annotations must be sorted so that ending_offset is + * increasing. + * + * \param count is the number of elements in the \c annotations array. + * If \c count is zero, then \c annotations will not be dereferenced. + * + * Annotations are copied into a private data structure, so caller may + * re-use the memory pointed to by \c annotations after the call + * returns. + * + * Annotations are stored for the lifetime of the bo; to reset to the + * default state (no annotations), call this function with a \c count + * of zero. + */ +void +drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo, + drm_intel_aub_annotation *annotations, + unsigned count) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + unsigned size = sizeof(*annotations) * count; + drm_intel_aub_annotation *new_annotations = + count > 0 ? realloc(bo_gem->aub_annotations, size) : NULL; + if (new_annotations == NULL) { + free(bo_gem->aub_annotations); + bo_gem->aub_annotations = NULL; + bo_gem->aub_annotation_count = 0; + return; + } + memcpy(new_annotations, annotations, size); + bo_gem->aub_annotations = new_annotations; + bo_gem->aub_annotation_count = count; +} + +/** + * Initializes the GEM buffer manager, which uses the kernel to allocate, map, + * and manage map buffer objections. + * + * \param fd File descriptor of the opened DRM device. + */ +drm_intel_bufmgr * +drm_intel_bufmgr_gem_init(int fd, int batch_size) +{ + drm_intel_bufmgr_gem *bufmgr_gem; + struct drm_i915_gem_get_aperture aperture; + drm_i915_getparam_t gp; + int ret, tmp; + bool exec2 = false; + + bufmgr_gem = calloc(1, sizeof(*bufmgr_gem)); + if (bufmgr_gem == NULL) + return NULL; + + bufmgr_gem->fd = fd; + + if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) { + free(bufmgr_gem); + return NULL; + } + + ret = drmIoctl(bufmgr_gem->fd, + DRM_IOCTL_I915_GEM_GET_APERTURE, + &aperture); + + if (ret == 0) + bufmgr_gem->gtt_size = aperture.aper_available_size; + else { + fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n", + strerror(errno)); + bufmgr_gem->gtt_size = 128 * 1024 * 1024; + fprintf(stderr, "Assuming %dkB available aperture size.\n" + "May lead to reduced performance or incorrect " + "rendering.\n", + (int)bufmgr_gem->gtt_size / 1024); + } + + bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem); + + if (IS_GEN2(bufmgr_gem->pci_device)) + bufmgr_gem->gen = 2; + else if (IS_GEN3(bufmgr_gem->pci_device)) + bufmgr_gem->gen = 3; + else if (IS_GEN4(bufmgr_gem->pci_device)) + bufmgr_gem->gen = 4; + else if (IS_GEN5(bufmgr_gem->pci_device)) + bufmgr_gem->gen = 5; + else if (IS_GEN6(bufmgr_gem->pci_device)) + bufmgr_gem->gen = 6; + else if (IS_GEN7(bufmgr_gem->pci_device)) + bufmgr_gem->gen = 7; + else + assert(0); + + if (IS_GEN3(bufmgr_gem->pci_device) && + bufmgr_gem->gtt_size > 256*1024*1024) { + /* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't + * be used for tiled blits. To simplify the accounting, just + * substract the unmappable part (fixed to 256MB on all known + * gen3 devices) if the kernel advertises it. */ + bufmgr_gem->gtt_size -= 256*1024*1024; + } + + VG_CLEAR(gp); + gp.value = &tmp; + + gp.param = I915_PARAM_HAS_EXECBUF2; + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); + if (!ret) + exec2 = true; + + gp.param = I915_PARAM_HAS_BSD; + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); + bufmgr_gem->has_bsd = ret == 0; + + gp.param = I915_PARAM_HAS_BLT; + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); + bufmgr_gem->has_blt = ret == 0; + + gp.param = I915_PARAM_HAS_RELAXED_FENCING; + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); + bufmgr_gem->has_relaxed_fencing = ret == 0; + + gp.param = I915_PARAM_HAS_LLC; + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); + if (ret != 0) { + /* Kernel does not supports HAS_LLC query, fallback to GPU + * generation detection and assume that we have LLC on GEN6/7 + */ + bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) | + IS_GEN7(bufmgr_gem->pci_device)); + } else + bufmgr_gem->has_llc = ret == 0; + + if (bufmgr_gem->gen < 4) { + gp.param = I915_PARAM_NUM_FENCES_AVAIL; + gp.value = &bufmgr_gem->available_fences; + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); + if (ret) { + fprintf(stderr, "get fences failed: %d [%d]\n", ret, + errno); + fprintf(stderr, "param: %d, val: %d\n", gp.param, + *gp.value); + bufmgr_gem->available_fences = 0; + } else { + /* XXX The kernel reports the total number of fences, + * including any that may be pinned. + * + * We presume that there will be at least one pinned + * fence for the scanout buffer, but there may be more + * than one scanout and the user may be manually + * pinning buffers. Let's move to execbuffer2 and + * thereby forget the insanity of using fences... + */ + bufmgr_gem->available_fences -= 2; + if (bufmgr_gem->available_fences < 0) + bufmgr_gem->available_fences = 0; + } + } + + /* Let's go with one relocation per every 2 dwords (but round down a bit + * since a power of two will mean an extra page allocation for the reloc + * buffer). + * + * Every 4 was too few for the blender benchmark. + */ + bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2; + + bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc; + bufmgr_gem->bufmgr.bo_alloc_for_render = + drm_intel_gem_bo_alloc_for_render; + bufmgr_gem->bufmgr.bo_alloc_tiled = drm_intel_gem_bo_alloc_tiled; + bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference; + bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference; + bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map; + bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap; + bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata; + bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata; + bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering; + bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc; + bufmgr_gem->bufmgr.bo_emit_reloc_fence = drm_intel_gem_bo_emit_reloc_fence; + bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin; + bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin; + bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling; + bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling; + bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink; + /* Use the new one if available */ + if (exec2) { + bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec2; + bufmgr_gem->bufmgr.bo_mrb_exec = drm_intel_gem_bo_mrb_exec2; + } else + bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec; + bufmgr_gem->bufmgr.bo_busy = drm_intel_gem_bo_busy; + bufmgr_gem->bufmgr.bo_madvise = drm_intel_gem_bo_madvise; + bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy; + bufmgr_gem->bufmgr.debug = 0; + bufmgr_gem->bufmgr.check_aperture_space = + drm_intel_gem_check_aperture_space; + bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse; + bufmgr_gem->bufmgr.bo_is_reusable = drm_intel_gem_bo_is_reusable; + bufmgr_gem->bufmgr.get_pipe_from_crtc_id = + drm_intel_gem_get_pipe_from_crtc_id; + bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references; + + DRMINITLISTHEAD(&bufmgr_gem->named); + init_cache_buckets(bufmgr_gem); + + DRMINITLISTHEAD(&bufmgr_gem->vma_cache); + bufmgr_gem->vma_max = -1; /* unlimited by default */ + + return &bufmgr_gem->bufmgr; +} diff --git a/intel/intel_bufmgr_priv.h b/intel/intel_bufmgr_priv.h new file mode 100644 index 0000000..0b62520 --- /dev/null +++ b/intel/intel_bufmgr_priv.h @@ -0,0 +1,287 @@ +/* + * Copyright © 2008 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +/** + * @file intel_bufmgr_priv.h + * + * Private definitions of Intel-specific bufmgr functions and structures. + */ + +#ifndef INTEL_BUFMGR_PRIV_H +#define INTEL_BUFMGR_PRIV_H + +/** + * Context for a buffer manager instance. + * + * Contains public methods followed by private storage for the buffer manager. + */ +struct _drm_intel_bufmgr { + /** + * Allocate a buffer object. + * + * Buffer objects are not necessarily initially mapped into CPU virtual + * address space or graphics device aperture. They must be mapped + * using bo_map() or drm_intel_gem_bo_map_gtt() to be used by the CPU. + */ + drm_intel_bo *(*bo_alloc) (drm_intel_bufmgr *bufmgr, const char *name, + unsigned long size, unsigned int alignment); + + /** + * Allocate a buffer object, hinting that it will be used as a + * render target. + * + * This is otherwise the same as bo_alloc. + */ + drm_intel_bo *(*bo_alloc_for_render) (drm_intel_bufmgr *bufmgr, + const char *name, + unsigned long size, + unsigned int alignment); + + /** + * Allocate a tiled buffer object. + * + * Alignment for tiled objects is set automatically; the 'flags' + * argument provides a hint about how the object will be used initially. + * + * Valid tiling formats are: + * I915_TILING_NONE + * I915_TILING_X + * I915_TILING_Y + * + * Note the tiling format may be rejected; callers should check the + * 'tiling_mode' field on return, as well as the pitch value, which + * may have been rounded up to accommodate for tiling restrictions. + */ + drm_intel_bo *(*bo_alloc_tiled) (drm_intel_bufmgr *bufmgr, + const char *name, + int x, int y, int cpp, + uint32_t *tiling_mode, + unsigned long *pitch, + unsigned long flags); + + /** Takes a reference on a buffer object */ + void (*bo_reference) (drm_intel_bo *bo); + + /** + * Releases a reference on a buffer object, freeing the data if + * no references remain. + */ + void (*bo_unreference) (drm_intel_bo *bo); + + /** + * Maps the buffer into userspace. + * + * This function will block waiting for any existing execution on the + * buffer to complete, first. The resulting mapping is available at + * buf->virtual. + */ + int (*bo_map) (drm_intel_bo *bo, int write_enable); + + /** + * Reduces the refcount on the userspace mapping of the buffer + * object. + */ + int (*bo_unmap) (drm_intel_bo *bo); + + /** + * Write data into an object. + * + * This is an optional function, if missing, + * drm_intel_bo will map/memcpy/unmap. + */ + int (*bo_subdata) (drm_intel_bo *bo, unsigned long offset, + unsigned long size, const void *data); + + /** + * Read data from an object + * + * This is an optional function, if missing, + * drm_intel_bo will map/memcpy/unmap. + */ + int (*bo_get_subdata) (drm_intel_bo *bo, unsigned long offset, + unsigned long size, void *data); + + /** + * Waits for rendering to an object by the GPU to have completed. + * + * This is not required for any access to the BO by bo_map, + * bo_subdata, etc. It is merely a way for the driver to implement + * glFinish. + */ + void (*bo_wait_rendering) (drm_intel_bo *bo); + + /** + * Tears down the buffer manager instance. + */ + void (*destroy) (drm_intel_bufmgr *bufmgr); + + /** + * Add relocation entry in reloc_buf, which will be updated with the + * target buffer's real offset on on command submission. + * + * Relocations remain in place for the lifetime of the buffer object. + * + * \param bo Buffer to write the relocation into. + * \param offset Byte offset within reloc_bo of the pointer to + * target_bo. + * \param target_bo Buffer whose offset should be written into the + * relocation entry. + * \param target_offset Constant value to be added to target_bo's + * offset in relocation entry. + * \param read_domains GEM read domains which the buffer will be + * read into by the command that this relocation + * is part of. + * \param write_domains GEM read domains which the buffer will be + * dirtied in by the command that this + * relocation is part of. + */ + int (*bo_emit_reloc) (drm_intel_bo *bo, uint32_t offset, + drm_intel_bo *target_bo, uint32_t target_offset, + uint32_t read_domains, uint32_t write_domain); + int (*bo_emit_reloc_fence)(drm_intel_bo *bo, uint32_t offset, + drm_intel_bo *target_bo, + uint32_t target_offset, + uint32_t read_domains, + uint32_t write_domain); + + /** Executes the command buffer pointed to by bo. */ + int (*bo_exec) (drm_intel_bo *bo, int used, + drm_clip_rect_t *cliprects, int num_cliprects, + int DR4); + + /** Executes the command buffer pointed to by bo on the selected + * ring buffer + */ + int (*bo_mrb_exec) (drm_intel_bo *bo, int used, + drm_clip_rect_t *cliprects, int num_cliprects, + int DR4, unsigned flags); + + /** + * Pin a buffer to the aperture and fix the offset until unpinned + * + * \param buf Buffer to pin + * \param alignment Required alignment for aperture, in bytes + */ + int (*bo_pin) (drm_intel_bo *bo, uint32_t alignment); + + /** + * Unpin a buffer from the aperture, allowing it to be removed + * + * \param buf Buffer to unpin + */ + int (*bo_unpin) (drm_intel_bo *bo); + + /** + * Ask that the buffer be placed in tiling mode + * + * \param buf Buffer to set tiling mode for + * \param tiling_mode desired, and returned tiling mode + */ + int (*bo_set_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode, + uint32_t stride); + + /** + * Get the current tiling (and resulting swizzling) mode for the bo. + * + * \param buf Buffer to get tiling mode for + * \param tiling_mode returned tiling mode + * \param swizzle_mode returned swizzling mode + */ + int (*bo_get_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode, + uint32_t * swizzle_mode); + + /** + * Create a visible name for a buffer which can be used by other apps + * + * \param buf Buffer to create a name for + * \param name Returned name + */ + int (*bo_flink) (drm_intel_bo *bo, uint32_t * name); + + /** + * Returns 1 if mapping the buffer for write could cause the process + * to block, due to the object being active in the GPU. + */ + int (*bo_busy) (drm_intel_bo *bo); + + /** + * Specify the volatility of the buffer. + * \param bo Buffer to create a name for + * \param madv The purgeable status + * + * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be + * reclaimed under memory pressure. If you subsequently require the buffer, + * then you must pass I915_MADV_WILLNEED to mark the buffer as required. + * + * Returns 1 if the buffer was retained, or 0 if it was discarded whilst + * marked as I915_MADV_DONTNEED. + */ + int (*bo_madvise) (drm_intel_bo *bo, int madv); + + int (*check_aperture_space) (drm_intel_bo ** bo_array, int count); + + /** + * Disable buffer reuse for buffers which will be shared in some way, + * as with scanout buffers. When the buffer reference count goes to + * zero, it will be freed and not placed in the reuse list. + * + * \param bo Buffer to disable reuse for + */ + int (*bo_disable_reuse) (drm_intel_bo *bo); + + /** + * Query whether a buffer is reusable. + * + * \param bo Buffer to query + */ + int (*bo_is_reusable) (drm_intel_bo *bo); + + /** + * + * Return the pipe associated with a crtc_id so that vblank + * synchronization can use the correct data in the request. + * This is only supported for KMS and gem at this point, when + * unsupported, this function returns -1 and leaves the decision + * of what to do in that case to the caller + * + * \param bufmgr the associated buffer manager + * \param crtc_id the crtc identifier + */ + int (*get_pipe_from_crtc_id) (drm_intel_bufmgr *bufmgr, int crtc_id); + + /** Returns true if target_bo is in the relocation tree rooted at bo. */ + int (*bo_references) (drm_intel_bo *bo, drm_intel_bo *target_bo); + + /**< Enables verbose debugging printouts */ + int debug; +}; + +#define ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1)) +#define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y)) +#define ROUND_UP_TO_MB(x) ROUND_UP_TO((x), 1024*1024) + +#endif /* INTEL_BUFMGR_PRIV_H */ diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h new file mode 100644 index 0000000..9c1abc8 --- /dev/null +++ b/intel/intel_chipset.h @@ -0,0 +1,157 @@ +/* + * + * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _INTEL_CHIPSET_H +#define _INTEL_CHIPSET_H + +#define PCI_CHIP_ILD_G 0x0042 +#define PCI_CHIP_ILM_G 0x0046 + +#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */ +#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 +#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 +#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */ +#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 +#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 +#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */ + +#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */ +#define PCI_CHIP_IVYBRIDGE_GT2 0x0162 +#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */ +#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 +#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */ +#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */ + +#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ +#define PCI_CHIP_HASWELL_GT2 0x0412 +#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ +#define PCI_CHIP_HASWELL_M_GT2 0x0416 +#define PCI_CHIP_HASWELL_M_ULT_GT2 0x0A16 /* Mobile ULT */ + +#define IS_830(dev) (dev == 0x3577) +#define IS_845(dev) (dev == 0x2562) +#define IS_85X(dev) (dev == 0x3582) +#define IS_865(dev) (dev == 0x2572) + +#define IS_GEN2(dev) (IS_830(dev) || \ + IS_845(dev) || \ + IS_85X(dev) || \ + IS_865(dev)) + +#define IS_915G(dev) (dev == 0x2582 || \ + dev == 0x258a) +#define IS_915GM(dev) (dev == 0x2592) +#define IS_945G(dev) (dev == 0x2772) +#define IS_945GM(dev) (dev == 0x27A2 || \ + dev == 0x27AE) + +#define IS_915(dev) (IS_915G(dev) || \ + IS_915GM(dev)) + +#define IS_945(dev) (IS_945G(dev) || \ + IS_945GM(dev) || \ + IS_G33(dev) || \ + IS_PINEVIEW(dev)) + +#define IS_G33(dev) (dev == 0x29C2 || \ + dev == 0x29B2 || \ + dev == 0x29D2) + +#define IS_PINEVIEW(dev) (dev == 0xa001 || \ + dev == 0xa011) + +#define IS_GEN3(dev) (IS_915(dev) || \ + IS_945(dev) || \ + IS_G33(dev) || \ + IS_PINEVIEW(dev)) + +#define IS_I965GM(dev) (dev == 0x2A02) + +#define IS_GEN4(dev) (dev == 0x2972 || \ + dev == 0x2982 || \ + dev == 0x2992 || \ + dev == 0x29A2 || \ + dev == 0x2A02 || \ + dev == 0x2A12 || \ + dev == 0x2A42 || \ + dev == 0x2E02 || \ + dev == 0x2E12 || \ + dev == 0x2E22 || \ + dev == 0x2E32 || \ + dev == 0x2E42 || \ + dev == 0x0042 || \ + dev == 0x0046 || \ + IS_I965GM(dev) || \ + IS_G4X(dev)) + +#define IS_GM45(dev) (dev == 0x2A42) + + +#define IS_GEN5(dev) (dev == PCI_CHIP_ILD_G || \ + dev == PCI_CHIP_ILM_G) + +#define IS_GEN6(dev) (dev == PCI_CHIP_SANDYBRIDGE_GT1 || \ + dev == PCI_CHIP_SANDYBRIDGE_GT2 || \ + dev == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \ + dev == PCI_CHIP_SANDYBRIDGE_M_GT1 || \ + dev == PCI_CHIP_SANDYBRIDGE_M_GT2 || \ + dev == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \ + dev == PCI_CHIP_SANDYBRIDGE_S) + +#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ + IS_HASWELL(devid)) + +#define IS_IVYBRIDGE(dev) (dev == PCI_CHIP_IVYBRIDGE_GT1 || \ + dev == PCI_CHIP_IVYBRIDGE_GT2 || \ + dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \ + dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \ + dev == PCI_CHIP_IVYBRIDGE_S || \ + dev == PCI_CHIP_IVYBRIDGE_S_GT2) + +#define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \ + devid == PCI_CHIP_HASWELL_M_GT1) +#define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \ + devid == PCI_CHIP_HASWELL_M_GT2 || \ + devid == PCI_CHIP_HASWELL_M_ULT_GT2) + +#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ + IS_HSW_GT2(devid)) + +#define IS_G4X(dev) (dev == 0x2E02 || \ + dev == 0x2E12 || \ + dev == 0x2E22 || \ + dev == 0x2E32 || \ + dev == 0x2E42 || \ + IS_GM45(dev)) + +#define IS_9XX(dev) (IS_GEN3(dev) || \ + IS_GEN4(dev) || \ + IS_GEN5(dev) || \ + IS_GEN6(dev) || \ + IS_GEN7(dev)) + +#endif /* _INTEL_CHIPSET_H */ diff --git a/intel/intel_debug.h b/intel/intel_debug.h new file mode 100644 index 0000000..fa0737c --- /dev/null +++ b/intel/intel_debug.h @@ -0,0 +1,44 @@ +/* + * Copyright © 2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Ben Widawsky + * + */ + +#ifndef INTEL_DEBUG_H +#define INTEL_DEBUG_H + +#include + +#define SHADER_DEBUG_SOCKET "/var/run/gen_debug" +#define DEBUG_HANDSHAKE_VERSION 0x3 +#define DEBUG_HANDSHAKE_ACK "okay" + +/* First byte must always be the 1 byte version */ +struct intel_debug_handshake { + uint32_t version; + int flink_handle; + uint32_t per_thread_scratch; +} __attribute__((packed)); + +#endif diff --git a/intel/intel_decode.c b/intel/intel_decode.c new file mode 100644 index 0000000..bf23706 --- /dev/null +++ b/intel/intel_decode.c @@ -0,0 +1,3956 @@ +/* + * Copyright © 2009-2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "intel_chipset.h" +#include "intel_bufmgr.h" + +/* Struct for tracking drm_intel_decode state. */ +struct drm_intel_decode { + /** stdio file where the output should land. Defaults to stdout. */ + FILE *out; + + /** PCI device ID. */ + uint32_t devid; + + /** + * Shorthand device identifier: 3 is 915, 4 is 965, 5 is + * Ironlake, etc. + */ + int gen; + + /** GPU address of the start of the current packet. */ + uint32_t hw_offset; + /** CPU virtual address of the start of the current packet. */ + uint32_t *data; + /** DWORDs of remaining batchbuffer data starting from the packet. */ + uint32_t count; + + /** GPU address of the start of the batchbuffer data. */ + uint32_t base_hw_offset; + /** CPU Virtual address of the start of the batchbuffer data. */ + uint32_t *base_data; + /** Number of DWORDs of batchbuffer data. */ + uint32_t base_count; + + /** @{ + * GPU head and tail pointers, which will be noted in the dump, or ~0. + */ + uint32_t head, tail; + /** @} */ + + /** + * Whether to dump the dwords after MI_BATCHBUFFER_END. + * + * This sometimes provides clues in corrupted batchbuffers, + * and is used by the intel-gpu-tools. + */ + bool dump_past_end; + + bool overflowed; +}; + +static FILE *out; +static uint32_t saved_s2 = 0, saved_s4 = 0; +static char saved_s2_set = 0, saved_s4_set = 0; +static uint32_t head_offset = 0xffffffff; /* undefined */ +static uint32_t tail_offset = 0xffffffff; /* undefined */ + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(A) (sizeof(A)/sizeof(A[0])) +#endif + +#define BUFFER_FAIL(_count, _len, _name) do { \ + fprintf(out, "Buffer size too small in %s (%d < %d)\n", \ + (_name), (_count), (_len)); \ + return _count; \ +} while (0) + +static float int_as_float(uint32_t intval) +{ + union intfloat { + uint32_t i; + float f; + } uval; + + uval.i = intval; + return uval.f; +} + +static void +instr_out(struct drm_intel_decode *ctx, unsigned int index, + const char *fmt, ...) __attribute__((format(__printf__, 3, 4))); + +static void +instr_out(struct drm_intel_decode *ctx, unsigned int index, + const char *fmt, ...) +{ + va_list va; + const char *parseinfo; + uint32_t offset = ctx->hw_offset + index * 4; + + if (index > ctx->count) { + if (!ctx->overflowed) { + fprintf(out, "ERROR: Decode attempted to continue beyond end of batchbuffer\n"); + ctx->overflowed = true; + } + return; + } + + if (offset == head_offset) + parseinfo = "HEAD"; + else if (offset == tail_offset) + parseinfo = "TAIL"; + else + parseinfo = " "; + + fprintf(out, "0x%08x: %s 0x%08x: %s", offset, parseinfo, + ctx->data[index], index == 0 ? "" : " "); + va_start(va, fmt); + vfprintf(out, fmt, va); + va_end(va); +} + +static int +decode_MI_WAIT_FOR_EVENT(struct drm_intel_decode *ctx) +{ + const char *cc_wait; + int cc_shift = 0; + uint32_t data = ctx->data[0]; + + if (ctx->gen <= 5) + cc_shift = 9; + else + cc_shift = 16; + + switch ((data >> cc_shift) & 0x1f) { + case 1: + cc_wait = ", cc wait 1"; + break; + case 2: + cc_wait = ", cc wait 2"; + break; + case 3: + cc_wait = ", cc wait 3"; + break; + case 4: + cc_wait = ", cc wait 4"; + break; + case 5: + cc_wait = ", cc wait 4"; + break; + default: + cc_wait = ""; + break; + } + + if (ctx->gen <= 5) { + instr_out(ctx, 0, "MI_WAIT_FOR_EVENT%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", + data & (1<<18)? ", pipe B start vblank wait": "", + data & (1<<17)? ", pipe A start vblank wait": "", + data & (1<<16)? ", overlay flip pending wait": "", + data & (1<<14)? ", pipe B hblank wait": "", + data & (1<<13)? ", pipe A hblank wait": "", + cc_wait, + data & (1<<8)? ", plane C pending flip wait": "", + data & (1<<7)? ", pipe B vblank wait": "", + data & (1<<6)? ", plane B pending flip wait": "", + data & (1<<5)? ", pipe B scan line wait": "", + data & (1<<4)? ", fbc idle wait": "", + data & (1<<3)? ", pipe A vblank wait": "", + data & (1<<2)? ", plane A pending flip wait": "", + data & (1<<1)? ", plane A scan line wait": ""); + } else { + instr_out(ctx, 0, "MI_WAIT_FOR_EVENT%s%s%s%s%s%s%s%s%s%s%s%s\n", + data & (1<<20)? ", sprite C pending flip wait": "", /* ivb */ + cc_wait, + data & (1<<13)? ", pipe B hblank wait": "", + data & (1<<11)? ", pipe B vblank wait": "", + data & (1<<10)? ", sprite B pending flip wait": "", + data & (1<<9)? ", plane B pending flip wait": "", + data & (1<<8)? ", plane B scan line wait": "", + data & (1<<5)? ", pipe A hblank wait": "", + data & (1<<3)? ", pipe A vblank wait": "", + data & (1<<2)? ", sprite A pending flip wait": "", + data & (1<<1)? ", plane A pending flip wait": "", + data & (1<<0)? ", plane A scan line wait": ""); + } + + return 1; +} + +static int +decode_mi(struct drm_intel_decode *ctx) +{ + unsigned int opcode, len = -1; + const char *post_sync_op = ""; + uint32_t *data = ctx->data; + + struct { + uint32_t opcode; + int len_mask; + unsigned int min_len; + unsigned int max_len; + const char *name; + int (*func)(struct drm_intel_decode *ctx); + } opcodes_mi[] = { + { 0x08, 0, 1, 1, "MI_ARB_ON_OFF" }, + { 0x0a, 0, 1, 1, "MI_BATCH_BUFFER_END" }, + { 0x30, 0x3f, 3, 3, "MI_BATCH_BUFFER" }, + { 0x31, 0x3f, 2, 2, "MI_BATCH_BUFFER_START" }, + { 0x14, 0x3f, 3, 3, "MI_DISPLAY_BUFFER_INFO" }, + { 0x04, 0, 1, 1, "MI_FLUSH" }, + { 0x22, 0x1f, 3, 3, "MI_LOAD_REGISTER_IMM" }, + { 0x13, 0x3f, 2, 2, "MI_LOAD_SCAN_LINES_EXCL" }, + { 0x12, 0x3f, 2, 2, "MI_LOAD_SCAN_LINES_INCL" }, + { 0x00, 0, 1, 1, "MI_NOOP" }, + { 0x11, 0x3f, 2, 2, "MI_OVERLAY_FLIP" }, + { 0x07, 0, 1, 1, "MI_REPORT_HEAD" }, + { 0x18, 0x3f, 2, 2, "MI_SET_CONTEXT" }, + { 0x20, 0x3f, 3, 4, "MI_STORE_DATA_IMM" }, + { 0x21, 0x3f, 3, 4, "MI_STORE_DATA_INDEX" }, + { 0x24, 0x3f, 3, 3, "MI_STORE_REGISTER_MEM" }, + { 0x02, 0, 1, 1, "MI_USER_INTERRUPT" }, + { 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT", decode_MI_WAIT_FOR_EVENT }, + { 0x16, 0x7f, 3, 3, "MI_SEMAPHORE_MBOX" }, + { 0x26, 0x1f, 3, 4, "MI_FLUSH_DW" }, + { 0x0b, 0, 1, 1, "MI_SUSPEND_FLUSH"}, + }, *opcode_mi = NULL; + + /* check instruction length */ + for (opcode = 0; opcode < sizeof(opcodes_mi) / sizeof(opcodes_mi[0]); + opcode++) { + if ((data[0] & 0x1f800000) >> 23 == opcodes_mi[opcode].opcode) { + len = 1; + if (opcodes_mi[opcode].max_len > 1) { + len = + (data[0] & opcodes_mi[opcode].len_mask) + 2; + if (len < opcodes_mi[opcode].min_len + || len > opcodes_mi[opcode].max_len) { + fprintf(out, + "Bad length (%d) in %s, [%d, %d]\n", + len, opcodes_mi[opcode].name, + opcodes_mi[opcode].min_len, + opcodes_mi[opcode].max_len); + } + } + opcode_mi = &opcodes_mi[opcode]; + break; + } + } + + if (opcode_mi && opcode_mi->func) + return opcode_mi->func(ctx); + + switch ((data[0] & 0x1f800000) >> 23) { + case 0x0a: + instr_out(ctx, 0, "MI_BATCH_BUFFER_END\n"); + return -1; + case 0x16: + instr_out(ctx, 0, "MI_SEMAPHORE_MBOX%s%s%s%s %u\n", + data[0] & (1 << 22) ? " global gtt," : "", + data[0] & (1 << 21) ? " update semaphore," : "", + data[0] & (1 << 20) ? " compare semaphore," : "", + data[0] & (1 << 18) ? " use compare reg" : "", + (data[0] & (0x3 << 16)) >> 16); + instr_out(ctx, 1, "value\n"); + instr_out(ctx, 2, "address\n"); + return len; + case 0x21: + instr_out(ctx, 0, "MI_STORE_DATA_INDEX%s\n", + data[0] & (1 << 21) ? " use per-process HWS," : ""); + instr_out(ctx, 1, "index\n"); + instr_out(ctx, 2, "dword\n"); + if (len == 4) + instr_out(ctx, 3, "upper dword\n"); + return len; + case 0x00: + if (data[0] & (1 << 22)) + instr_out(ctx, 0, + "MI_NOOP write NOPID reg, val=0x%x\n", + data[0] & ((1 << 22) - 1)); + else + instr_out(ctx, 0, "MI_NOOP\n"); + return len; + case 0x26: + switch (data[0] & (0x3 << 14)) { + case (0 << 14): + post_sync_op = "no write"; + break; + case (1 << 14): + post_sync_op = "write data"; + break; + case (2 << 14): + post_sync_op = "reserved"; + break; + case (3 << 14): + post_sync_op = "write TIMESTAMP"; + break; + } + instr_out(ctx, 0, + "MI_FLUSH_DW%s%s%s%s post_sync_op='%s' %s%s\n", + data[0] & (1 << 22) ? + " enable protected mem (BCS-only)," : "", + data[0] & (1 << 21) ? " store in hws," : "", + data[0] & (1 << 18) ? " invalidate tlb," : "", + data[0] & (1 << 17) ? " flush gfdt," : "", + post_sync_op, + data[0] & (1 << 8) ? " enable notify interrupt," : "", + data[0] & (1 << 7) ? + " invalidate video state (BCS-only)," : ""); + if (data[0] & (1 << 21)) + instr_out(ctx, 1, "hws index\n"); + else + instr_out(ctx, 1, "address\n"); + instr_out(ctx, 2, "dword\n"); + if (len == 4) + instr_out(ctx, 3, "upper dword\n"); + return len; + } + + for (opcode = 0; opcode < sizeof(opcodes_mi) / sizeof(opcodes_mi[0]); + opcode++) { + if ((data[0] & 0x1f800000) >> 23 == opcodes_mi[opcode].opcode) { + unsigned int i; + + instr_out(ctx, 0, "%s\n", + opcodes_mi[opcode].name); + for (i = 1; i < len; i++) { + instr_out(ctx, i, "dword %d\n", i); + } + + return len; + } + } + + instr_out(ctx, 0, "MI UNKNOWN\n"); + return 1; +} + +static void +decode_2d_br00(struct drm_intel_decode *ctx, const char *cmd) +{ + instr_out(ctx, 0, + "%s (rgb %sabled, alpha %sabled, src tile %d, dst tile %d)\n", + cmd, + (ctx->data[0] & (1 << 20)) ? "en" : "dis", + (ctx->data[0] & (1 << 21)) ? "en" : "dis", + (ctx->data[0] >> 15) & 1, + (ctx->data[0] >> 11) & 1); +} + +static void +decode_2d_br01(struct drm_intel_decode *ctx) +{ + const char *format; + switch ((ctx->data[1] >> 24) & 0x3) { + case 0: + format = "8"; + break; + case 1: + format = "565"; + break; + case 2: + format = "1555"; + break; + case 3: + format = "8888"; + break; + } + + instr_out(ctx, 1, + "format %s, pitch %d, rop 0x%02x, " + "clipping %sabled, %s%s \n", + format, + (short)(ctx->data[1] & 0xffff), + (ctx->data[1] >> 16) & 0xff, + ctx->data[1] & (1 << 30) ? "en" : "dis", + ctx->data[1] & (1 << 31) ? "solid pattern enabled, " : "", + ctx->data[1] & (1 << 31) ? + "mono pattern transparency enabled, " : ""); + +} + +static int +decode_2d(struct drm_intel_decode *ctx) +{ + unsigned int opcode, len; + uint32_t *data = ctx->data; + + struct { + uint32_t opcode; + unsigned int min_len; + unsigned int max_len; + const char *name; + } opcodes_2d[] = { + { 0x40, 5, 5, "COLOR_BLT" }, + { 0x43, 6, 6, "SRC_COPY_BLT" }, + { 0x01, 8, 8, "XY_SETUP_BLT" }, + { 0x11, 9, 9, "XY_SETUP_MONO_PATTERN_SL_BLT" }, + { 0x03, 3, 3, "XY_SETUP_CLIP_BLT" }, + { 0x24, 2, 2, "XY_PIXEL_BLT" }, + { 0x25, 3, 3, "XY_SCANLINES_BLT" }, + { 0x26, 4, 4, "Y_TEXT_BLT" }, + { 0x31, 5, 134, "XY_TEXT_IMMEDIATE_BLT" }, + { 0x50, 6, 6, "XY_COLOR_BLT" }, + { 0x51, 6, 6, "XY_PAT_BLT" }, + { 0x76, 8, 8, "XY_PAT_CHROMA_BLT" }, + { 0x72, 7, 135, "XY_PAT_BLT_IMMEDIATE" }, + { 0x77, 9, 137, "XY_PAT_CHROMA_BLT_IMMEDIATE" }, + { 0x52, 9, 9, "XY_MONO_PAT_BLT" }, + { 0x59, 7, 7, "XY_MONO_PAT_FIXED_BLT" }, + { 0x53, 8, 8, "XY_SRC_COPY_BLT" }, + { 0x54, 8, 8, "XY_MONO_SRC_COPY_BLT" }, + { 0x71, 9, 137, "XY_MONO_SRC_COPY_IMMEDIATE_BLT" }, + { 0x55, 9, 9, "XY_FULL_BLT" }, + { 0x55, 9, 137, "XY_FULL_IMMEDIATE_PATTERN_BLT" }, + { 0x56, 9, 9, "XY_FULL_MONO_SRC_BLT" }, + { 0x75, 10, 138, "XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT" }, + { 0x57, 12, 12, "XY_FULL_MONO_PATTERN_BLT" }, + { 0x58, 12, 12, "XY_FULL_MONO_PATTERN_MONO_SRC_BLT"}, + }; + + switch ((data[0] & 0x1fc00000) >> 22) { + case 0x25: + instr_out(ctx, 0, + "XY_SCANLINES_BLT (pattern seed (%d, %d), dst tile %d)\n", + (data[0] >> 12) & 0x8, + (data[0] >> 8) & 0x8, (data[0] >> 11) & 1); + + len = (data[0] & 0x000000ff) + 2; + if (len != 3) + fprintf(out, "Bad count in XY_SCANLINES_BLT\n"); + + instr_out(ctx, 1, "dest (%d,%d)\n", + data[1] & 0xffff, data[1] >> 16); + instr_out(ctx, 2, "dest (%d,%d)\n", + data[2] & 0xffff, data[2] >> 16); + return len; + case 0x01: + decode_2d_br00(ctx, "XY_SETUP_BLT"); + + len = (data[0] & 0x000000ff) + 2; + if (len != 8) + fprintf(out, "Bad count in XY_SETUP_BLT\n"); + + decode_2d_br01(ctx); + instr_out(ctx, 2, "cliprect (%d,%d)\n", + data[2] & 0xffff, data[2] >> 16); + instr_out(ctx, 3, "cliprect (%d,%d)\n", + data[3] & 0xffff, data[3] >> 16); + instr_out(ctx, 4, "setup dst offset 0x%08x\n", + data[4]); + instr_out(ctx, 5, "setup background color\n"); + instr_out(ctx, 6, "setup foreground color\n"); + instr_out(ctx, 7, "color pattern offset\n"); + return len; + case 0x03: + decode_2d_br00(ctx, "XY_SETUP_CLIP_BLT"); + + len = (data[0] & 0x000000ff) + 2; + if (len != 3) + fprintf(out, "Bad count in XY_SETUP_CLIP_BLT\n"); + + instr_out(ctx, 1, "cliprect (%d,%d)\n", + data[1] & 0xffff, data[2] >> 16); + instr_out(ctx, 2, "cliprect (%d,%d)\n", + data[2] & 0xffff, data[3] >> 16); + return len; + case 0x11: + decode_2d_br00(ctx, "XY_SETUP_MONO_PATTERN_SL_BLT"); + + len = (data[0] & 0x000000ff) + 2; + if (len != 9) + fprintf(out, + "Bad count in XY_SETUP_MONO_PATTERN_SL_BLT\n"); + + decode_2d_br01(ctx); + instr_out(ctx, 2, "cliprect (%d,%d)\n", + data[2] & 0xffff, data[2] >> 16); + instr_out(ctx, 3, "cliprect (%d,%d)\n", + data[3] & 0xffff, data[3] >> 16); + instr_out(ctx, 4, "setup dst offset 0x%08x\n", + data[4]); + instr_out(ctx, 5, "setup background color\n"); + instr_out(ctx, 6, "setup foreground color\n"); + instr_out(ctx, 7, "mono pattern dw0\n"); + instr_out(ctx, 8, "mono pattern dw1\n"); + return len; + case 0x50: + decode_2d_br00(ctx, "XY_COLOR_BLT"); + + len = (data[0] & 0x000000ff) + 2; + if (len != 6) + fprintf(out, "Bad count in XY_COLOR_BLT\n"); + + decode_2d_br01(ctx); + instr_out(ctx, 2, "(%d,%d)\n", + data[2] & 0xffff, data[2] >> 16); + instr_out(ctx, 3, "(%d,%d)\n", + data[3] & 0xffff, data[3] >> 16); + instr_out(ctx, 4, "offset 0x%08x\n", data[4]); + instr_out(ctx, 5, "color\n"); + return len; + case 0x53: + decode_2d_br00(ctx, "XY_SRC_COPY_BLT"); + + len = (data[0] & 0x000000ff) + 2; + if (len != 8) + fprintf(out, "Bad count in XY_SRC_COPY_BLT\n"); + + decode_2d_br01(ctx); + instr_out(ctx, 2, "dst (%d,%d)\n", + data[2] & 0xffff, data[2] >> 16); + instr_out(ctx, 3, "dst (%d,%d)\n", + data[3] & 0xffff, data[3] >> 16); + instr_out(ctx, 4, "dst offset 0x%08x\n", data[4]); + instr_out(ctx, 5, "src (%d,%d)\n", + data[5] & 0xffff, data[5] >> 16); + instr_out(ctx, 6, "src pitch %d\n", + (short)(data[6] & 0xffff)); + instr_out(ctx, 7, "src offset 0x%08x\n", data[7]); + return len; + } + + for (opcode = 0; opcode < sizeof(opcodes_2d) / sizeof(opcodes_2d[0]); + opcode++) { + if ((data[0] & 0x1fc00000) >> 22 == opcodes_2d[opcode].opcode) { + unsigned int i; + + len = 1; + instr_out(ctx, 0, "%s\n", + opcodes_2d[opcode].name); + if (opcodes_2d[opcode].max_len > 1) { + len = (data[0] & 0x000000ff) + 2; + if (len < opcodes_2d[opcode].min_len || + len > opcodes_2d[opcode].max_len) { + fprintf(out, "Bad count in %s\n", + opcodes_2d[opcode].name); + } + } + + for (i = 1; i < len; i++) { + instr_out(ctx, i, "dword %d\n", i); + } + + return len; + } + } + + instr_out(ctx, 0, "2D UNKNOWN\n"); + return 1; +} + +static int +decode_3d_1c(struct drm_intel_decode *ctx) +{ + uint32_t *data = ctx->data; + uint32_t opcode; + + opcode = (data[0] & 0x00f80000) >> 19; + + switch (opcode) { + case 0x11: + instr_out(ctx, 0, + "3DSTATE_DEPTH_SUBRECTANGLE_DISABLE\n"); + return 1; + case 0x10: + instr_out(ctx, 0, "3DSTATE_SCISSOR_ENABLE %s\n", + data[0] & 1 ? "enabled" : "disabled"); + return 1; + case 0x01: + instr_out(ctx, 0, "3DSTATE_MAP_COORD_SET_I830\n"); + return 1; + case 0x0a: + instr_out(ctx, 0, "3DSTATE_MAP_CUBE_I830\n"); + return 1; + case 0x05: + instr_out(ctx, 0, "3DSTATE_MAP_TEX_STREAM_I830\n"); + return 1; + } + + instr_out(ctx, 0, "3D UNKNOWN: 3d_1c opcode = 0x%x\n", + opcode); + return 1; +} + +/** Sets the string dstname to describe the destination of the PS instruction */ +static void +i915_get_instruction_dst(uint32_t *data, int i, char *dstname, int do_mask) +{ + uint32_t a0 = data[i]; + int dst_nr = (a0 >> 14) & 0xf; + char dstmask[8]; + const char *sat; + + if (do_mask) { + if (((a0 >> 10) & 0xf) == 0xf) { + dstmask[0] = 0; + } else { + int dstmask_index = 0; + + dstmask[dstmask_index++] = '.'; + if (a0 & (1 << 10)) + dstmask[dstmask_index++] = 'x'; + if (a0 & (1 << 11)) + dstmask[dstmask_index++] = 'y'; + if (a0 & (1 << 12)) + dstmask[dstmask_index++] = 'z'; + if (a0 & (1 << 13)) + dstmask[dstmask_index++] = 'w'; + dstmask[dstmask_index++] = 0; + } + + if (a0 & (1 << 22)) + sat = ".sat"; + else + sat = ""; + } else { + dstmask[0] = 0; + sat = ""; + } + + switch ((a0 >> 19) & 0x7) { + case 0: + if (dst_nr > 15) + fprintf(out, "bad destination reg R%d\n", dst_nr); + sprintf(dstname, "R%d%s%s", dst_nr, dstmask, sat); + break; + case 4: + if (dst_nr > 0) + fprintf(out, "bad destination reg oC%d\n", dst_nr); + sprintf(dstname, "oC%s%s", dstmask, sat); + break; + case 5: + if (dst_nr > 0) + fprintf(out, "bad destination reg oD%d\n", dst_nr); + sprintf(dstname, "oD%s%s", dstmask, sat); + break; + case 6: + if (dst_nr > 3) + fprintf(out, "bad destination reg U%d\n", dst_nr); + sprintf(dstname, "U%d%s%s", dst_nr, dstmask, sat); + break; + default: + sprintf(dstname, "RESERVED"); + break; + } +} + +static const char * +i915_get_channel_swizzle(uint32_t select) +{ + switch (select & 0x7) { + case 0: + return (select & 8) ? "-x" : "x"; + case 1: + return (select & 8) ? "-y" : "y"; + case 2: + return (select & 8) ? "-z" : "z"; + case 3: + return (select & 8) ? "-w" : "w"; + case 4: + return (select & 8) ? "-0" : "0"; + case 5: + return (select & 8) ? "-1" : "1"; + default: + return (select & 8) ? "-bad" : "bad"; + } +} + +static void +i915_get_instruction_src_name(uint32_t src_type, uint32_t src_nr, char *name) +{ + switch (src_type) { + case 0: + sprintf(name, "R%d", src_nr); + if (src_nr > 15) + fprintf(out, "bad src reg %s\n", name); + break; + case 1: + if (src_nr < 8) + sprintf(name, "T%d", src_nr); + else if (src_nr == 8) + sprintf(name, "DIFFUSE"); + else if (src_nr == 9) + sprintf(name, "SPECULAR"); + else if (src_nr == 10) + sprintf(name, "FOG"); + else { + fprintf(out, "bad src reg T%d\n", src_nr); + sprintf(name, "RESERVED"); + } + break; + case 2: + sprintf(name, "C%d", src_nr); + if (src_nr > 31) + fprintf(out, "bad src reg %s\n", name); + break; + case 4: + sprintf(name, "oC"); + if (src_nr > 0) + fprintf(out, "bad src reg oC%d\n", src_nr); + break; + case 5: + sprintf(name, "oD"); + if (src_nr > 0) + fprintf(out, "bad src reg oD%d\n", src_nr); + break; + case 6: + sprintf(name, "U%d", src_nr); + if (src_nr > 3) + fprintf(out, "bad src reg %s\n", name); + break; + default: + fprintf(out, "bad src reg type %d\n", src_type); + sprintf(name, "RESERVED"); + break; + } +} + +static void i915_get_instruction_src0(uint32_t *data, int i, char *srcname) +{ + uint32_t a0 = data[i]; + uint32_t a1 = data[i + 1]; + int src_nr = (a0 >> 2) & 0x1f; + const char *swizzle_x = i915_get_channel_swizzle((a1 >> 28) & 0xf); + const char *swizzle_y = i915_get_channel_swizzle((a1 >> 24) & 0xf); + const char *swizzle_z = i915_get_channel_swizzle((a1 >> 20) & 0xf); + const char *swizzle_w = i915_get_channel_swizzle((a1 >> 16) & 0xf); + char swizzle[100]; + + i915_get_instruction_src_name((a0 >> 7) & 0x7, src_nr, srcname); + sprintf(swizzle, ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z, + swizzle_w); + if (strcmp(swizzle, ".xyzw") != 0) + strcat(srcname, swizzle); +} + +static void i915_get_instruction_src1(uint32_t *data, int i, char *srcname) +{ + uint32_t a1 = data[i + 1]; + uint32_t a2 = data[i + 2]; + int src_nr = (a1 >> 8) & 0x1f; + const char *swizzle_x = i915_get_channel_swizzle((a1 >> 4) & 0xf); + const char *swizzle_y = i915_get_channel_swizzle((a1 >> 0) & 0xf); + const char *swizzle_z = i915_get_channel_swizzle((a2 >> 28) & 0xf); + const char *swizzle_w = i915_get_channel_swizzle((a2 >> 24) & 0xf); + char swizzle[100]; + + i915_get_instruction_src_name((a1 >> 13) & 0x7, src_nr, srcname); + sprintf(swizzle, ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z, + swizzle_w); + if (strcmp(swizzle, ".xyzw") != 0) + strcat(srcname, swizzle); +} + +static void i915_get_instruction_src2(uint32_t *data, int i, char *srcname) +{ + uint32_t a2 = data[i + 2]; + int src_nr = (a2 >> 16) & 0x1f; + const char *swizzle_x = i915_get_channel_swizzle((a2 >> 12) & 0xf); + const char *swizzle_y = i915_get_channel_swizzle((a2 >> 8) & 0xf); + const char *swizzle_z = i915_get_channel_swizzle((a2 >> 4) & 0xf); + const char *swizzle_w = i915_get_channel_swizzle((a2 >> 0) & 0xf); + char swizzle[100]; + + i915_get_instruction_src_name((a2 >> 21) & 0x7, src_nr, srcname); + sprintf(swizzle, ".%s%s%s%s", swizzle_x, swizzle_y, swizzle_z, + swizzle_w); + if (strcmp(swizzle, ".xyzw") != 0) + strcat(srcname, swizzle); +} + +static void +i915_get_instruction_addr(uint32_t src_type, uint32_t src_nr, char *name) +{ + switch (src_type) { + case 0: + sprintf(name, "R%d", src_nr); + if (src_nr > 15) + fprintf(out, "bad src reg %s\n", name); + break; + case 1: + if (src_nr < 8) + sprintf(name, "T%d", src_nr); + else if (src_nr == 8) + sprintf(name, "DIFFUSE"); + else if (src_nr == 9) + sprintf(name, "SPECULAR"); + else if (src_nr == 10) + sprintf(name, "FOG"); + else { + fprintf(out, "bad src reg T%d\n", src_nr); + sprintf(name, "RESERVED"); + } + break; + case 4: + sprintf(name, "oC"); + if (src_nr > 0) + fprintf(out, "bad src reg oC%d\n", src_nr); + break; + case 5: + sprintf(name, "oD"); + if (src_nr > 0) + fprintf(out, "bad src reg oD%d\n", src_nr); + break; + default: + fprintf(out, "bad src reg type %d\n", src_type); + sprintf(name, "RESERVED"); + break; + } +} + +static void +i915_decode_alu1(struct drm_intel_decode *ctx, + int i, char *instr_prefix, const char *op_name) +{ + char dst[100], src0[100]; + + i915_get_instruction_dst(ctx->data, i, dst, 1); + i915_get_instruction_src0(ctx->data, i, src0); + + instr_out(ctx, i++, "%s: %s %s, %s\n", instr_prefix, + op_name, dst, src0); + instr_out(ctx, i++, "%s\n", instr_prefix); + instr_out(ctx, i++, "%s\n", instr_prefix); +} + +static void +i915_decode_alu2(struct drm_intel_decode *ctx, + int i, char *instr_prefix, const char *op_name) +{ + char dst[100], src0[100], src1[100]; + + i915_get_instruction_dst(ctx->data, i, dst, 1); + i915_get_instruction_src0(ctx->data, i, src0); + i915_get_instruction_src1(ctx->data, i, src1); + + instr_out(ctx, i++, "%s: %s %s, %s, %s\n", instr_prefix, + op_name, dst, src0, src1); + instr_out(ctx, i++, "%s\n", instr_prefix); + instr_out(ctx, i++, "%s\n", instr_prefix); +} + +static void +i915_decode_alu3(struct drm_intel_decode *ctx, + int i, char *instr_prefix, const char *op_name) +{ + char dst[100], src0[100], src1[100], src2[100]; + + i915_get_instruction_dst(ctx->data, i, dst, 1); + i915_get_instruction_src0(ctx->data, i, src0); + i915_get_instruction_src1(ctx->data, i, src1); + i915_get_instruction_src2(ctx->data, i, src2); + + instr_out(ctx, i++, "%s: %s %s, %s, %s, %s\n", instr_prefix, + op_name, dst, src0, src1, src2); + instr_out(ctx, i++, "%s\n", instr_prefix); + instr_out(ctx, i++, "%s\n", instr_prefix); +} + +static void +i915_decode_tex(struct drm_intel_decode *ctx, int i, + const char *instr_prefix, const char *tex_name) +{ + uint32_t t0 = ctx->data[i]; + uint32_t t1 = ctx->data[i + 1]; + char dst_name[100]; + char addr_name[100]; + int sampler_nr; + + i915_get_instruction_dst(ctx->data, i, dst_name, 0); + i915_get_instruction_addr((t1 >> 24) & 0x7, + (t1 >> 17) & 0xf, addr_name); + sampler_nr = t0 & 0xf; + + instr_out(ctx, i++, "%s: %s %s, S%d, %s\n", instr_prefix, + tex_name, dst_name, sampler_nr, addr_name); + instr_out(ctx, i++, "%s\n", instr_prefix); + instr_out(ctx, i++, "%s\n", instr_prefix); +} + +static void +i915_decode_dcl(struct drm_intel_decode *ctx, int i, char *instr_prefix) +{ + uint32_t d0 = ctx->data[i]; + const char *sampletype; + int dcl_nr = (d0 >> 14) & 0xf; + const char *dcl_x = d0 & (1 << 10) ? "x" : ""; + const char *dcl_y = d0 & (1 << 11) ? "y" : ""; + const char *dcl_z = d0 & (1 << 12) ? "z" : ""; + const char *dcl_w = d0 & (1 << 13) ? "w" : ""; + char dcl_mask[10]; + + switch ((d0 >> 19) & 0x3) { + case 1: + sprintf(dcl_mask, ".%s%s%s%s", dcl_x, dcl_y, dcl_z, dcl_w); + if (strcmp(dcl_mask, ".") == 0) + fprintf(out, "bad (empty) dcl mask\n"); + + if (dcl_nr > 10) + fprintf(out, "bad T%d dcl register number\n", dcl_nr); + if (dcl_nr < 8) { + if (strcmp(dcl_mask, ".x") != 0 && + strcmp(dcl_mask, ".xy") != 0 && + strcmp(dcl_mask, ".xz") != 0 && + strcmp(dcl_mask, ".w") != 0 && + strcmp(dcl_mask, ".xyzw") != 0) { + fprintf(out, "bad T%d.%s dcl mask\n", dcl_nr, + dcl_mask); + } + instr_out(ctx, i++, "%s: DCL T%d%s\n", + instr_prefix, dcl_nr, dcl_mask); + } else { + if (strcmp(dcl_mask, ".xz") == 0) + fprintf(out, "errataed bad dcl mask %s\n", + dcl_mask); + else if (strcmp(dcl_mask, ".xw") == 0) + fprintf(out, "errataed bad dcl mask %s\n", + dcl_mask); + else if (strcmp(dcl_mask, ".xzw") == 0) + fprintf(out, "errataed bad dcl mask %s\n", + dcl_mask); + + if (dcl_nr == 8) { + instr_out(ctx, i++, + "%s: DCL DIFFUSE%s\n", instr_prefix, + dcl_mask); + } else if (dcl_nr == 9) { + instr_out(ctx, i++, + "%s: DCL SPECULAR%s\n", instr_prefix, + dcl_mask); + } else if (dcl_nr == 10) { + instr_out(ctx, i++, + "%s: DCL FOG%s\n", instr_prefix, + dcl_mask); + } + } + instr_out(ctx, i++, "%s\n", instr_prefix); + instr_out(ctx, i++, "%s\n", instr_prefix); + break; + case 3: + switch ((d0 >> 22) & 0x3) { + case 0: + sampletype = "2D"; + break; + case 1: + sampletype = "CUBE"; + break; + case 2: + sampletype = "3D"; + break; + default: + sampletype = "RESERVED"; + break; + } + if (dcl_nr > 15) + fprintf(out, "bad S%d dcl register number\n", dcl_nr); + instr_out(ctx, i++, "%s: DCL S%d %s\n", + instr_prefix, dcl_nr, sampletype); + instr_out(ctx, i++, "%s\n", instr_prefix); + instr_out(ctx, i++, "%s\n", instr_prefix); + break; + default: + instr_out(ctx, i++, "%s: DCL RESERVED%d\n", + instr_prefix, dcl_nr); + instr_out(ctx, i++, "%s\n", instr_prefix); + instr_out(ctx, i++, "%s\n", instr_prefix); + } +} + +static void +i915_decode_instruction(struct drm_intel_decode *ctx, + int i, char *instr_prefix) +{ + switch ((ctx->data[i] >> 24) & 0x1f) { + case 0x0: + instr_out(ctx, i++, "%s: NOP\n", instr_prefix); + instr_out(ctx, i++, "%s\n", instr_prefix); + instr_out(ctx, i++, "%s\n", instr_prefix); + break; + case 0x01: + i915_decode_alu2(ctx, i, instr_prefix, "ADD"); + break; + case 0x02: + i915_decode_alu1(ctx, i, instr_prefix, "MOV"); + break; + case 0x03: + i915_decode_alu2(ctx, i, instr_prefix, "MUL"); + break; + case 0x04: + i915_decode_alu3(ctx, i, instr_prefix, "MAD"); + break; + case 0x05: + i915_decode_alu3(ctx, i, instr_prefix, "DP2ADD"); + break; + case 0x06: + i915_decode_alu2(ctx, i, instr_prefix, "DP3"); + break; + case 0x07: + i915_decode_alu2(ctx, i, instr_prefix, "DP4"); + break; + case 0x08: + i915_decode_alu1(ctx, i, instr_prefix, "FRC"); + break; + case 0x09: + i915_decode_alu1(ctx, i, instr_prefix, "RCP"); + break; + case 0x0a: + i915_decode_alu1(ctx, i, instr_prefix, "RSQ"); + break; + case 0x0b: + i915_decode_alu1(ctx, i, instr_prefix, "EXP"); + break; + case 0x0c: + i915_decode_alu1(ctx, i, instr_prefix, "LOG"); + break; + case 0x0d: + i915_decode_alu2(ctx, i, instr_prefix, "CMP"); + break; + case 0x0e: + i915_decode_alu2(ctx, i, instr_prefix, "MIN"); + break; + case 0x0f: + i915_decode_alu2(ctx, i, instr_prefix, "MAX"); + break; + case 0x10: + i915_decode_alu1(ctx, i, instr_prefix, "FLR"); + break; + case 0x11: + i915_decode_alu1(ctx, i, instr_prefix, "MOD"); + break; + case 0x12: + i915_decode_alu1(ctx, i, instr_prefix, "TRC"); + break; + case 0x13: + i915_decode_alu2(ctx, i, instr_prefix, "SGE"); + break; + case 0x14: + i915_decode_alu2(ctx, i, instr_prefix, "SLT"); + break; + case 0x15: + i915_decode_tex(ctx, i, instr_prefix, "TEXLD"); + break; + case 0x16: + i915_decode_tex(ctx, i, instr_prefix, "TEXLDP"); + break; + case 0x17: + i915_decode_tex(ctx, i, instr_prefix, "TEXLDB"); + break; + case 0x19: + i915_decode_dcl(ctx, i, instr_prefix); + break; + default: + instr_out(ctx, i++, "%s: unknown\n", instr_prefix); + instr_out(ctx, i++, "%s\n", instr_prefix); + instr_out(ctx, i++, "%s\n", instr_prefix); + break; + } +} + +static const char * +decode_compare_func(uint32_t op) +{ + switch (op & 0x7) { + case 0: + return "always"; + case 1: + return "never"; + case 2: + return "less"; + case 3: + return "equal"; + case 4: + return "lequal"; + case 5: + return "greater"; + case 6: + return "notequal"; + case 7: + return "gequal"; + } + return ""; +} + +static const char * +decode_stencil_op(uint32_t op) +{ + switch (op & 0x7) { + case 0: + return "keep"; + case 1: + return "zero"; + case 2: + return "replace"; + case 3: + return "incr_sat"; + case 4: + return "decr_sat"; + case 5: + return "greater"; + case 6: + return "incr"; + case 7: + return "decr"; + } + return ""; +} + +#if 0 +static const char * +decode_logic_op(uint32_t op) +{ + switch (op & 0xf) { + case 0: + return "clear"; + case 1: + return "nor"; + case 2: + return "and_inv"; + case 3: + return "copy_inv"; + case 4: + return "and_rvrse"; + case 5: + return "inv"; + case 6: + return "xor"; + case 7: + return "nand"; + case 8: + return "and"; + case 9: + return "equiv"; + case 10: + return "noop"; + case 11: + return "or_inv"; + case 12: + return "copy"; + case 13: + return "or_rvrse"; + case 14: + return "or"; + case 15: + return "set"; + } + return ""; +} +#endif + +static const char * +decode_blend_fact(uint32_t op) +{ + switch (op & 0xf) { + case 1: + return "zero"; + case 2: + return "one"; + case 3: + return "src_colr"; + case 4: + return "inv_src_colr"; + case 5: + return "src_alpha"; + case 6: + return "inv_src_alpha"; + case 7: + return "dst_alpha"; + case 8: + return "inv_dst_alpha"; + case 9: + return "dst_colr"; + case 10: + return "inv_dst_colr"; + case 11: + return "src_alpha_sat"; + case 12: + return "cnst_colr"; + case 13: + return "inv_cnst_colr"; + case 14: + return "cnst_alpha"; + case 15: + return "inv_const_alpha"; + } + return ""; +} + +static const char * +decode_tex_coord_mode(uint32_t mode) +{ + switch (mode & 0x7) { + case 0: + return "wrap"; + case 1: + return "mirror"; + case 2: + return "clamp_edge"; + case 3: + return "cube"; + case 4: + return "clamp_border"; + case 5: + return "mirror_once"; + } + return ""; +} + +static const char * +decode_sample_filter(uint32_t mode) +{ + switch (mode & 0x7) { + case 0: + return "nearest"; + case 1: + return "linear"; + case 2: + return "anisotropic"; + case 3: + return "4x4_1"; + case 4: + return "4x4_2"; + case 5: + return "4x4_flat"; + case 6: + return "6x5_mono"; + } + return ""; +} + +static int +decode_3d_1d(struct drm_intel_decode *ctx) +{ + unsigned int len, i, c, idx, word, map, sampler, instr; + const char *format, *zformat, *type; + uint32_t opcode; + uint32_t *data = ctx->data; + uint32_t devid = ctx->devid; + + struct { + uint32_t opcode; + int i830_only; + unsigned int min_len; + unsigned int max_len; + const char *name; + } opcodes_3d_1d[] = { + { 0x86, 0, 4, 4, "3DSTATE_CHROMA_KEY" }, + { 0x88, 0, 2, 2, "3DSTATE_CONSTANT_BLEND_COLOR" }, + { 0x99, 0, 2, 2, "3DSTATE_DEFAULT_DIFFUSE" }, + { 0x9a, 0, 2, 2, "3DSTATE_DEFAULT_SPECULAR" }, + { 0x98, 0, 2, 2, "3DSTATE_DEFAULT_Z" }, + { 0x97, 0, 2, 2, "3DSTATE_DEPTH_OFFSET_SCALE" }, + { 0x9d, 0, 65, 65, "3DSTATE_FILTER_COEFFICIENTS_4X4" }, + { 0x9e, 0, 4, 4, "3DSTATE_MONO_FILTER" }, + { 0x89, 0, 4, 4, "3DSTATE_FOG_MODE" }, + { 0x8f, 0, 2, 16, "3DSTATE_MAP_PALLETE_LOAD_32" }, + { 0x83, 0, 2, 2, "3DSTATE_SPAN_STIPPLE" }, + { 0x8c, 1, 2, 2, "3DSTATE_MAP_COORD_TRANSFORM_I830" }, + { 0x8b, 1, 2, 2, "3DSTATE_MAP_VERTEX_TRANSFORM_I830" }, + { 0x8d, 1, 3, 3, "3DSTATE_W_STATE_I830" }, + { 0x01, 1, 2, 2, "3DSTATE_COLOR_FACTOR_I830" }, + { 0x02, 1, 2, 2, "3DSTATE_MAP_COORD_SETBIND_I830"}, + }, *opcode_3d_1d; + + opcode = (data[0] & 0x00ff0000) >> 16; + + switch (opcode) { + case 0x07: + /* This instruction is unusual. A 0 length means just + * 1 DWORD instead of 2. The 0 length is specified in + * one place to be unsupported, but stated to be + * required in another, and 0 length LOAD_INDIRECTs + * appear to cause no harm at least. + */ + instr_out(ctx, 0, "3DSTATE_LOAD_INDIRECT\n"); + len = (data[0] & 0x000000ff) + 1; + i = 1; + if (data[0] & (0x01 << 8)) { + instr_out(ctx, i++, "SIS.0\n"); + instr_out(ctx, i++, "SIS.1\n"); + } + if (data[0] & (0x02 << 8)) { + instr_out(ctx, i++, "DIS.0\n"); + } + if (data[0] & (0x04 << 8)) { + instr_out(ctx, i++, "SSB.0\n"); + instr_out(ctx, i++, "SSB.1\n"); + } + if (data[0] & (0x08 << 8)) { + instr_out(ctx, i++, "MSB.0\n"); + instr_out(ctx, i++, "MSB.1\n"); + } + if (data[0] & (0x10 << 8)) { + instr_out(ctx, i++, "PSP.0\n"); + instr_out(ctx, i++, "PSP.1\n"); + } + if (data[0] & (0x20 << 8)) { + instr_out(ctx, i++, "PSC.0\n"); + instr_out(ctx, i++, "PSC.1\n"); + } + if (len != i) { + fprintf(out, "Bad count in 3DSTATE_LOAD_INDIRECT\n"); + return len; + } + return len; + case 0x04: + instr_out(ctx, 0, + "3DSTATE_LOAD_STATE_IMMEDIATE_1\n"); + len = (data[0] & 0x0000000f) + 2; + i = 1; + for (word = 0; word <= 8; word++) { + if (data[0] & (1 << (4 + word))) { + /* save vertex state for decode */ + if (!IS_GEN2(devid)) { + int tex_num; + + if (word == 2) { + saved_s2_set = 1; + saved_s2 = data[i]; + } + if (word == 4) { + saved_s4_set = 1; + saved_s4 = data[i]; + } + + switch (word) { + case 0: + instr_out(ctx, i, + "S0: vbo offset: 0x%08x%s\n", + data[i] & (~1), + data[i] & 1 ? + ", auto cache invalidate disabled" + : ""); + break; + case 1: + instr_out(ctx, i, + "S1: vertex width: %i, vertex pitch: %i\n", + (data[i] >> 24) & + 0x3f, + (data[i] >> 16) & + 0x3f); + break; + case 2: + instr_out(ctx, i, + "S2: texcoord formats: "); + for (tex_num = 0; + tex_num < 8; tex_num++) { + switch ((data[i] >> + tex_num * + 4) & 0xf) { + case 0: + fprintf(out, + "%i=2D ", + tex_num); + break; + case 1: + fprintf(out, + "%i=3D ", + tex_num); + break; + case 2: + fprintf(out, + "%i=4D ", + tex_num); + break; + case 3: + fprintf(out, + "%i=1D ", + tex_num); + break; + case 4: + fprintf(out, + "%i=2D_16 ", + tex_num); + break; + case 5: + fprintf(out, + "%i=4D_16 ", + tex_num); + break; + case 0xf: + fprintf(out, + "%i=NP ", + tex_num); + break; + } + } + fprintf(out, "\n"); + + break; + case 3: + instr_out(ctx, i, + "S3: not documented\n"); + break; + case 4: + { + const char *cullmode = ""; + const char *vfmt_xyzw = ""; + switch ((data[i] >> 13) + & 0x3) { + case 0: + cullmode = + "both"; + break; + case 1: + cullmode = + "none"; + break; + case 2: + cullmode = "cw"; + break; + case 3: + cullmode = + "ccw"; + break; + } + switch (data[i] & + (7 << 6 | 1 << + 2)) { + case 1 << 6: + vfmt_xyzw = + "XYZ,"; + break; + case 2 << 6: + vfmt_xyzw = + "XYZW,"; + break; + case 3 << 6: + vfmt_xyzw = + "XY,"; + break; + case 4 << 6: + vfmt_xyzw = + "XYW,"; + break; + case 1 << 6 | 1 << 2: + vfmt_xyzw = + "XYZF,"; + break; + case 2 << 6 | 1 << 2: + vfmt_xyzw = + "XYZWF,"; + break; + case 3 << 6 | 1 << 2: + vfmt_xyzw = + "XYF,"; + break; + case 4 << 6 | 1 << 2: + vfmt_xyzw = + "XYWF,"; + break; + } + instr_out(ctx, i, + "S4: point_width=%i, line_width=%.1f," + "%s%s%s%s%s cullmode=%s, vfmt=%s%s%s%s%s%s " + "%s%s%s%s%s\n", + (data[i] >> + 23) & 0x1ff, + ((data[i] >> + 19) & 0xf) / + 2.0, + data[i] & (0xf + << + 15) + ? + " flatshade=" + : "", + data[i] & (1 + << + 18) + ? "Alpha," : + "", + data[i] & (1 + << + 17) + ? "Fog," : "", + data[i] & (1 + << + 16) + ? "Specular," + : "", + data[i] & (1 + << + 15) + ? "Color," : + "", cullmode, + data[i] & (1 + << + 12) + ? + "PointWidth," + : "", + data[i] & (1 + << + 11) + ? "SpecFog," : + "", + data[i] & (1 + << + 10) + ? "Color," : + "", + data[i] & (1 + << + 9) + ? "DepthOfs," + : "", + vfmt_xyzw, + data[i] & (1 + << + 9) + ? "FogParam," + : "", + data[i] & (1 + << + 5) + ? + "force default diffuse, " + : "", + data[i] & (1 + << + 4) + ? + "force default specular, " + : "", + data[i] & (1 + << + 3) + ? + "local depth ofs enable, " + : "", + data[i] & (1 + << + 1) + ? + "point sprite enable, " + : "", + data[i] & (1 + << + 0) + ? + "line AA enable, " + : ""); + break; + } + case 5: + { + instr_out(ctx, i, + "S5:%s%s%s%s%s" + "%s%s%s%s stencil_ref=0x%x, stencil_test=%s, " + "stencil_fail=%s, stencil_pass_z_fail=%s, " + "stencil_pass_z_pass=%s, %s%s%s%s\n", + data[i] & (0xf + << + 28) + ? + " write_disable=" + : "", + data[i] & (1 + << + 31) + ? "Alpha," : + "", + data[i] & (1 + << + 30) + ? "Red," : "", + data[i] & (1 + << + 29) + ? "Green," : + "", + data[i] & (1 + << + 28) + ? "Blue," : + "", + data[i] & (1 + << + 27) + ? + " force default point size," + : "", + data[i] & (1 + << + 26) + ? + " last pixel enable," + : "", + data[i] & (1 + << + 25) + ? + " global depth ofs enable," + : "", + data[i] & (1 + << + 24) + ? + " fog enable," + : "", + (data[i] >> + 16) & 0xff, + decode_compare_func + (data[i] >> + 13), + decode_stencil_op + (data[i] >> + 10), + decode_stencil_op + (data[i] >> + 7), + decode_stencil_op + (data[i] >> + 4), + data[i] & (1 + << + 3) + ? + "stencil write enable, " + : "", + data[i] & (1 + << + 2) + ? + "stencil test enable, " + : "", + data[i] & (1 + << + 1) + ? + "color dither enable, " + : "", + data[i] & (1 + << + 0) + ? + "logicop enable, " + : ""); + } + break; + case 6: + instr_out(ctx, i, + "S6: %salpha_test=%s, alpha_ref=0x%x, " + "depth_test=%s, %ssrc_blnd_fct=%s, dst_blnd_fct=%s, " + "%s%stristrip_provoking_vertex=%i\n", + data[i] & (1 << 31) ? + "alpha test enable, " + : "", + decode_compare_func + (data[i] >> 28), + data[i] & (0xff << + 20), + decode_compare_func + (data[i] >> 16), + data[i] & (1 << 15) ? + "cbuf blend enable, " + : "", + decode_blend_fact(data + [i] + >> + 8), + decode_blend_fact(data + [i] + >> + 4), + data[i] & (1 << 3) ? + "depth write enable, " + : "", + data[i] & (1 << 2) ? + "cbuf write enable, " + : "", + data[i] & (0x3)); + break; + case 7: + instr_out(ctx, i, + "S7: depth offset constant: 0x%08x\n", + data[i]); + break; + } + } else { + instr_out(ctx, i, + "S%d: 0x%08x\n", i, data[i]); + } + i++; + } + } + if (len != i) { + fprintf(out, + "Bad count in 3DSTATE_LOAD_STATE_IMMEDIATE_1\n"); + } + return len; + case 0x03: + instr_out(ctx, 0, + "3DSTATE_LOAD_STATE_IMMEDIATE_2\n"); + len = (data[0] & 0x0000000f) + 2; + i = 1; + for (word = 6; word <= 14; word++) { + if (data[0] & (1 << word)) { + if (word == 6) + instr_out(ctx, i++, + "TBCF\n"); + else if (word >= 7 && word <= 10) { + instr_out(ctx, i++, + "TB%dC\n", word - 7); + instr_out(ctx, i++, + "TB%dA\n", word - 7); + } else if (word >= 11 && word <= 14) { + instr_out(ctx, i, + "TM%dS0: offset=0x%08x, %s\n", + word - 11, + data[i] & 0xfffffffe, + data[i] & 1 ? "use fence" : + ""); + i++; + instr_out(ctx, i, + "TM%dS1: height=%i, width=%i, %s\n", + word - 11, data[i] >> 21, + (data[i] >> 10) & 0x3ff, + data[i] & 2 ? (data[i] & 1 ? + "y-tiled" : + "x-tiled") : + ""); + i++; + instr_out(ctx, i, + "TM%dS2: pitch=%i, \n", + word - 11, + ((data[i] >> 21) + 1) * 4); + i++; + instr_out(ctx, i++, + "TM%dS3\n", word - 11); + instr_out(ctx, i++, + "TM%dS4: dflt color\n", + word - 11); + } + } + } + if (len != i) { + fprintf(out, + "Bad count in 3DSTATE_LOAD_STATE_IMMEDIATE_2\n"); + } + return len; + case 0x00: + instr_out(ctx, 0, "3DSTATE_MAP_STATE\n"); + len = (data[0] & 0x0000003f) + 2; + instr_out(ctx, 1, "mask\n"); + + i = 2; + for (map = 0; map <= 15; map++) { + if (data[1] & (1 << map)) { + int width, height, pitch, dword; + const char *tiling; + + dword = data[i]; + instr_out(ctx, i++, + "map %d MS2 %s%s%s\n", map, + dword & (1 << 31) ? + "untrusted surface, " : "", + dword & (1 << 1) ? + "vertical line stride enable, " : "", + dword & (1 << 0) ? + "vertical ofs enable, " : ""); + + dword = data[i]; + width = ((dword >> 10) & ((1 << 11) - 1)) + 1; + height = ((dword >> 21) & ((1 << 11) - 1)) + 1; + + tiling = "none"; + if (dword & (1 << 2)) + tiling = "fenced"; + else if (dword & (1 << 1)) + tiling = dword & (1 << 0) ? "Y" : "X"; + type = " BAD"; + format = "BAD"; + switch ((dword >> 7) & 0x7) { + case 1: + type = "8b"; + switch ((dword >> 3) & 0xf) { + case 0: + format = "I"; + break; + case 1: + format = "L"; + break; + case 4: + format = "A"; + break; + case 5: + format = " mono"; + break; + } + break; + case 2: + type = "16b"; + switch ((dword >> 3) & 0xf) { + case 0: + format = " rgb565"; + break; + case 1: + format = " argb1555"; + break; + case 2: + format = " argb4444"; + break; + case 5: + format = " ay88"; + break; + case 6: + format = " bump655"; + break; + case 7: + format = "I"; + break; + case 8: + format = "L"; + break; + case 9: + format = "A"; + break; + } + break; + case 3: + type = "32b"; + switch ((dword >> 3) & 0xf) { + case 0: + format = " argb8888"; + break; + case 1: + format = " abgr8888"; + break; + case 2: + format = " xrgb8888"; + break; + case 3: + format = " xbgr8888"; + break; + case 4: + format = " qwvu8888"; + break; + case 5: + format = " axvu8888"; + break; + case 6: + format = " lxvu8888"; + break; + case 7: + format = " xlvu8888"; + break; + case 8: + format = " argb2101010"; + break; + case 9: + format = " abgr2101010"; + break; + case 10: + format = " awvu2101010"; + break; + case 11: + format = " gr1616"; + break; + case 12: + format = " vu1616"; + break; + case 13: + format = " xI824"; + break; + case 14: + format = " xA824"; + break; + case 15: + format = " xL824"; + break; + } + break; + case 5: + type = "422"; + switch ((dword >> 3) & 0xf) { + case 0: + format = " yuv_swapy"; + break; + case 1: + format = " yuv"; + break; + case 2: + format = " yuv_swapuv"; + break; + case 3: + format = " yuv_swapuvy"; + break; + } + break; + case 6: + type = "compressed"; + switch ((dword >> 3) & 0x7) { + case 0: + format = " dxt1"; + break; + case 1: + format = " dxt2_3"; + break; + case 2: + format = " dxt4_5"; + break; + case 3: + format = " fxt1"; + break; + case 4: + format = " dxt1_rb"; + break; + } + break; + case 7: + type = "4b indexed"; + switch ((dword >> 3) & 0xf) { + case 7: + format = " argb8888"; + break; + } + break; + } + dword = data[i]; + instr_out(ctx, i++, + "map %d MS3 [width=%d, height=%d, format=%s%s, tiling=%s%s]\n", + map, width, height, type, format, + tiling, + dword & (1 << 9) ? " palette select" : + ""); + + dword = data[i]; + pitch = + 4 * (((dword >> 21) & ((1 << 11) - 1)) + 1); + instr_out(ctx, i++, + "map %d MS4 [pitch=%d, max_lod=%i, vol_depth=%i, cube_face_ena=%x, %s]\n", + map, pitch, (dword >> 9) & 0x3f, + dword & 0xff, (dword >> 15) & 0x3f, + dword & (1 << 8) ? "miplayout legacy" + : "miplayout right"); + } + } + if (len != i) { + fprintf(out, "Bad count in 3DSTATE_MAP_STATE\n"); + return len; + } + return len; + case 0x06: + instr_out(ctx, 0, + "3DSTATE_PIXEL_SHADER_CONSTANTS\n"); + len = (data[0] & 0x000000ff) + 2; + + i = 2; + for (c = 0; c <= 31; c++) { + if (data[1] & (1 << c)) { + instr_out(ctx, i, "C%d.X = %f\n", c, + int_as_float(data[i])); + i++; + instr_out(ctx, i, "C%d.Y = %f\n", + c, int_as_float(data[i])); + i++; + instr_out(ctx, i, "C%d.Z = %f\n", + c, int_as_float(data[i])); + i++; + instr_out(ctx, i, "C%d.W = %f\n", + c, int_as_float(data[i])); + i++; + } + } + if (len != i) { + fprintf(out, + "Bad count in 3DSTATE_PIXEL_SHADER_CONSTANTS\n"); + } + return len; + case 0x05: + instr_out(ctx, 0, "3DSTATE_PIXEL_SHADER_PROGRAM\n"); + len = (data[0] & 0x000000ff) + 2; + if ((len - 1) % 3 != 0 || len > 370) { + fprintf(out, + "Bad count in 3DSTATE_PIXEL_SHADER_PROGRAM\n"); + } + i = 1; + for (instr = 0; instr < (len - 1) / 3; instr++) { + char instr_prefix[10]; + + sprintf(instr_prefix, "PS%03d", instr); + i915_decode_instruction(ctx, i, + instr_prefix); + i += 3; + } + return len; + case 0x01: + if (IS_GEN2(devid)) + break; + instr_out(ctx, 0, "3DSTATE_SAMPLER_STATE\n"); + instr_out(ctx, 1, "mask\n"); + len = (data[0] & 0x0000003f) + 2; + i = 2; + for (sampler = 0; sampler <= 15; sampler++) { + if (data[1] & (1 << sampler)) { + uint32_t dword; + const char *mip_filter = ""; + + dword = data[i]; + switch ((dword >> 20) & 0x3) { + case 0: + mip_filter = "none"; + break; + case 1: + mip_filter = "nearest"; + break; + case 3: + mip_filter = "linear"; + break; + } + instr_out(ctx, i++, + "sampler %d SS2:%s%s%s " + "base_mip_level=%i, mip_filter=%s, mag_filter=%s, min_filter=%s " + "lod_bias=%.2f,%s max_aniso=%i, shadow_func=%s\n", + sampler, + dword & (1 << 31) ? " reverse gamma," + : "", + dword & (1 << 30) ? " packed2planar," + : "", + dword & (1 << 29) ? + " colorspace conversion," : "", + (dword >> 22) & 0x1f, mip_filter, + decode_sample_filter(dword >> 17), + decode_sample_filter(dword >> 14), + ((dword >> 5) & 0x1ff) / (0x10 * 1.0), + dword & (1 << 4) ? " shadow," : "", + dword & (1 << 3) ? 4 : 2, + decode_compare_func(dword)); + dword = data[i]; + instr_out(ctx, i++, + "sampler %d SS3: min_lod=%.2f,%s " + "tcmode_x=%s, tcmode_y=%s, tcmode_z=%s,%s texmap_idx=%i,%s\n", + sampler, + ((dword >> 24) & 0xff) / (0x10 * 1.0), + dword & (1 << 17) ? + " kill pixel enable," : "", + decode_tex_coord_mode(dword >> 12), + decode_tex_coord_mode(dword >> 9), + decode_tex_coord_mode(dword >> 6), + dword & (1 << 5) ? + " normalized coords," : "", + (dword >> 1) & 0xf, + dword & (1 << 0) ? " deinterlacer," : + ""); + dword = data[i]; + instr_out(ctx, i++, + "sampler %d SS4: border color\n", + sampler); + } + } + if (len != i) { + fprintf(out, "Bad count in 3DSTATE_SAMPLER_STATE\n"); + } + return len; + case 0x85: + len = (data[0] & 0x0000000f) + 2; + + if (len != 2) + fprintf(out, + "Bad count in 3DSTATE_DEST_BUFFER_VARIABLES\n"); + + instr_out(ctx, 0, + "3DSTATE_DEST_BUFFER_VARIABLES\n"); + + switch ((data[1] >> 8) & 0xf) { + case 0x0: + format = "g8"; + break; + case 0x1: + format = "x1r5g5b5"; + break; + case 0x2: + format = "r5g6b5"; + break; + case 0x3: + format = "a8r8g8b8"; + break; + case 0x4: + format = "ycrcb_swapy"; + break; + case 0x5: + format = "ycrcb_normal"; + break; + case 0x6: + format = "ycrcb_swapuv"; + break; + case 0x7: + format = "ycrcb_swapuvy"; + break; + case 0x8: + format = "a4r4g4b4"; + break; + case 0x9: + format = "a1r5g5b5"; + break; + case 0xa: + format = "a2r10g10b10"; + break; + default: + format = "BAD"; + break; + } + switch ((data[1] >> 2) & 0x3) { + case 0x0: + zformat = "u16"; + break; + case 0x1: + zformat = "f16"; + break; + case 0x2: + zformat = "u24x8"; + break; + default: + zformat = "BAD"; + break; + } + instr_out(ctx, 1, + "%s format, %s depth format, early Z %sabled\n", + format, zformat, + (data[1] & (1 << 31)) ? "en" : "dis"); + return len; + + case 0x8e: + { + const char *name, *tiling; + + len = (data[0] & 0x0000000f) + 2; + if (len != 3) + fprintf(out, + "Bad count in 3DSTATE_BUFFER_INFO\n"); + + switch ((data[1] >> 24) & 0x7) { + case 0x3: + name = "color"; + break; + case 0x7: + name = "depth"; + break; + default: + name = "unknown"; + break; + } + + tiling = "none"; + if (data[1] & (1 << 23)) + tiling = "fenced"; + else if (data[1] & (1 << 22)) + tiling = data[1] & (1 << 21) ? "Y" : "X"; + + instr_out(ctx, 0, "3DSTATE_BUFFER_INFO\n"); + instr_out(ctx, 1, + "%s, tiling = %s, pitch=%d\n", name, tiling, + data[1] & 0xffff); + + instr_out(ctx, 2, "address\n"); + return len; + } + case 0x81: + len = (data[0] & 0x0000000f) + 2; + + if (len != 3) + fprintf(out, + "Bad count in 3DSTATE_SCISSOR_RECTANGLE\n"); + + instr_out(ctx, 0, "3DSTATE_SCISSOR_RECTANGLE\n"); + instr_out(ctx, 1, "(%d,%d)\n", + data[1] & 0xffff, data[1] >> 16); + instr_out(ctx, 2, "(%d,%d)\n", + data[2] & 0xffff, data[2] >> 16); + + return len; + case 0x80: + len = (data[0] & 0x0000000f) + 2; + + if (len != 5) + fprintf(out, + "Bad count in 3DSTATE_DRAWING_RECTANGLE\n"); + + instr_out(ctx, 0, "3DSTATE_DRAWING_RECTANGLE\n"); + instr_out(ctx, 1, "%s\n", + data[1] & (1 << 30) ? "depth ofs disabled " : ""); + instr_out(ctx, 2, "(%d,%d)\n", + data[2] & 0xffff, data[2] >> 16); + instr_out(ctx, 3, "(%d,%d)\n", + data[3] & 0xffff, data[3] >> 16); + instr_out(ctx, 4, "(%d,%d)\n", + data[4] & 0xffff, data[4] >> 16); + + return len; + case 0x9c: + len = (data[0] & 0x0000000f) + 2; + + if (len != 7) + fprintf(out, "Bad count in 3DSTATE_CLEAR_PARAMETERS\n"); + + instr_out(ctx, 0, "3DSTATE_CLEAR_PARAMETERS\n"); + instr_out(ctx, 1, "prim_type=%s, clear=%s%s%s\n", + data[1] & (1 << 16) ? "CLEAR_RECT" : "ZONE_INIT", + data[1] & (1 << 2) ? "color," : "", + data[1] & (1 << 1) ? "depth," : "", + data[1] & (1 << 0) ? "stencil," : ""); + instr_out(ctx, 2, "clear color\n"); + instr_out(ctx, 3, "clear depth/stencil\n"); + instr_out(ctx, 4, "color value (rgba8888)\n"); + instr_out(ctx, 5, "depth value %f\n", + int_as_float(data[5])); + instr_out(ctx, 6, "clear stencil\n"); + return len; + } + + for (idx = 0; idx < ARRAY_SIZE(opcodes_3d_1d); idx++) { + opcode_3d_1d = &opcodes_3d_1d[idx]; + if (opcode_3d_1d->i830_only && !IS_GEN2(devid)) + continue; + + if (((data[0] & 0x00ff0000) >> 16) == opcode_3d_1d->opcode) { + len = 1; + + instr_out(ctx, 0, "%s\n", + opcode_3d_1d->name); + if (opcode_3d_1d->max_len > 1) { + len = (data[0] & 0x0000ffff) + 2; + if (len < opcode_3d_1d->min_len || + len > opcode_3d_1d->max_len) { + fprintf(out, "Bad count in %s\n", + opcode_3d_1d->name); + } + } + + for (i = 1; i < len; i++) { + instr_out(ctx, i, "dword %d\n", i); + } + + return len; + } + } + + instr_out(ctx, 0, "3D UNKNOWN: 3d_1d opcode = 0x%x\n", + opcode); + return 1; +} + +static int +decode_3d_primitive(struct drm_intel_decode *ctx) +{ + uint32_t *data = ctx->data; + uint32_t count = ctx->count; + char immediate = (data[0] & (1 << 23)) == 0; + unsigned int len, i, j, ret; + const char *primtype; + int original_s2 = saved_s2; + int original_s4 = saved_s4; + + switch ((data[0] >> 18) & 0xf) { + case 0x0: + primtype = "TRILIST"; + break; + case 0x1: + primtype = "TRISTRIP"; + break; + case 0x2: + primtype = "TRISTRIP_REVERSE"; + break; + case 0x3: + primtype = "TRIFAN"; + break; + case 0x4: + primtype = "POLYGON"; + break; + case 0x5: + primtype = "LINELIST"; + break; + case 0x6: + primtype = "LINESTRIP"; + break; + case 0x7: + primtype = "RECTLIST"; + break; + case 0x8: + primtype = "POINTLIST"; + break; + case 0x9: + primtype = "DIB"; + break; + case 0xa: + primtype = "CLEAR_RECT"; + saved_s4 = 3 << 6; + saved_s2 = ~0; + break; + default: + primtype = "unknown"; + break; + } + + /* XXX: 3DPRIM_DIB not supported */ + if (immediate) { + len = (data[0] & 0x0003ffff) + 2; + instr_out(ctx, 0, "3DPRIMITIVE inline %s\n", + primtype); + if (count < len) + BUFFER_FAIL(count, len, "3DPRIMITIVE inline"); + if (!saved_s2_set || !saved_s4_set) { + fprintf(out, "unknown vertex format\n"); + for (i = 1; i < len; i++) { + instr_out(ctx, i, + " vertex data (%f float)\n", + int_as_float(data[i])); + } + } else { + unsigned int vertex = 0; + for (i = 1; i < len;) { + unsigned int tc; + +#define VERTEX_OUT(fmt, ...) do { \ + if (i < len) \ + instr_out(ctx, i, " V%d."fmt"\n", vertex, __VA_ARGS__); \ + else \ + fprintf(out, " missing data in V%d\n", vertex); \ + i++; \ +} while (0) + + VERTEX_OUT("X = %f", int_as_float(data[i])); + VERTEX_OUT("Y = %f", int_as_float(data[i])); + switch (saved_s4 >> 6 & 0x7) { + case 0x1: + VERTEX_OUT("Z = %f", + int_as_float(data[i])); + break; + case 0x2: + VERTEX_OUT("Z = %f", + int_as_float(data[i])); + VERTEX_OUT("W = %f", + int_as_float(data[i])); + break; + case 0x3: + break; + case 0x4: + VERTEX_OUT("W = %f", + int_as_float(data[i])); + break; + default: + fprintf(out, "bad S4 position mask\n"); + } + + if (saved_s4 & (1 << 10)) { + VERTEX_OUT + ("color = (A=0x%02x, R=0x%02x, G=0x%02x, " + "B=0x%02x)", data[i] >> 24, + (data[i] >> 16) & 0xff, + (data[i] >> 8) & 0xff, + data[i] & 0xff); + } + if (saved_s4 & (1 << 11)) { + VERTEX_OUT + ("spec = (A=0x%02x, R=0x%02x, G=0x%02x, " + "B=0x%02x)", data[i] >> 24, + (data[i] >> 16) & 0xff, + (data[i] >> 8) & 0xff, + data[i] & 0xff); + } + if (saved_s4 & (1 << 12)) + VERTEX_OUT("width = 0x%08x)", data[i]); + + for (tc = 0; tc <= 7; tc++) { + switch ((saved_s2 >> (tc * 4)) & 0xf) { + case 0x0: + VERTEX_OUT("T%d.X = %f", tc, + int_as_float(data + [i])); + VERTEX_OUT("T%d.Y = %f", tc, + int_as_float(data + [i])); + break; + case 0x1: + VERTEX_OUT("T%d.X = %f", tc, + int_as_float(data + [i])); + VERTEX_OUT("T%d.Y = %f", tc, + int_as_float(data + [i])); + VERTEX_OUT("T%d.Z = %f", tc, + int_as_float(data + [i])); + break; + case 0x2: + VERTEX_OUT("T%d.X = %f", tc, + int_as_float(data + [i])); + VERTEX_OUT("T%d.Y = %f", tc, + int_as_float(data + [i])); + VERTEX_OUT("T%d.Z = %f", tc, + int_as_float(data + [i])); + VERTEX_OUT("T%d.W = %f", tc, + int_as_float(data + [i])); + break; + case 0x3: + VERTEX_OUT("T%d.X = %f", tc, + int_as_float(data + [i])); + break; + case 0x4: + VERTEX_OUT + ("T%d.XY = 0x%08x half-float", + tc, data[i]); + break; + case 0x5: + VERTEX_OUT + ("T%d.XY = 0x%08x half-float", + tc, data[i]); + VERTEX_OUT + ("T%d.ZW = 0x%08x half-float", + tc, data[i]); + break; + case 0xf: + break; + default: + fprintf(out, + "bad S2.T%d format\n", + tc); + } + } + vertex++; + } + } + + ret = len; + } else { + /* indirect vertices */ + len = data[0] & 0x0000ffff; /* index count */ + if (data[0] & (1 << 17)) { + /* random vertex access */ + if (count < (len + 1) / 2 + 1) { + BUFFER_FAIL(count, (len + 1) / 2 + 1, + "3DPRIMITIVE random indirect"); + } + instr_out(ctx, 0, + "3DPRIMITIVE random indirect %s (%d)\n", + primtype, len); + if (len == 0) { + /* vertex indices continue until 0xffff is + * found + */ + for (i = 1; i < count; i++) { + if ((data[i] & 0xffff) == 0xffff) { + instr_out(ctx, i, + " indices: (terminator)\n"); + ret = i; + goto out; + } else if ((data[i] >> 16) == 0xffff) { + instr_out(ctx, i, + " indices: 0x%04x, (terminator)\n", + data[i] & 0xffff); + ret = i; + goto out; + } else { + instr_out(ctx, i, + " indices: 0x%04x, 0x%04x\n", + data[i] & 0xffff, + data[i] >> 16); + } + } + fprintf(out, + "3DPRIMITIVE: no terminator found in index buffer\n"); + ret = count; + goto out; + } else { + /* fixed size vertex index buffer */ + for (j = 1, i = 0; i < len; i += 2, j++) { + if (i * 2 == len - 1) { + instr_out(ctx, j, + " indices: 0x%04x\n", + data[j] & 0xffff); + } else { + instr_out(ctx, j, + " indices: 0x%04x, 0x%04x\n", + data[j] & 0xffff, + data[j] >> 16); + } + } + } + ret = (len + 1) / 2 + 1; + goto out; + } else { + /* sequential vertex access */ + instr_out(ctx, 0, + "3DPRIMITIVE sequential indirect %s, %d starting from " + "%d\n", primtype, len, data[1] & 0xffff); + instr_out(ctx, 1, " start\n"); + ret = 2; + goto out; + } + } + +out: + saved_s2 = original_s2; + saved_s4 = original_s4; + return ret; +} + +static int +decode_3d(struct drm_intel_decode *ctx) +{ + uint32_t opcode; + unsigned int idx; + uint32_t *data = ctx->data; + + struct { + uint32_t opcode; + unsigned int min_len; + unsigned int max_len; + const char *name; + } opcodes_3d[] = { + { 0x06, 1, 1, "3DSTATE_ANTI_ALIASING" }, + { 0x08, 1, 1, "3DSTATE_BACKFACE_STENCIL_OPS" }, + { 0x09, 1, 1, "3DSTATE_BACKFACE_STENCIL_MASKS" }, + { 0x16, 1, 1, "3DSTATE_COORD_SET_BINDINGS" }, + { 0x15, 1, 1, "3DSTATE_FOG_COLOR" }, + { 0x0b, 1, 1, "3DSTATE_INDEPENDENT_ALPHA_BLEND" }, + { 0x0d, 1, 1, "3DSTATE_MODES_4" }, + { 0x0c, 1, 1, "3DSTATE_MODES_5" }, + { 0x07, 1, 1, "3DSTATE_RASTERIZATION_RULES"}, + }, *opcode_3d; + + opcode = (data[0] & 0x1f000000) >> 24; + + switch (opcode) { + case 0x1f: + return decode_3d_primitive(ctx); + case 0x1d: + return decode_3d_1d(ctx); + case 0x1c: + return decode_3d_1c(ctx); + } + + for (idx = 0; idx < ARRAY_SIZE(opcodes_3d); idx++) { + opcode_3d = &opcodes_3d[idx]; + if (opcode == opcode_3d->opcode) { + unsigned int len = 1, i; + + instr_out(ctx, 0, "%s\n", opcode_3d->name); + if (opcode_3d->max_len > 1) { + len = (data[0] & 0xff) + 2; + if (len < opcode_3d->min_len || + len > opcode_3d->max_len) { + fprintf(out, "Bad count in %s\n", + opcode_3d->name); + } + } + + for (i = 1; i < len; i++) { + instr_out(ctx, i, "dword %d\n", i); + } + return len; + } + } + + instr_out(ctx, 0, "3D UNKNOWN: 3d opcode = 0x%x\n", opcode); + return 1; +} + +static const char *get_965_surfacetype(unsigned int surfacetype) +{ + switch (surfacetype) { + case 0: + return "1D"; + case 1: + return "2D"; + case 2: + return "3D"; + case 3: + return "CUBE"; + case 4: + return "BUFFER"; + case 7: + return "NULL"; + default: + return "unknown"; + } +} + +static const char *get_965_depthformat(unsigned int depthformat) +{ + switch (depthformat) { + case 0: + return "s8_z24float"; + case 1: + return "z32float"; + case 2: + return "z24s8"; + case 5: + return "z16"; + default: + return "unknown"; + } +} + +static const char *get_965_element_component(uint32_t data, int component) +{ + uint32_t component_control = (data >> (16 + (3 - component) * 4)) & 0x7; + + switch (component_control) { + case 0: + return "nostore"; + case 1: + switch (component) { + case 0: + return "X"; + case 1: + return "Y"; + case 2: + return "Z"; + case 3: + return "W"; + default: + return "fail"; + } + case 2: + return "0.0"; + case 3: + return "1.0"; + case 4: + return "0x1"; + case 5: + return "VID"; + default: + return "fail"; + } +} + +static const char *get_965_prim_type(uint32_t primtype) +{ + switch (primtype) { + case 0x01: + return "point list"; + case 0x02: + return "line list"; + case 0x03: + return "line strip"; + case 0x04: + return "tri list"; + case 0x05: + return "tri strip"; + case 0x06: + return "tri fan"; + case 0x07: + return "quad list"; + case 0x08: + return "quad strip"; + case 0x09: + return "line list adj"; + case 0x0a: + return "line strip adj"; + case 0x0b: + return "tri list adj"; + case 0x0c: + return "tri strip adj"; + case 0x0d: + return "tri strip reverse"; + case 0x0e: + return "polygon"; + case 0x0f: + return "rect list"; + case 0x10: + return "line loop"; + case 0x11: + return "point list bf"; + case 0x12: + return "line strip cont"; + case 0x13: + return "line strip bf"; + case 0x14: + return "line strip cont bf"; + case 0x15: + return "tri fan no stipple"; + default: + return "fail"; + } +} + +static int +i965_decode_urb_fence(struct drm_intel_decode *ctx, int len) +{ + uint32_t vs_fence, clip_fence, gs_fence, sf_fence, vfe_fence, cs_fence; + uint32_t *data = ctx->data; + + if (len != 3) + fprintf(out, "Bad count in URB_FENCE\n"); + + vs_fence = data[1] & 0x3ff; + gs_fence = (data[1] >> 10) & 0x3ff; + clip_fence = (data[1] >> 20) & 0x3ff; + sf_fence = data[2] & 0x3ff; + vfe_fence = (data[2] >> 10) & 0x3ff; + cs_fence = (data[2] >> 20) & 0x7ff; + + instr_out(ctx, 0, "URB_FENCE: %s%s%s%s%s%s\n", + (data[0] >> 13) & 1 ? "cs " : "", + (data[0] >> 12) & 1 ? "vfe " : "", + (data[0] >> 11) & 1 ? "sf " : "", + (data[0] >> 10) & 1 ? "clip " : "", + (data[0] >> 9) & 1 ? "gs " : "", + (data[0] >> 8) & 1 ? "vs " : ""); + instr_out(ctx, 1, + "vs fence: %d, clip_fence: %d, gs_fence: %d\n", + vs_fence, clip_fence, gs_fence); + instr_out(ctx, 2, + "sf fence: %d, vfe_fence: %d, cs_fence: %d\n", + sf_fence, vfe_fence, cs_fence); + if (gs_fence < vs_fence) + fprintf(out, "gs fence < vs fence!\n"); + if (clip_fence < gs_fence) + fprintf(out, "clip fence < gs fence!\n"); + if (sf_fence < clip_fence) + fprintf(out, "sf fence < clip fence!\n"); + if (cs_fence < sf_fence) + fprintf(out, "cs fence < sf fence!\n"); + + return len; +} + +static void +state_base_out(struct drm_intel_decode *ctx, unsigned int index, + const char *name) +{ + if (ctx->data[index] & 1) { + instr_out(ctx, index, + "%s state base address 0x%08x\n", name, + ctx->data[index] & ~1); + } else { + instr_out(ctx, index, "%s state base not updated\n", + name); + } +} + +static void +state_max_out(struct drm_intel_decode *ctx, unsigned int index, + const char *name) +{ + if (ctx->data[index] & 1) { + if (ctx->data[index] == 1) { + instr_out(ctx, index, + "%s state upper bound disabled\n", name); + } else { + instr_out(ctx, index, + "%s state upper bound 0x%08x\n", name, + ctx->data[index] & ~1); + } + } else { + instr_out(ctx, index, + "%s state upper bound not updated\n", name); + } +} + +static int +gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(struct drm_intel_decode *ctx) +{ + instr_out(ctx, 0, "3DSTATE_VIEWPORT_STATE_POINTERS_CC\n"); + instr_out(ctx, 1, "pointer to CC viewport\n"); + + return 2; +} + +static int +gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(struct drm_intel_decode *ctx) +{ + instr_out(ctx, 0, "3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP\n"); + instr_out(ctx, 1, "pointer to SF_CLIP viewport\n"); + + return 2; +} + +static int +gen7_3DSTATE_BLEND_STATE_POINTERS(struct drm_intel_decode *ctx) +{ + instr_out(ctx, 0, "3DSTATE_BLEND_STATE_POINTERS\n"); + instr_out(ctx, 1, "pointer to BLEND_STATE at 0x%08x (%s)\n", + ctx->data[1] & ~1, + (ctx->data[1] & 1) ? "changed" : "unchanged"); + + return 2; +} + +static int +gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(struct drm_intel_decode *ctx) +{ + instr_out(ctx, 0, "3DSTATE_DEPTH_STENCIL_STATE_POINTERS\n"); + instr_out(ctx, 1, + "pointer to DEPTH_STENCIL_STATE at 0x%08x (%s)\n", + ctx->data[1] & ~1, + (ctx->data[1] & 1) ? "changed" : "unchanged"); + + return 2; +} + +static int +gen7_3DSTATE_HIER_DEPTH_BUFFER(struct drm_intel_decode *ctx) +{ + instr_out(ctx, 0, "3DSTATE_HIER_DEPTH_BUFFER\n"); + instr_out(ctx, 1, "pitch %db\n", + (ctx->data[1] & 0x1ffff) + 1); + instr_out(ctx, 2, "pointer to HiZ buffer\n"); + + return 3; +} + +static int +gen6_3DSTATE_CC_STATE_POINTERS(struct drm_intel_decode *ctx) +{ + instr_out(ctx, 0, "3DSTATE_CC_STATE_POINTERS\n"); + instr_out(ctx, 1, "blend change %d\n", ctx->data[1] & 1); + instr_out(ctx, 2, "depth stencil change %d\n", + ctx->data[2] & 1); + instr_out(ctx, 3, "cc change %d\n", ctx->data[3] & 1); + + return 4; +} + +static int +gen7_3DSTATE_CC_STATE_POINTERS(struct drm_intel_decode *ctx) +{ + instr_out(ctx, 0, "3DSTATE_CC_STATE_POINTERS\n"); + instr_out(ctx, 1, "pointer to COLOR_CALC_STATE at 0x%08x " + "(%s)\n", + ctx->data[1] & ~1, + (ctx->data[1] & 1) ? "changed" : "unchanged"); + + return 2; +} + +static int +gen7_3DSTATE_URB_unit(struct drm_intel_decode *ctx, const char *unit) +{ + int start_kb = ((ctx->data[1] >> 25) & 0x3f) * 8; + /* the field is # of 512-bit rows - 1, we print bytes */ + int entry_size = (((ctx->data[1] >> 16) & 0x1ff) + 1); + int nr_entries = ctx->data[1] & 0xffff; + + instr_out(ctx, 0, "3DSTATE_URB_%s\n", unit); + instr_out(ctx, 1, + "%dKB start, size=%d 64B rows, nr_entries=%d, total size %dB\n", + start_kb, entry_size, nr_entries, nr_entries * 64 * entry_size); + + return 2; +} + +static int +gen7_3DSTATE_URB_VS(struct drm_intel_decode *ctx) +{ + return gen7_3DSTATE_URB_unit(ctx, "VS"); +} + +static int +gen7_3DSTATE_URB_HS(struct drm_intel_decode *ctx) +{ + return gen7_3DSTATE_URB_unit(ctx, "HS"); +} + +static int +gen7_3DSTATE_URB_DS(struct drm_intel_decode *ctx) +{ + return gen7_3DSTATE_URB_unit(ctx, "DS"); +} + +static int +gen7_3DSTATE_URB_GS(struct drm_intel_decode *ctx) +{ + return gen7_3DSTATE_URB_unit(ctx, "GS"); +} + +static int +gen7_3DSTATE_CONSTANT(struct drm_intel_decode *ctx, const char *unit) +{ + int rlen[4]; + + rlen[0] = (ctx->data[1] >> 0) & 0xffff; + rlen[1] = (ctx->data[1] >> 16) & 0xffff; + rlen[2] = (ctx->data[2] >> 0) & 0xffff; + rlen[3] = (ctx->data[2] >> 16) & 0xffff; + + instr_out(ctx, 0, "3DSTATE_CONSTANT_%s\n", unit); + instr_out(ctx, 1, "len 0 = %d, len 1 = %d\n", rlen[0], rlen[1]); + instr_out(ctx, 2, "len 2 = %d, len 3 = %d\n", rlen[2], rlen[3]); + instr_out(ctx, 3, "pointer to constbuf 0\n"); + instr_out(ctx, 4, "pointer to constbuf 1\n"); + instr_out(ctx, 5, "pointer to constbuf 2\n"); + instr_out(ctx, 6, "pointer to constbuf 3\n"); + + return 7; +} + +static int +gen7_3DSTATE_CONSTANT_VS(struct drm_intel_decode *ctx) +{ + return gen7_3DSTATE_CONSTANT(ctx, "VS"); +} + +static int +gen7_3DSTATE_CONSTANT_GS(struct drm_intel_decode *ctx) +{ + return gen7_3DSTATE_CONSTANT(ctx, "GS"); +} + +static int +gen7_3DSTATE_CONSTANT_PS(struct drm_intel_decode *ctx) +{ + return gen7_3DSTATE_CONSTANT(ctx, "PS"); +} + +static int +gen7_3DSTATE_CONSTANT_DS(struct drm_intel_decode *ctx) +{ + return gen7_3DSTATE_CONSTANT(ctx, "DS"); +} + +static int +gen7_3DSTATE_CONSTANT_HS(struct drm_intel_decode *ctx) +{ + return gen7_3DSTATE_CONSTANT(ctx, "HS"); +} + + +static int +gen6_3DSTATE_WM(struct drm_intel_decode *ctx) +{ + instr_out(ctx, 0, "3DSTATE_WM\n"); + instr_out(ctx, 1, "kernel start pointer 0\n"); + instr_out(ctx, 2, + "SPF=%d, VME=%d, Sampler Count %d, " + "Binding table count %d\n", + (ctx->data[2] >> 31) & 1, + (ctx->data[2] >> 30) & 1, + (ctx->data[2] >> 27) & 7, + (ctx->data[2] >> 18) & 0xff); + instr_out(ctx, 3, "scratch offset\n"); + instr_out(ctx, 4, + "Depth Clear %d, Depth Resolve %d, HiZ Resolve %d, " + "Dispatch GRF start[0] %d, start[1] %d, start[2] %d\n", + (ctx->data[4] & (1 << 30)) != 0, + (ctx->data[4] & (1 << 28)) != 0, + (ctx->data[4] & (1 << 27)) != 0, + (ctx->data[4] >> 16) & 0x7f, + (ctx->data[4] >> 8) & 0x7f, + (ctx->data[4] & 0x7f)); + instr_out(ctx, 5, + "MaxThreads %d, PS KillPixel %d, PS computed Z %d, " + "PS use sourceZ %d, Thread Dispatch %d, PS use sourceW %d, " + "Dispatch32 %d, Dispatch16 %d, Dispatch8 %d\n", + ((ctx->data[5] >> 25) & 0x7f) + 1, + (ctx->data[5] & (1 << 22)) != 0, + (ctx->data[5] & (1 << 21)) != 0, + (ctx->data[5] & (1 << 20)) != 0, + (ctx->data[5] & (1 << 19)) != 0, + (ctx->data[5] & (1 << 8)) != 0, + (ctx->data[5] & (1 << 2)) != 0, + (ctx->data[5] & (1 << 1)) != 0, + (ctx->data[5] & (1 << 0)) != 0); + instr_out(ctx, 6, + "Num SF output %d, Pos XY offset %d, ZW interp mode %d , " + "Barycentric interp mode 0x%x, Point raster rule %d, " + "Multisample mode %d, " + "Multisample Dispatch mode %d\n", + (ctx->data[6] >> 20) & 0x3f, + (ctx->data[6] >> 18) & 3, + (ctx->data[6] >> 16) & 3, + (ctx->data[6] >> 10) & 0x3f, + (ctx->data[6] & (1 << 9)) != 0, + (ctx->data[6] >> 1) & 3, + (ctx->data[6] & 1)); + instr_out(ctx, 7, "kernel start pointer 1\n"); + instr_out(ctx, 8, "kernel start pointer 2\n"); + + return 9; +} + +static int +gen7_3DSTATE_WM(struct drm_intel_decode *ctx) +{ + const char *computed_depth = ""; + const char *early_depth = ""; + const char *zw_interp = ""; + + switch ((ctx->data[1] >> 23) & 0x3) { + case 0: + computed_depth = ""; + break; + case 1: + computed_depth = "computed depth"; + break; + case 2: + computed_depth = "computed depth >="; + break; + case 3: + computed_depth = "computed depth <="; + break; + } + + switch ((ctx->data[1] >> 21) & 0x3) { + case 0: + early_depth = ""; + break; + case 1: + early_depth = ", EDSC_PSEXEC"; + break; + case 2: + early_depth = ", EDSC_PREPS"; + break; + case 3: + early_depth = ", BAD EDSC"; + break; + } + + switch ((ctx->data[1] >> 17) & 0x3) { + case 0: + early_depth = ""; + break; + case 1: + early_depth = ", BAD ZW interp"; + break; + case 2: + early_depth = ", ZW centroid"; + break; + case 3: + early_depth = ", ZW sample"; + break; + } + + instr_out(ctx, 0, "3DSTATE_WM\n"); + instr_out(ctx, 1, "(%s%s%s%s%s%s)%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", + (ctx->data[1] & (1 << 11)) ? "PP " : "", + (ctx->data[1] & (1 << 12)) ? "PC " : "", + (ctx->data[1] & (1 << 13)) ? "PS " : "", + (ctx->data[1] & (1 << 14)) ? "NPP " : "", + (ctx->data[1] & (1 << 15)) ? "NPC " : "", + (ctx->data[1] & (1 << 16)) ? "NPS " : "", + (ctx->data[1] & (1 << 30)) ? ", depth clear" : "", + (ctx->data[1] & (1 << 29)) ? "" : ", disabled", + (ctx->data[1] & (1 << 28)) ? ", depth resolve" : "", + (ctx->data[1] & (1 << 27)) ? ", hiz resolve" : "", + (ctx->data[1] & (1 << 25)) ? ", kill" : "", + computed_depth, + early_depth, + zw_interp, + (ctx->data[1] & (1 << 20)) ? ", source depth" : "", + (ctx->data[1] & (1 << 19)) ? ", source W" : "", + (ctx->data[1] & (1 << 10)) ? ", coverage" : "", + (ctx->data[1] & (1 << 4)) ? ", poly stipple" : "", + (ctx->data[1] & (1 << 3)) ? ", line stipple" : "", + (ctx->data[1] & (1 << 2)) ? ", point UL" : ", point UR" + ); + instr_out(ctx, 2, "MS\n"); + + return 3; +} + +static int +gen4_3DPRIMITIVE(struct drm_intel_decode *ctx) +{ + instr_out(ctx, 0, + "3DPRIMITIVE: %s %s\n", + get_965_prim_type((ctx->data[0] >> 10) & 0x1f), + (ctx->data[0] & (1 << 15)) ? "random" : "sequential"); + instr_out(ctx, 1, "vertex count\n"); + instr_out(ctx, 2, "start vertex\n"); + instr_out(ctx, 3, "instance count\n"); + instr_out(ctx, 4, "start instance\n"); + instr_out(ctx, 5, "index bias\n"); + + return 6; +} + +static int +gen7_3DPRIMITIVE(struct drm_intel_decode *ctx) +{ + bool indirect = !!(ctx->data[0] & (1 << 10)); + + instr_out(ctx, 0, + "3DPRIMITIVE: %s%s\n", + indirect ? " indirect" : "", + (ctx->data[0] & (1 << 8)) ? " predicated" : ""); + instr_out(ctx, 1, "%s %s\n", + get_965_prim_type(ctx->data[1] & 0x3f), + (ctx->data[1] & (1 << 8)) ? "random" : "sequential"); + instr_out(ctx, 2, indirect ? "ignored" : "vertex count\n"); + instr_out(ctx, 3, indirect ? "ignored" : "start vertex\n"); + instr_out(ctx, 4, indirect ? "ignored" : "instance count\n"); + instr_out(ctx, 5, indirect ? "ignored" : "start instance\n"); + instr_out(ctx, 6, indirect ? "ignored" : "index bias\n"); + + return 7; +} + +static int +decode_3d_965(struct drm_intel_decode *ctx) +{ + uint32_t opcode; + unsigned int len; + unsigned int i, j, sba_len; + const char *desc1 = NULL; + uint32_t *data = ctx->data; + uint32_t devid = ctx->devid; + + struct { + uint32_t opcode; + uint32_t len_mask; + int unsigned min_len; + int unsigned max_len; + const char *name; + int gen; + int (*func)(struct drm_intel_decode *ctx); + } opcodes_3d[] = { + { 0x6000, 0x00ff, 3, 3, "URB_FENCE" }, + { 0x6001, 0xffff, 2, 2, "CS_URB_STATE" }, + { 0x6002, 0x00ff, 2, 2, "CONSTANT_BUFFER" }, + { 0x6101, 0xffff, 6, 10, "STATE_BASE_ADDRESS" }, + { 0x6102, 0xffff, 2, 2, "STATE_SIP" }, + { 0x6104, 0xffff, 1, 1, "3DSTATE_PIPELINE_SELECT" }, + { 0x680b, 0xffff, 1, 1, "3DSTATE_VF_STATISTICS" }, + { 0x6904, 0xffff, 1, 1, "3DSTATE_PIPELINE_SELECT" }, + { 0x7800, 0xffff, 7, 7, "3DSTATE_PIPELINED_POINTERS" }, + { 0x7801, 0x00ff, 4, 6, "3DSTATE_BINDING_TABLE_POINTERS" }, + { 0x7802, 0x00ff, 4, 4, "3DSTATE_SAMPLER_STATE_POINTERS" }, + { 0x7805, 0x00ff, 7, 7, "3DSTATE_DEPTH_BUFFER", 7 }, + { 0x7805, 0x00ff, 3, 3, "3DSTATE_URB" }, + { 0x7804, 0x00ff, 3, 3, "3DSTATE_CLEAR_PARAMS" }, + { 0x7806, 0x00ff, 3, 3, "3DSTATE_STENCIL_BUFFER" }, + { 0x7807, 0x00ff, 4, 4, "3DSTATE_HIER_DEPTH_BUFFER", 6 }, + { 0x7807, 0x00ff, 3, 3, "3DSTATE_HIER_DEPTH_BUFFER", 7, gen7_3DSTATE_HIER_DEPTH_BUFFER }, + { 0x7808, 0x00ff, 5, 257, "3DSTATE_VERTEX_BUFFERS" }, + { 0x7809, 0x00ff, 3, 256, "3DSTATE_VERTEX_ELEMENTS" }, + { 0x780a, 0x00ff, 3, 3, "3DSTATE_INDEX_BUFFER" }, + { 0x780b, 0xffff, 1, 1, "3DSTATE_VF_STATISTICS" }, + { 0x780d, 0x00ff, 4, 4, "3DSTATE_VIEWPORT_STATE_POINTERS" }, + { 0x780e, 0xffff, 4, 4, NULL, 6, gen6_3DSTATE_CC_STATE_POINTERS }, + { 0x780e, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_CC_STATE_POINTERS }, + { 0x780f, 0x00ff, 2, 2, "3DSTATE_SCISSOR_POINTERS" }, + { 0x7810, 0x00ff, 6, 6, "3DSTATE_VS" }, + { 0x7811, 0x00ff, 7, 7, "3DSTATE_GS" }, + { 0x7812, 0x00ff, 4, 4, "3DSTATE_CLIP" }, + { 0x7813, 0x00ff, 20, 20, "3DSTATE_SF", 6 }, + { 0x7813, 0x00ff, 7, 7, "3DSTATE_SF", 7 }, + { 0x7814, 0x00ff, 3, 3, "3DSTATE_WM", 7, gen7_3DSTATE_WM }, + { 0x7814, 0x00ff, 9, 9, "3DSTATE_WM", 6, gen6_3DSTATE_WM }, + { 0x7815, 0x00ff, 5, 5, "3DSTATE_CONSTANT_VS_STATE", 6 }, + { 0x7815, 0x00ff, 7, 7, "3DSTATE_CONSTANT_VS", 7, gen7_3DSTATE_CONSTANT_VS }, + { 0x7816, 0x00ff, 5, 5, "3DSTATE_CONSTANT_GS_STATE", 6 }, + { 0x7816, 0x00ff, 7, 7, "3DSTATE_CONSTANT_GS", 7, gen7_3DSTATE_CONSTANT_GS }, + { 0x7817, 0x00ff, 5, 5, "3DSTATE_CONSTANT_PS_STATE", 6 }, + { 0x7817, 0x00ff, 7, 7, "3DSTATE_CONSTANT_PS", 7, gen7_3DSTATE_CONSTANT_PS }, + { 0x7818, 0xffff, 2, 2, "3DSTATE_SAMPLE_MASK" }, + { 0x7819, 0x00ff, 7, 7, "3DSTATE_CONSTANT_HS", 7, gen7_3DSTATE_CONSTANT_HS }, + { 0x781a, 0x00ff, 7, 7, "3DSTATE_CONSTANT_DS", 7, gen7_3DSTATE_CONSTANT_DS }, + { 0x781b, 0x00ff, 7, 7, "3DSTATE_HS" }, + { 0x781c, 0x00ff, 4, 4, "3DSTATE_TE" }, + { 0x781d, 0x00ff, 6, 6, "3DSTATE_DS" }, + { 0x781e, 0x00ff, 3, 3, "3DSTATE_STREAMOUT" }, + { 0x781f, 0x00ff, 14, 14, "3DSTATE_SBE" }, + { 0x7820, 0x00ff, 8, 8, "3DSTATE_PS" }, + { 0x7821, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP }, + { 0x7823, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC }, + { 0x7824, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_BLEND_STATE_POINTERS }, + { 0x7825, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS }, + { 0x7826, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_VS" }, + { 0x7827, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_HS" }, + { 0x7828, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_DS" }, + { 0x7829, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_GS" }, + { 0x782a, 0x00ff, 2, 2, "3DSTATE_BINDING_TABLE_POINTERS_PS" }, + { 0x782b, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_VS" }, + { 0x782e, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_GS" }, + { 0x782f, 0x00ff, 2, 2, "3DSTATE_SAMPLER_STATE_POINTERS_PS" }, + { 0x7830, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_VS }, + { 0x7831, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_HS }, + { 0x7832, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_DS }, + { 0x7833, 0x00ff, 2, 2, NULL, 7, gen7_3DSTATE_URB_GS }, + { 0x7900, 0xffff, 4, 4, "3DSTATE_DRAWING_RECTANGLE" }, + { 0x7901, 0xffff, 5, 5, "3DSTATE_CONSTANT_COLOR" }, + { 0x7905, 0xffff, 5, 7, "3DSTATE_DEPTH_BUFFER" }, + { 0x7906, 0xffff, 2, 2, "3DSTATE_POLY_STIPPLE_OFFSET" }, + { 0x7907, 0xffff, 33, 33, "3DSTATE_POLY_STIPPLE_PATTERN" }, + { 0x7908, 0xffff, 3, 3, "3DSTATE_LINE_STIPPLE" }, + { 0x7909, 0xffff, 2, 2, "3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP" }, + { 0x7909, 0xffff, 2, 2, "3DSTATE_CLEAR_PARAMS" }, + { 0x790a, 0xffff, 3, 3, "3DSTATE_AA_LINE_PARAMETERS" }, + { 0x790b, 0xffff, 4, 4, "3DSTATE_GS_SVB_INDEX" }, + { 0x790d, 0xffff, 3, 3, "3DSTATE_MULTISAMPLE", 6 }, + { 0x790d, 0xffff, 4, 4, "3DSTATE_MULTISAMPLE", 7 }, + { 0x7910, 0xffff, 2, 2, "3DSTATE_CLEAR_PARAMS" }, + { 0x7912, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_VS" }, + { 0x7916, 0x00ff, 2, 2, "3DSTATE_PUSH_CONSTANT_ALLOC_PS" }, + { 0x7917, 0x00ff, 2, 2+128*2, "3DSTATE_SO_DECL_LIST" }, + { 0x7918, 0x00ff, 4, 4, "3DSTATE_SO_BUFFER" }, + { 0x7a00, 0x00ff, 4, 6, "PIPE_CONTROL" }, + { 0x7b00, 0x00ff, 7, 7, NULL, 7, gen7_3DPRIMITIVE }, + { 0x7b00, 0x00ff, 6, 6, NULL, 0, gen4_3DPRIMITIVE }, + }, *opcode_3d = NULL; + + opcode = (data[0] & 0xffff0000) >> 16; + + for (i = 0; i < ARRAY_SIZE(opcodes_3d); i++) { + if (opcode != opcodes_3d[i].opcode) + continue; + + /* If it's marked as not our gen, skip. */ + if (opcodes_3d[i].gen && opcodes_3d[i].gen != ctx->gen) + continue; + + opcode_3d = &opcodes_3d[i]; + break; + } + + if (opcode_3d) { + if (opcode_3d->max_len == 1) + len = 1; + else + len = (data[0] & opcode_3d->len_mask) + 2; + + if (len < opcode_3d->min_len || + len > opcode_3d->max_len) { + fprintf(out, "Bad length %d in %s, expected %d-%d\n", + len, opcode_3d->name, + opcode_3d->min_len, opcode_3d->max_len); + } + } else { + len = (data[0] & 0x0000ffff) + 2; + } + + switch (opcode) { + case 0x6000: + return i965_decode_urb_fence(ctx, len); + case 0x6001: + instr_out(ctx, 0, "CS_URB_STATE\n"); + instr_out(ctx, 1, + "entry_size: %d [%d bytes], n_entries: %d\n", + (data[1] >> 4) & 0x1f, + (((data[1] >> 4) & 0x1f) + 1) * 64, data[1] & 0x7); + return len; + case 0x6002: + instr_out(ctx, 0, "CONSTANT_BUFFER: %s\n", + (data[0] >> 8) & 1 ? "valid" : "invalid"); + instr_out(ctx, 1, + "offset: 0x%08x, length: %d bytes\n", data[1] & ~0x3f, + ((data[1] & 0x3f) + 1) * 64); + return len; + case 0x6101: + i = 0; + instr_out(ctx, 0, "STATE_BASE_ADDRESS\n"); + i++; + + if (IS_GEN6(devid) || IS_GEN7(devid)) + sba_len = 10; + else if (IS_GEN5(devid)) + sba_len = 8; + else + sba_len = 6; + if (len != sba_len) + fprintf(out, "Bad count in STATE_BASE_ADDRESS\n"); + + state_base_out(ctx, i++, "general"); + state_base_out(ctx, i++, "surface"); + if (IS_GEN6(devid) || IS_GEN7(devid)) + state_base_out(ctx, i++, "dynamic"); + state_base_out(ctx, i++, "indirect"); + if (IS_GEN5(devid) || IS_GEN6(devid) || IS_GEN7(devid)) + state_base_out(ctx, i++, "instruction"); + + state_max_out(ctx, i++, "general"); + if (IS_GEN6(devid) || IS_GEN7(devid)) + state_max_out(ctx, i++, "dynamic"); + state_max_out(ctx, i++, "indirect"); + if (IS_GEN5(devid) || IS_GEN6(devid) || IS_GEN7(devid)) + state_max_out(ctx, i++, "instruction"); + + return len; + case 0x7800: + instr_out(ctx, 0, "3DSTATE_PIPELINED_POINTERS\n"); + instr_out(ctx, 1, "VS state\n"); + instr_out(ctx, 2, "GS state\n"); + instr_out(ctx, 3, "Clip state\n"); + instr_out(ctx, 4, "SF state\n"); + instr_out(ctx, 5, "WM state\n"); + instr_out(ctx, 6, "CC state\n"); + return len; + case 0x7801: + if (len != 6 && len != 4) + fprintf(out, + "Bad count in 3DSTATE_BINDING_TABLE_POINTERS\n"); + if (len == 6) { + instr_out(ctx, 0, + "3DSTATE_BINDING_TABLE_POINTERS\n"); + instr_out(ctx, 1, "VS binding table\n"); + instr_out(ctx, 2, "GS binding table\n"); + instr_out(ctx, 3, "Clip binding table\n"); + instr_out(ctx, 4, "SF binding table\n"); + instr_out(ctx, 5, "WM binding table\n"); + } else { + instr_out(ctx, 0, + "3DSTATE_BINDING_TABLE_POINTERS: VS mod %d, " + "GS mod %d, PS mod %d\n", + (data[0] & (1 << 8)) != 0, + (data[0] & (1 << 9)) != 0, + (data[0] & (1 << 12)) != 0); + instr_out(ctx, 1, "VS binding table\n"); + instr_out(ctx, 2, "GS binding table\n"); + instr_out(ctx, 3, "WM binding table\n"); + } + + return len; + case 0x7802: + instr_out(ctx, 0, + "3DSTATE_SAMPLER_STATE_POINTERS: VS mod %d, " + "GS mod %d, PS mod %d\n", (data[0] & (1 << 8)) != 0, + (data[0] & (1 << 9)) != 0, + (data[0] & (1 << 12)) != 0); + instr_out(ctx, 1, "VS sampler state\n"); + instr_out(ctx, 2, "GS sampler state\n"); + instr_out(ctx, 3, "WM sampler state\n"); + return len; + case 0x7805: + /* Actually 3DSTATE_DEPTH_BUFFER on gen7. */ + if (ctx->gen == 7) + break; + + instr_out(ctx, 0, "3DSTATE_URB\n"); + instr_out(ctx, 1, + "VS entries %d, alloc size %d (1024bit row)\n", + data[1] & 0xffff, ((data[1] >> 16) & 0x07f) + 1); + instr_out(ctx, 2, + "GS entries %d, alloc size %d (1024bit row)\n", + (data[2] >> 8) & 0x3ff, (data[2] & 7) + 1); + return len; + + case 0x7808: + if ((len - 1) % 4 != 0) + fprintf(out, "Bad count in 3DSTATE_VERTEX_BUFFERS\n"); + instr_out(ctx, 0, "3DSTATE_VERTEX_BUFFERS\n"); + + for (i = 1; i < len;) { + int idx, access; + if (IS_GEN6(devid)) { + idx = 26; + access = 20; + } else { + idx = 27; + access = 26; + } + instr_out(ctx, i, + "buffer %d: %s, pitch %db\n", data[i] >> idx, + data[i] & (1 << access) ? "random" : + "sequential", data[i] & 0x07ff); + i++; + instr_out(ctx, i++, "buffer address\n"); + instr_out(ctx, i++, "max index\n"); + instr_out(ctx, i++, "mbz\n"); + } + return len; + + case 0x7809: + if ((len + 1) % 2 != 0) + fprintf(out, "Bad count in 3DSTATE_VERTEX_ELEMENTS\n"); + instr_out(ctx, 0, "3DSTATE_VERTEX_ELEMENTS\n"); + + for (i = 1; i < len;) { + instr_out(ctx, i, + "buffer %d: %svalid, type 0x%04x, " + "src offset 0x%04x bytes\n", + data[i] >> (IS_GEN6(devid) ? 26 : 27), + data[i] & (1 << (IS_GEN6(devid) ? 25 : 26)) ? + "" : "in", (data[i] >> 16) & 0x1ff, + data[i] & 0x07ff); + i++; + instr_out(ctx, i, "(%s, %s, %s, %s), " + "dst offset 0x%02x bytes\n", + get_965_element_component(data[i], 0), + get_965_element_component(data[i], 1), + get_965_element_component(data[i], 2), + get_965_element_component(data[i], 3), + (data[i] & 0xff) * 4); + i++; + } + return len; + + case 0x780d: + instr_out(ctx, 0, + "3DSTATE_VIEWPORT_STATE_POINTERS\n"); + instr_out(ctx, 1, "clip\n"); + instr_out(ctx, 2, "sf\n"); + instr_out(ctx, 3, "cc\n"); + return len; + + case 0x780a: + instr_out(ctx, 0, "3DSTATE_INDEX_BUFFER\n"); + instr_out(ctx, 1, "beginning buffer address\n"); + instr_out(ctx, 2, "ending buffer address\n"); + return len; + + case 0x780f: + instr_out(ctx, 0, "3DSTATE_SCISSOR_POINTERS\n"); + instr_out(ctx, 1, "scissor rect offset\n"); + return len; + + case 0x7810: + instr_out(ctx, 0, "3DSTATE_VS\n"); + instr_out(ctx, 1, "kernel pointer\n"); + instr_out(ctx, 2, + "SPF=%d, VME=%d, Sampler Count %d, " + "Binding table count %d\n", (data[2] >> 31) & 1, + (data[2] >> 30) & 1, (data[2] >> 27) & 7, + (data[2] >> 18) & 0xff); + instr_out(ctx, 3, "scratch offset\n"); + instr_out(ctx, 4, + "Dispatch GRF start %d, VUE read length %d, " + "VUE read offset %d\n", (data[4] >> 20) & 0x1f, + (data[4] >> 11) & 0x3f, (data[4] >> 4) & 0x3f); + instr_out(ctx, 5, + "Max Threads %d, Vertex Cache %sable, " + "VS func %sable\n", ((data[5] >> 25) & 0x7f) + 1, + (data[5] & (1 << 1)) != 0 ? "dis" : "en", + (data[5] & 1) != 0 ? "en" : "dis"); + return len; + + case 0x7811: + instr_out(ctx, 0, "3DSTATE_GS\n"); + instr_out(ctx, 1, "kernel pointer\n"); + instr_out(ctx, 2, + "SPF=%d, VME=%d, Sampler Count %d, " + "Binding table count %d\n", (data[2] >> 31) & 1, + (data[2] >> 30) & 1, (data[2] >> 27) & 7, + (data[2] >> 18) & 0xff); + instr_out(ctx, 3, "scratch offset\n"); + instr_out(ctx, 4, + "Dispatch GRF start %d, VUE read length %d, " + "VUE read offset %d\n", (data[4] & 0xf), + (data[4] >> 11) & 0x3f, (data[4] >> 4) & 0x3f); + instr_out(ctx, 5, + "Max Threads %d, Rendering %sable\n", + ((data[5] >> 25) & 0x7f) + 1, + (data[5] & (1 << 8)) != 0 ? "en" : "dis"); + instr_out(ctx, 6, + "Reorder %sable, Discard Adjaceny %sable, " + "GS %sable\n", + (data[6] & (1 << 30)) != 0 ? "en" : "dis", + (data[6] & (1 << 29)) != 0 ? "en" : "dis", + (data[6] & (1 << 15)) != 0 ? "en" : "dis"); + return len; + + case 0x7812: + instr_out(ctx, 0, "3DSTATE_CLIP\n"); + instr_out(ctx, 1, + "UserClip distance cull test mask 0x%x\n", + data[1] & 0xff); + instr_out(ctx, 2, + "Clip %sable, API mode %s, Viewport XY test %sable, " + "Viewport Z test %sable, Guardband test %sable, Clip mode %d, " + "Perspective Divide %sable, Non-Perspective Barycentric %sable, " + "Tri Provoking %d, Line Provoking %d, Trifan Provoking %d\n", + (data[2] & (1 << 31)) != 0 ? "en" : "dis", + (data[2] & (1 << 30)) != 0 ? "D3D" : "OGL", + (data[2] & (1 << 28)) != 0 ? "en" : "dis", + (data[2] & (1 << 27)) != 0 ? "en" : "dis", + (data[2] & (1 << 26)) != 0 ? "en" : "dis", + (data[2] >> 13) & 7, + (data[2] & (1 << 9)) != 0 ? "dis" : "en", + (data[2] & (1 << 8)) != 0 ? "en" : "dis", + (data[2] >> 4) & 3, (data[2] >> 2) & 3, + (data[2] & 3)); + instr_out(ctx, 3, + "Min PointWidth %d, Max PointWidth %d, " + "Force Zero RTAIndex %sable, Max VPIndex %d\n", + (data[3] >> 17) & 0x7ff, (data[3] >> 6) & 0x7ff, + (data[3] & (1 << 5)) != 0 ? "en" : "dis", + (data[3] & 0xf)); + return len; + + case 0x7813: + if (ctx->gen == 7) + break; + + instr_out(ctx, 0, "3DSTATE_SF\n"); + instr_out(ctx, 1, + "Attrib Out %d, Attrib Swizzle %sable, VUE read length %d, " + "VUE read offset %d\n", (data[1] >> 22) & 0x3f, + (data[1] & (1 << 21)) != 0 ? "en" : "dis", + (data[1] >> 11) & 0x1f, (data[1] >> 4) & 0x3f); + instr_out(ctx, 2, + "Legacy Global DepthBias %sable, FrontFace fill %d, BF fill %d, " + "VP transform %sable, FrontWinding_%s\n", + (data[2] & (1 << 11)) != 0 ? "en" : "dis", + (data[2] >> 5) & 3, (data[2] >> 3) & 3, + (data[2] & (1 << 1)) != 0 ? "en" : "dis", + (data[2] & 1) != 0 ? "CCW" : "CW"); + instr_out(ctx, 3, + "AA %sable, CullMode %d, Scissor %sable, Multisample m ode %d\n", + (data[3] & (1 << 31)) != 0 ? "en" : "dis", + (data[3] >> 29) & 3, + (data[3] & (1 << 11)) != 0 ? "en" : "dis", + (data[3] >> 8) & 3); + instr_out(ctx, 4, + "Last Pixel %sable, SubPixel Precision %d, Use PixelWidth %d\n", + (data[4] & (1 << 31)) != 0 ? "en" : "dis", + (data[4] & (1 << 12)) != 0 ? 4 : 8, + (data[4] & (1 << 11)) != 0); + instr_out(ctx, 5, + "Global Depth Offset Constant %f\n", + *(float *)(&data[5])); + instr_out(ctx, 6, "Global Depth Offset Scale %f\n", + *(float *)(&data[6])); + instr_out(ctx, 7, "Global Depth Offset Clamp %f\n", + *(float *)(&data[7])); + + for (i = 0, j = 0; i < 8; i++, j += 2) + instr_out(ctx, i + 8, + "Attrib %d (Override %s%s%s%s, Const Source %d, Swizzle Select %d, " + "Source %d); Attrib %d (Override %s%s%s%s, Const Source %d, Swizzle Select %d, Source %d)\n", + j + 1, + (data[8 + i] & (1 << 31)) != 0 ? "W" : "", + (data[8 + i] & (1 << 30)) != 0 ? "Z" : "", + (data[8 + i] & (1 << 29)) != 0 ? "Y" : "", + (data[8 + i] & (1 << 28)) != 0 ? "X" : "", + (data[8 + i] >> 25) & 3, + (data[8 + i] >> 22) & 3, + (data[8 + i] >> 16) & 0x1f, j, + (data[8 + i] & (1 << 15)) != 0 ? "W" : "", + (data[8 + i] & (1 << 14)) != 0 ? "Z" : "", + (data[8 + i] & (1 << 13)) != 0 ? "Y" : "", + (data[8 + i] & (1 << 12)) != 0 ? "X" : "", + (data[8 + i] >> 9) & 3, + (data[8 + i] >> 6) & 3, (data[8 + i] & 0x1f)); + instr_out(ctx, 16, + "Point Sprite TexCoord Enable\n"); + instr_out(ctx, 17, "Const Interp Enable\n"); + instr_out(ctx, 18, + "Attrib 7-0 WrapShortest Enable\n"); + instr_out(ctx, 19, + "Attrib 15-8 WrapShortest Enable\n"); + + return len; + + case 0x7900: + instr_out(ctx, 0, "3DSTATE_DRAWING_RECTANGLE\n"); + instr_out(ctx, 1, "top left: %d,%d\n", + data[1] & 0xffff, (data[1] >> 16) & 0xffff); + instr_out(ctx, 2, "bottom right: %d,%d\n", + data[2] & 0xffff, (data[2] >> 16) & 0xffff); + instr_out(ctx, 3, "origin: %d,%d\n", + (int)data[3] & 0xffff, ((int)data[3] >> 16) & 0xffff); + + return len; + + case 0x7905: + instr_out(ctx, 0, "3DSTATE_DEPTH_BUFFER\n"); + if (IS_GEN5(devid) || IS_GEN6(devid)) + instr_out(ctx, 1, + "%s, %s, pitch = %d bytes, %stiled, HiZ %d, Seperate Stencil %d\n", + get_965_surfacetype(data[1] >> 29), + get_965_depthformat((data[1] >> 18) & 0x7), + (data[1] & 0x0001ffff) + 1, + data[1] & (1 << 27) ? "" : "not ", + (data[1] & (1 << 22)) != 0, + (data[1] & (1 << 21)) != 0); + else + instr_out(ctx, 1, + "%s, %s, pitch = %d bytes, %stiled\n", + get_965_surfacetype(data[1] >> 29), + get_965_depthformat((data[1] >> 18) & 0x7), + (data[1] & 0x0001ffff) + 1, + data[1] & (1 << 27) ? "" : "not "); + instr_out(ctx, 2, "depth offset\n"); + instr_out(ctx, 3, "%dx%d\n", + ((data[3] & 0x0007ffc0) >> 6) + 1, + ((data[3] & 0xfff80000) >> 19) + 1); + instr_out(ctx, 4, "volume depth\n"); + if (len >= 6) + instr_out(ctx, 5, "\n"); + if (len >= 7) { + if (IS_GEN6(devid)) + instr_out(ctx, 6, "\n"); + else + instr_out(ctx, 6, + "render target view extent\n"); + } + + return len; + + case 0x7a00: + if (IS_GEN6(devid) || IS_GEN7(devid)) { + unsigned int i; + if (len != 4 && len != 5) + fprintf(out, "Bad count in PIPE_CONTROL\n"); + + switch ((data[1] >> 14) & 0x3) { + case 0: + desc1 = "no write"; + break; + case 1: + desc1 = "qword write"; + break; + case 2: + desc1 = "PS_DEPTH_COUNT write"; + break; + case 3: + desc1 = "TIMESTAMP write"; + break; + } + instr_out(ctx, 0, "PIPE_CONTROL\n"); + instr_out(ctx, 1, + "%s, %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", + desc1, + data[1] & (1 << 20) ? "cs stall, " : "", + data[1] & (1 << 19) ? + "global snapshot count reset, " : "", + data[1] & (1 << 18) ? "tlb invalidate, " : "", + data[1] & (1 << 17) ? "gfdt flush, " : "", + data[1] & (1 << 17) ? "media state clear, " : + "", + data[1] & (1 << 13) ? "depth stall, " : "", + data[1] & (1 << 12) ? + "render target cache flush, " : "", + data[1] & (1 << 11) ? + "instruction cache invalidate, " : "", + data[1] & (1 << 10) ? + "texture cache invalidate, " : "", + data[1] & (1 << 9) ? + "indirect state invalidate, " : "", + data[1] & (1 << 8) ? "notify irq, " : "", + data[1] & (1 << 7) ? "PIPE_CONTROL flush, " : + "", + data[1] & (1 << 6) ? "protect mem app_id, " : + "", data[1] & (1 << 5) ? "DC flush, " : "", + data[1] & (1 << 4) ? "vf fetch invalidate, " : + "", + data[1] & (1 << 3) ? + "constant cache invalidate, " : "", + data[1] & (1 << 2) ? + "state cache invalidate, " : "", + data[1] & (1 << 1) ? "stall at scoreboard, " : + "", + data[1] & (1 << 0) ? "depth cache flush, " : + ""); + if (len == 5) { + instr_out(ctx, 2, + "destination address\n"); + instr_out(ctx, 3, + "immediate dword low\n"); + instr_out(ctx, 4, + "immediate dword high\n"); + } else { + for (i = 2; i < len; i++) { + instr_out(ctx, i, "\n"); + } + } + return len; + } else { + if (len != 4) + fprintf(out, "Bad count in PIPE_CONTROL\n"); + + switch ((data[0] >> 14) & 0x3) { + case 0: + desc1 = "no write"; + break; + case 1: + desc1 = "qword write"; + break; + case 2: + desc1 = "PS_DEPTH_COUNT write"; + break; + case 3: + desc1 = "TIMESTAMP write"; + break; + } + instr_out(ctx, 0, + "PIPE_CONTROL: %s, %sdepth stall, %sRC write flush, " + "%sinst flush\n", + desc1, + data[0] & (1 << 13) ? "" : "no ", + data[0] & (1 << 12) ? "" : "no ", + data[0] & (1 << 11) ? "" : "no "); + instr_out(ctx, 1, "destination address\n"); + instr_out(ctx, 2, "immediate dword low\n"); + instr_out(ctx, 3, "immediate dword high\n"); + return len; + } + } + + if (opcode_3d) { + if (opcode_3d->func) { + return opcode_3d->func(ctx); + } else { + unsigned int i; + + instr_out(ctx, 0, "%s\n", opcode_3d->name); + + for (i = 1; i < len; i++) { + instr_out(ctx, i, "dword %d\n", i); + } + return len; + } + } + + instr_out(ctx, 0, "3D UNKNOWN: 3d_965 opcode = 0x%x\n", + opcode); + return 1; +} + +static int +decode_3d_i830(struct drm_intel_decode *ctx) +{ + unsigned int idx; + uint32_t opcode; + uint32_t *data = ctx->data; + + struct { + uint32_t opcode; + unsigned int min_len; + unsigned int max_len; + const char *name; + } opcodes_3d[] = { + { 0x02, 1, 1, "3DSTATE_MODES_3" }, + { 0x03, 1, 1, "3DSTATE_ENABLES_1" }, + { 0x04, 1, 1, "3DSTATE_ENABLES_2" }, + { 0x05, 1, 1, "3DSTATE_VFT0" }, + { 0x06, 1, 1, "3DSTATE_AA" }, + { 0x07, 1, 1, "3DSTATE_RASTERIZATION_RULES" }, + { 0x08, 1, 1, "3DSTATE_MODES_1" }, + { 0x09, 1, 1, "3DSTATE_STENCIL_TEST" }, + { 0x0a, 1, 1, "3DSTATE_VFT1" }, + { 0x0b, 1, 1, "3DSTATE_INDPT_ALPHA_BLEND" }, + { 0x0c, 1, 1, "3DSTATE_MODES_5" }, + { 0x0d, 1, 1, "3DSTATE_MAP_BLEND_OP" }, + { 0x0e, 1, 1, "3DSTATE_MAP_BLEND_ARG" }, + { 0x0f, 1, 1, "3DSTATE_MODES_2" }, + { 0x15, 1, 1, "3DSTATE_FOG_COLOR" }, + { 0x16, 1, 1, "3DSTATE_MODES_4"}, + }, *opcode_3d; + + opcode = (data[0] & 0x1f000000) >> 24; + + switch (opcode) { + case 0x1f: + return decode_3d_primitive(ctx); + case 0x1d: + return decode_3d_1d(ctx); + case 0x1c: + return decode_3d_1c(ctx); + } + + for (idx = 0; idx < ARRAY_SIZE(opcodes_3d); idx++) { + opcode_3d = &opcodes_3d[idx]; + if ((data[0] & 0x1f000000) >> 24 == opcode_3d->opcode) { + unsigned int len = 1, i; + + instr_out(ctx, 0, "%s\n", opcode_3d->name); + if (opcode_3d->max_len > 1) { + len = (data[0] & 0xff) + 2; + if (len < opcode_3d->min_len || + len > opcode_3d->max_len) { + fprintf(out, "Bad count in %s\n", + opcode_3d->name); + } + } + + for (i = 1; i < len; i++) { + instr_out(ctx, i, "dword %d\n", i); + } + return len; + } + } + + instr_out(ctx, 0, "3D UNKNOWN: 3d_i830 opcode = 0x%x\n", + opcode); + return 1; +} + +struct drm_intel_decode * +drm_intel_decode_context_alloc(uint32_t devid) +{ + struct drm_intel_decode *ctx; + + ctx = calloc(1, sizeof(struct drm_intel_decode)); + if (!ctx) + return NULL; + + ctx->devid = devid; + ctx->out = stdout; + + if (IS_GEN7(devid)) + ctx->gen = 7; + else if (IS_GEN6(devid)) + ctx->gen = 6; + else if (IS_GEN5(devid)) + ctx->gen = 5; + else if (IS_GEN4(devid)) + ctx->gen = 4; + else if (IS_9XX(devid)) + ctx->gen = 3; + else { + assert(IS_GEN2(devid)); + ctx->gen = 2; + } + + return ctx; +} + +void +drm_intel_decode_context_free(struct drm_intel_decode *ctx) +{ + free(ctx); +} + +void +drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx, + int dump_past_end) +{ + ctx->dump_past_end = !!dump_past_end; +} + +void +drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx, + void *data, uint32_t hw_offset, int count) +{ + ctx->base_data = data; + ctx->base_hw_offset = hw_offset; + ctx->base_count = count; +} + +void +drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx, + uint32_t head, uint32_t tail) +{ + ctx->head = head; + ctx->tail = tail; +} + +void +drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, + FILE *out) +{ + ctx->out = out; +} + +/** + * Decodes an i830-i915 batch buffer, writing the output to stdout. + * + * \param data batch buffer contents + * \param count number of DWORDs to decode in the batch buffer + * \param hw_offset hardware address for the buffer + */ +void +drm_intel_decode(struct drm_intel_decode *ctx) +{ + int ret; + unsigned int index = 0; + uint32_t devid; + int size = ctx->base_count * 4; + void *temp; + + if (!ctx) + return; + + /* Put a scratch page full of obviously undefined data after + * the batchbuffer. This lets us avoid a bunch of length + * checking in statically sized packets. + */ + temp = malloc(size + 4096); + memcpy(temp, ctx->base_data, size); + memset((char *)temp + size, 0xd0, 4096); + ctx->data = temp; + + ctx->hw_offset = ctx->base_hw_offset; + ctx->count = ctx->base_count; + + devid = ctx->devid; + head_offset = ctx->head; + tail_offset = ctx->tail; + out = ctx->out; + + saved_s2_set = 0; + saved_s4_set = 1; + + while (ctx->count > 0) { + index = 0; + + switch ((ctx->data[index] & 0xe0000000) >> 29) { + case 0x0: + ret = decode_mi(ctx); + + /* If MI_BATCHBUFFER_END happened, then dump + * the rest of the output in case we some day + * want it in debugging, but don't decode it + * since it'll just confuse in the common + * case. + */ + if (ret == -1) { + if (ctx->dump_past_end) { + index++; + } else { + for (index = index + 1; index < ctx->count; + index++) { + instr_out(ctx, index, "\n"); + } + } + } else + index += ret; + break; + case 0x2: + index += decode_2d(ctx); + break; + case 0x3: + if (IS_9XX(devid) && !IS_GEN3(devid)) { + index += + decode_3d_965(ctx); + } else if (IS_GEN3(devid)) { + index += decode_3d(ctx); + } else { + index += + decode_3d_i830(ctx); + } + break; + default: + instr_out(ctx, index, "UNKNOWN\n"); + index++; + break; + } + fflush(out); + + if (ctx->count < index) + break; + + ctx->count -= index; + ctx->data += index; + ctx->hw_offset += 4 * index; + } + + free(temp); +} diff --git a/intel/libdrm_intel.pc.in b/intel/libdrm_intel.pc.in new file mode 100644 index 0000000..3ba6793 --- /dev/null +++ b/intel/libdrm_intel.pc.in @@ -0,0 +1,11 @@ +prefix=@prefix@ +exec_prefix=@exec_prefix@ +libdir=@libdir@ +includedir=@includedir@ + +Name: libdrm +Description: Userspace interface to kernel DRM services +Version: @PACKAGE_VERSION@ +Requires: libdrm +Libs: -L${libdir} -ldrm_intel +Cflags: -I${includedir} -I${includedir}/libdrm diff --git a/intel/mm.c b/intel/mm.c new file mode 100644 index 0000000..1069745 --- /dev/null +++ b/intel/mm.c @@ -0,0 +1,271 @@ +/* + * GLX Hardware Device Driver common code + * Copyright (C) 1999 Wittawat Yamwong + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * WITTAWAT YAMWONG, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include + +#include "xf86drm.h" +#include "mm.h" + +void mmDumpMemInfo(const struct mem_block *heap) +{ + drmMsg("Memory heap %p:\n", (void *)heap); + if (heap == 0) { + drmMsg(" heap == 0\n"); + } else { + const struct mem_block *p; + + for (p = heap->next; p != heap; p = p->next) { + drmMsg(" Offset:%08x, Size:%08x, %c%c\n", p->ofs, + p->size, p->free ? 'F' : '.', + p->reserved ? 'R' : '.'); + } + + drmMsg("\nFree list:\n"); + + for (p = heap->next_free; p != heap; p = p->next_free) { + drmMsg(" FREE Offset:%08x, Size:%08x, %c%c\n", p->ofs, + p->size, p->free ? 'F' : '.', + p->reserved ? 'R' : '.'); + } + + } + drmMsg("End of memory blocks\n"); +} + +struct mem_block *mmInit(int ofs, int size) +{ + struct mem_block *heap, *block; + + if (size <= 0) + return NULL; + + heap = (struct mem_block *)calloc(1, sizeof(struct mem_block)); + if (!heap) + return NULL; + + block = (struct mem_block *)calloc(1, sizeof(struct mem_block)); + if (!block) { + free(heap); + return NULL; + } + + heap->next = block; + heap->prev = block; + heap->next_free = block; + heap->prev_free = block; + + block->heap = heap; + block->next = heap; + block->prev = heap; + block->next_free = heap; + block->prev_free = heap; + + block->ofs = ofs; + block->size = size; + block->free = 1; + + return heap; +} + +static struct mem_block *SliceBlock(struct mem_block *p, + int startofs, int size, + int reserved, int alignment) +{ + struct mem_block *newblock; + + /* break left [p, newblock, p->next], then p = newblock */ + if (startofs > p->ofs) { + newblock = + (struct mem_block *)calloc(1, sizeof(struct mem_block)); + if (!newblock) + return NULL; + newblock->ofs = startofs; + newblock->size = p->size - (startofs - p->ofs); + newblock->free = 1; + newblock->heap = p->heap; + + newblock->next = p->next; + newblock->prev = p; + p->next->prev = newblock; + p->next = newblock; + + newblock->next_free = p->next_free; + newblock->prev_free = p; + p->next_free->prev_free = newblock; + p->next_free = newblock; + + p->size -= newblock->size; + p = newblock; + } + + /* break right, also [p, newblock, p->next] */ + if (size < p->size) { + newblock = + (struct mem_block *)calloc(1, sizeof(struct mem_block)); + if (!newblock) + return NULL; + newblock->ofs = startofs + size; + newblock->size = p->size - size; + newblock->free = 1; + newblock->heap = p->heap; + + newblock->next = p->next; + newblock->prev = p; + p->next->prev = newblock; + p->next = newblock; + + newblock->next_free = p->next_free; + newblock->prev_free = p; + p->next_free->prev_free = newblock; + p->next_free = newblock; + + p->size = size; + } + + /* p = middle block */ + p->free = 0; + + /* Remove p from the free list: + */ + p->next_free->prev_free = p->prev_free; + p->prev_free->next_free = p->next_free; + + p->next_free = 0; + p->prev_free = 0; + + p->reserved = reserved; + return p; +} + +struct mem_block *mmAllocMem(struct mem_block *heap, int size, int align2, + int startSearch) +{ + struct mem_block *p; + const int mask = (1 << align2) - 1; + int startofs = 0; + int endofs; + + if (!heap || align2 < 0 || size <= 0) + return NULL; + + for (p = heap->next_free; p != heap; p = p->next_free) { + assert(p->free); + + startofs = (p->ofs + mask) & ~mask; + if (startofs < startSearch) { + startofs = startSearch; + } + endofs = startofs + size; + if (endofs <= (p->ofs + p->size)) + break; + } + + if (p == heap) + return NULL; + + assert(p->free); + p = SliceBlock(p, startofs, size, 0, mask + 1); + + return p; +} + +struct mem_block *mmFindBlock(struct mem_block *heap, int start) +{ + struct mem_block *p; + + for (p = heap->next; p != heap; p = p->next) { + if (p->ofs == start) + return p; + } + + return NULL; +} + +static int Join2Blocks(struct mem_block *p) +{ + /* XXX there should be some assertions here */ + + /* NOTE: heap->free == 0 */ + + if (p->free && p->next->free) { + struct mem_block *q = p->next; + + assert(p->ofs + p->size == q->ofs); + p->size += q->size; + + p->next = q->next; + q->next->prev = p; + + q->next_free->prev_free = q->prev_free; + q->prev_free->next_free = q->next_free; + + free(q); + return 1; + } + return 0; +} + +int mmFreeMem(struct mem_block *b) +{ + if (!b) + return 0; + + if (b->free) { + drmMsg("block already free\n"); + return -1; + } + if (b->reserved) { + drmMsg("block is reserved\n"); + return -1; + } + + b->free = 1; + b->next_free = b->heap->next_free; + b->prev_free = b->heap; + b->next_free->prev_free = b; + b->prev_free->next_free = b; + + Join2Blocks(b); + if (b->prev != b->heap) + Join2Blocks(b->prev); + + return 0; +} + +void mmDestroy(struct mem_block *heap) +{ + struct mem_block *p; + + if (!heap) + return; + + for (p = heap->next; p != heap;) { + struct mem_block *next = p->next; + free(p); + p = next; + } + + free(heap); +} diff --git a/intel/mm.h b/intel/mm.h new file mode 100644 index 0000000..8a5235b --- /dev/null +++ b/intel/mm.h @@ -0,0 +1,94 @@ +/* + * GLX Hardware Device Driver common code + * Copyright (C) 1999 Wittawat Yamwong + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * KEITH WHITWELL, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/** + * Memory manager code. Primarily used by device drivers to manage texture + * heaps, etc. + */ + +#ifndef MM_H +#define MM_H + +struct mem_block { + struct mem_block *next, *prev; + struct mem_block *next_free, *prev_free; + struct mem_block *heap; + int ofs, size; + unsigned int free:1; + unsigned int reserved:1; +}; + +/* Rename the variables in the drm copy of this code so that it doesn't + * conflict with mesa or whoever else has copied it around. + */ +#define mmInit drm_mmInit +#define mmAllocMem drm_mmAllocMem +#define mmFreeMem drm_mmFreeMem +#define mmFindBlock drm_mmFindBlock +#define mmDestroy drm_mmDestroy +#define mmDumpMemInfo drm_mmDumpMemInfo + +/** + * input: total size in bytes + * return: a heap pointer if OK, NULL if error + */ +extern struct mem_block *mmInit(int ofs, int size); + +/** + * Allocate 'size' bytes with 2^align2 bytes alignment, + * restrict the search to free memory after 'startSearch' + * depth and back buffers should be in different 4mb banks + * to get better page hits if possible + * input: size = size of block + * align2 = 2^align2 bytes alignment + * startSearch = linear offset from start of heap to begin search + * return: pointer to the allocated block, 0 if error + */ +extern struct mem_block *mmAllocMem(struct mem_block *heap, int size, + int align2, int startSearch); + +/** + * Free block starts at offset + * input: pointer to a block + * return: 0 if OK, -1 if error + */ +extern int mmFreeMem(struct mem_block *b); + +/** + * Free block starts at offset + * input: pointer to a heap, start offset + * return: pointer to a block + */ +extern struct mem_block *mmFindBlock(struct mem_block *heap, int start); + +/** + * destroy MM + */ +extern void mmDestroy(struct mem_block *mmInit); + +/** + * For debuging purpose. + */ +extern void mmDumpMemInfo(const struct mem_block *mmInit); + +#endif diff --git a/intel/test_decode.c b/intel/test_decode.c new file mode 100644 index 0000000..c9ab7ad --- /dev/null +++ b/intel/test_decode.c @@ -0,0 +1,191 @@ +/* + * Copyright © 2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "config.h" +#include "intel_bufmgr.h" +#include "intel_chipset.h" + +#define HW_OFFSET 0x12300000 + +static void +usage(void) +{ + fprintf(stderr, "usage:\n"); + fprintf(stderr, " test_decode \n"); + fprintf(stderr, " test_decode -dump\n"); + exit(1); +} + +static void +read_file(const char *filename, void **ptr, size_t *size) +{ + int fd, ret; + struct stat st; + + fd = open(filename, O_RDONLY); + if (fd == -1) + errx(1, "couldn't open `%s'", filename); + + ret = fstat(fd, &st); + if (ret) + errx(1, "couldn't stat `%s'", filename); + + *size = st.st_size; + *ptr = mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0); + if (*ptr == MAP_FAILED) + errx(1, "couldn't map `%s'", filename); + + close(fd); +} + +static void +dump_batch(struct drm_intel_decode *ctx, const char *batch_filename) +{ + void *batch_ptr; + size_t batch_size; + + read_file(batch_filename, &batch_ptr, &batch_size); + + drm_intel_decode_set_batch_pointer(ctx, batch_ptr, HW_OFFSET, + batch_size / 4); + drm_intel_decode_set_output_file(ctx, stdout); + + drm_intel_decode(ctx); +} + +static void +compare_batch(struct drm_intel_decode *ctx, const char *batch_filename) +{ + FILE *out = NULL; + void *ptr, *ref_ptr, *batch_ptr; + size_t size, ref_size, batch_size; + const char *ref_suffix = "-ref.txt"; + char *ref_filename; + + ref_filename = malloc(strlen(batch_filename) + strlen(ref_suffix) + 1); + sprintf(ref_filename, "%s%s", batch_filename, ref_suffix); + + /* Read the batch and reference. */ + read_file(batch_filename, &batch_ptr, &batch_size); + read_file(ref_filename, &ref_ptr, &ref_size); + + /* Set up our decode output in memory, because I don't want to + * figure out how to output to a file in a safe and sane way + * inside of an automake project's test infrastructure. + */ +#ifdef HAVE_OPEN_MEMSTREAM + out = open_memstream((char **)&ptr, &size); +#else + fprintf(stderr, "platform lacks open_memstream, skipping.\n"); + exit(77); +#endif + + drm_intel_decode_set_batch_pointer(ctx, batch_ptr, HW_OFFSET, + batch_size / 4); + drm_intel_decode_set_output_file(ctx, out); + + drm_intel_decode(ctx); + + if (strcmp(ref_ptr, ptr) != 0) { + fprintf(stderr, "Decode mismatch with reference `%s'.\n", + ref_filename); + fprintf(stderr, "You can dump the new output using:\n"); + fprintf(stderr, " test_decode \"%s\" -dump\n", batch_filename); + exit(1); + } + + fclose(out); + free(ref_filename); + free(ptr); +} + +static uint16_t +infer_devid(const char *batch_filename) +{ + struct { + const char *name; + uint16_t devid; + } chipsets[] = { + { "830", 0x3577}, + { "855", 0x3582}, + { "945", 0x2772}, + { "gen4", 0x2a02 }, + { "gm45", 0x2a42 }, + { "gen5", PCI_CHIP_ILD_G }, + { "gen6", PCI_CHIP_SANDYBRIDGE_GT2 }, + { "gen7", PCI_CHIP_IVYBRIDGE_GT2 }, + { NULL, 0 }, + }; + int i; + + for (i = 0; chipsets[i].name != NULL; i++) { + if (strstr(batch_filename, chipsets[i].name)) + return chipsets[i].devid; + } + + fprintf(stderr, "Couldn't guess chipset id from batch filename `%s'.\n", + batch_filename); + fprintf(stderr, "Must be contain one of:\n"); + for (i = 0; chipsets[i].name != NULL; i++) { + fprintf(stderr, " %s\n", chipsets[i].name); + } + exit(1); +} + +int +main(int argc, char **argv) +{ + uint16_t devid; + struct drm_intel_decode *ctx; + + if (argc < 2) + usage(); + + + devid = infer_devid(argv[1]); + + ctx = drm_intel_decode_context_alloc(devid); + + if (argc == 3) { + if (strcmp(argv[2], "-dump") == 0) + dump_batch(ctx, argv[1]); + else + usage(); + } else { + compare_batch(ctx, argv[1]); + } + + drm_intel_decode_context_free(ctx); + + return 0; +} diff --git a/intel/tests/.gitignore b/intel/tests/.gitignore new file mode 100644 index 0000000..e9d01ec --- /dev/null +++ b/intel/tests/.gitignore @@ -0,0 +1 @@ +*-new.txt diff --git a/intel/tests/gen4-3d.batch b/intel/tests/gen4-3d.batch new file mode 100644 index 0000000000000000000000000000000000000000..e6911a438e740c493b1c7f3670cf1bc650f32e34 GIT binary patch literal 1952 zcma)7Jx>Bb5S=>?1Cd0H#!y%s#=?k&iKT@=Wvq;q<A{5U*6fM0_C3QORZz(26C z*Y}oPax8lX6XternS1kQ=5dGwZIN=V; z*!e4#PI)rCzAJMrip0?ycOo^cUHAk({6MZtiNZlxXo+m&E;>StFQRbkUY%5cS&A#% zq|B3YEYb)>c6Y?{BL)UlNpPS{J*fBO-$?Y0UU*MlgBOt|ybT}11?R)pMP9D_%-KhH z5K3~ZG1EB>c5Mar9Opoi8{iPjh2yP()53#>&sPS{6rIhhm3$PA=JT6@Gg=cz^#QS~ z;@RUWa$RlVqOFjcaRsvu^sIddgmtn;+ETxidT@@l0gvFEsj&skpu{Tz!k6 zG!I^bci{tgmPYOmO&0Q6)aY3AW*(Z&n|Y?s`FS`Wg@gGV1A|yDoRI^EIcawN{lcuD z#B%A6ygnUxP8`jP?RN3%t%*b3M2KA#Z*+5Jnu@$xx@qC%V16G6Tjqy+w9ykT*oSa? z&g%C;9Oz{qVXl6Kcz*PVS;8CGNAN8DnRm<2IWy19){T#5khdw(?kn?sI`Y}`Q8+oe zAx>`%oNmv?6afnz~yeq%a&-aD-Hd{aajePwu YFRk~0dBZ1Mt^X4Bz9&wGe(-ql9|CIZ;Q#;t literal 0 HcmV?d00001 diff --git a/intel/tests/gen4-3d.batch-ref.txt b/intel/tests/gen4-3d.batch-ref.txt new file mode 100644 index 0000000..20aa1d4 --- /dev/null +++ b/intel/tests/gen4-3d.batch-ref.txt @@ -0,0 +1,488 @@ +0x12300000: 0x61040000: 3DSTATE_PIPELINE_SELECT +0x12300004: 0x79090000: 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP +0x12300008: 0x00000000: dword 1 +0x1230000c: 0x61020000: STATE_SIP +0x12300010: 0x00000000: dword 1 +0x12300014: 0x780b0000: 3DSTATE_VF_STATISTICS +0x12300018: 0x61010004: STATE_BASE_ADDRESS +0x1230001c: 0x00000001: general state base address 0x00000000 +0x12300020: 0x00000001: surface state base address 0x00000000 +0x12300024: 0x00000001: indirect state base address 0x00000000 +0x12300028: 0x00000001: general state upper bound disabled +0x1230002c: 0x00000001: indirect state upper bound disabled +0x12300030: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS +0x12300034: 0x00007e20: VS binding table +0x12300038: 0x00000000: GS binding table +0x1230003c: 0x00000000: Clip binding table +0x12300040: 0x00000000: SF binding table +0x12300044: 0x00007e20: WM binding table +0x12300048: 0x79010003: 3DSTATE_CONSTANT_COLOR +0x1230004c: 0x00000000: dword 1 +0x12300050: 0x00000000: dword 2 +0x12300054: 0x00000000: dword 3 +0x12300058: 0x00000000: dword 4 +0x1230005c: 0x79050003: 3DSTATE_DEPTH_BUFFER +0x12300060: 0x2c0805ff: 2D, z24s8, pitch = 1536 bytes, tiled +0x12300064: 0x00000000: depth offset +0x12300068: 0x09584ac0: 300x300 +0x1230006c: 0x00000000: volume depth +0x12300070: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300074: 0x00007d60: VS state +0x12300078: 0x00000000: GS state +0x1230007c: 0x00007d21: Clip state +0x12300080: 0x00007d80: SF state +0x12300084: 0x00007de0: WM state +0x12300088: 0x00007fc0: CC state +0x1230008c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300090: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300094: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x12300098: 0x60010000: CS_URB_STATE +0x1230009c: 0x00000024: entry_size: 2 [192 bytes], n_entries: 4 +0x123000a0: 0x79000002: 3DSTATE_DRAWING_RECTANGLE +0x123000a4: 0x00000000: top left: 0,0 +0x123000a8: 0x012b012b: bottom right: 299,299 +0x123000ac: 0x00000000: origin: 0,0 +0x123000b0: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x123000b4: 0x0000000c: buffer 0: sequential, pitch 12b +0x123000b8: 0x00000000: buffer address +0x123000bc: 0x00000000: max index +0x123000c0: 0x00000000: mbz +0x123000c4: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x123000c8: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123000cc: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123000d0: 0x60020100: CONSTANT_BUFFER: valid +0x123000d4: 0x00000001: offset: 0x00000000, length: 128 bytes +0x123000d8: 0x7b001804: 3DPRIMITIVE: tri fan sequential +0x123000dc: 0x00000004: vertex count +0x123000e0: 0x00000000: start vertex +0x123000e4: 0x00000001: instance count +0x123000e8: 0x00000000: start instance +0x123000ec: 0x00000000: index bias +0x123000f0: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS +0x123000f4: 0x00007b40: VS binding table +0x123000f8: 0x00000000: GS binding table +0x123000fc: 0x00000000: Clip binding table +0x12300100: 0x00000000: SF binding table +0x12300104: 0x00007b40: WM binding table +0x12300108: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x1230010c: 0x00007aa0: VS state +0x12300110: 0x00007a41: GS state +0x12300114: 0x00007a61: Clip state +0x12300118: 0x00007ac0: SF state +0x1230011c: 0x00007b00: WM state +0x12300120: 0x00007cc0: CC state +0x12300124: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300128: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x1230012c: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x12300130: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300134: 0x0000000c: buffer 0: sequential, pitch 12b +0x12300138: 0x00000000: buffer address +0x1230013c: 0x00000000: max index +0x12300140: 0x00000000: mbz +0x12300144: 0x60020100: CONSTANT_BUFFER: valid +0x12300148: 0x00000082: offset: 0x00000080, length: 192 bytes +0x1230014c: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300150: 0x00000052: vertex count +0x12300154: 0x00000000: start vertex +0x12300158: 0x00000001: instance count +0x1230015c: 0x00000000: start instance +0x12300160: 0x00000000: index bias +0x12300164: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300168: 0x00007aa0: VS state +0x1230016c: 0x00007a21: GS state +0x12300170: 0x00007a61: Clip state +0x12300174: 0x00007ac0: SF state +0x12300178: 0x00007b00: WM state +0x1230017c: 0x00007cc0: CC state +0x12300180: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300184: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300188: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230018c: 0x60020100: CONSTANT_BUFFER: valid +0x12300190: 0x00000082: offset: 0x00000080, length: 192 bytes +0x12300194: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300198: 0x00000050: vertex count +0x1230019c: 0x00000052: start vertex +0x123001a0: 0x00000001: instance count +0x123001a4: 0x00000000: start instance +0x123001a8: 0x00000000: index bias +0x123001ac: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123001b0: 0x00007aa0: VS state +0x123001b4: 0x00007a01: GS state +0x123001b8: 0x00007a61: Clip state +0x123001bc: 0x00007ac0: SF state +0x123001c0: 0x00007b00: WM state +0x123001c4: 0x00007cc0: CC state +0x123001c8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123001cc: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x123001d0: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x123001d4: 0x60020100: CONSTANT_BUFFER: valid +0x123001d8: 0x00000142: offset: 0x00000140, length: 192 bytes +0x123001dc: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x123001e0: 0x00000052: vertex count +0x123001e4: 0x000000a2: start vertex +0x123001e8: 0x00000001: instance count +0x123001ec: 0x00000000: start instance +0x123001f0: 0x00000000: index bias +0x123001f4: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123001f8: 0x00007aa0: VS state +0x123001fc: 0x000079e1: GS state +0x12300200: 0x00007a61: Clip state +0x12300204: 0x00007ac0: SF state +0x12300208: 0x00007b00: WM state +0x1230020c: 0x00007cc0: CC state +0x12300210: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300214: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300218: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230021c: 0x60020100: CONSTANT_BUFFER: valid +0x12300220: 0x00000142: offset: 0x00000140, length: 192 bytes +0x12300224: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300228: 0x00000050: vertex count +0x1230022c: 0x000000f4: start vertex +0x12300230: 0x00000001: instance count +0x12300234: 0x00000000: start instance +0x12300238: 0x00000000: index bias +0x1230023c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300240: 0x00007aa0: VS state +0x12300244: 0x000079c1: GS state +0x12300248: 0x00007a61: Clip state +0x1230024c: 0x00007ac0: SF state +0x12300250: 0x00007b00: WM state +0x12300254: 0x00007cc0: CC state +0x12300258: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230025c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300260: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x12300264: 0x60020100: CONSTANT_BUFFER: valid +0x12300268: 0x00000142: offset: 0x00000140, length: 192 bytes +0x1230026c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300270: 0x000079a0: VS state +0x12300274: 0x000079c1: GS state +0x12300278: 0x00007a61: Clip state +0x1230027c: 0x00007ac0: SF state +0x12300280: 0x00007b00: WM state +0x12300284: 0x00007cc0: CC state +0x12300288: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230028c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300290: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x12300294: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300298: 0x00000018: buffer 0: sequential, pitch 24b +0x1230029c: 0x00000f48: buffer address +0x123002a0: 0x00000000: max index +0x123002a4: 0x00000000: mbz +0x123002a8: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x123002ac: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123002b0: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123002b4: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x123002b8: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes +0x123002bc: 0x60020100: CONSTANT_BUFFER: valid +0x123002c0: 0x00000202: offset: 0x00000200, length: 192 bytes +0x123002c4: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x123002c8: 0x000000a2: vertex count +0x123002cc: 0x00000000: start vertex +0x123002d0: 0x00000001: instance count +0x123002d4: 0x00000000: start instance +0x123002d8: 0x00000000: index bias +0x123002dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123002e0: 0x000079a0: VS state +0x123002e4: 0x00000000: GS state +0x123002e8: 0x00007901: Clip state +0x123002ec: 0x00007940: SF state +0x123002f0: 0x00007960: WM state +0x123002f4: 0x00007cc0: CC state +0x123002f8: 0x00000000: MI_NOOP +0x123002fc: 0x00000000: MI_NOOP +0x12300300: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300304: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300308: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230030c: 0x60020100: CONSTANT_BUFFER: valid +0x12300310: 0x00000202: offset: 0x00000200, length: 192 bytes +0x12300314: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x12300318: 0x0000002a: vertex count +0x1230031c: 0x000000a2: start vertex +0x12300320: 0x00000001: instance count +0x12300324: 0x00000000: start instance +0x12300328: 0x00000000: index bias +0x1230032c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300330: 0x00007860: VS state +0x12300334: 0x00007801: GS state +0x12300338: 0x00007821: Clip state +0x1230033c: 0x00007880: SF state +0x12300340: 0x000078a0: WM state +0x12300344: 0x00007cc0: CC state +0x12300348: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230034c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300350: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x12300354: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300358: 0x0000000c: buffer 0: sequential, pitch 12b +0x1230035c: 0x00002268: buffer address +0x12300360: 0x00000000: max index +0x12300364: 0x00000000: mbz +0x12300368: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x1230036c: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x12300370: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x12300374: 0x60020100: CONSTANT_BUFFER: valid +0x12300378: 0x000002c2: offset: 0x000002c0, length: 192 bytes +0x1230037c: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300380: 0x0000002a: vertex count +0x12300384: 0x00000000: start vertex +0x12300388: 0x00000001: instance count +0x1230038c: 0x00000000: start instance +0x12300390: 0x00000000: index bias +0x12300394: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300398: 0x00007860: VS state +0x1230039c: 0x000077e1: GS state +0x123003a0: 0x00007821: Clip state +0x123003a4: 0x00007880: SF state +0x123003a8: 0x000078a0: WM state +0x123003ac: 0x00007cc0: CC state +0x123003b0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123003b4: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x123003b8: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x123003bc: 0x60020100: CONSTANT_BUFFER: valid +0x123003c0: 0x000002c2: offset: 0x000002c0, length: 192 bytes +0x123003c4: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x123003c8: 0x00000028: vertex count +0x123003cc: 0x0000002a: start vertex +0x123003d0: 0x00000001: instance count +0x123003d4: 0x00000000: start instance +0x123003d8: 0x00000000: index bias +0x123003dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123003e0: 0x00007860: VS state +0x123003e4: 0x000077c1: GS state +0x123003e8: 0x00007821: Clip state +0x123003ec: 0x00007880: SF state +0x123003f0: 0x000078a0: WM state +0x123003f4: 0x00007cc0: CC state +0x123003f8: 0x00000000: MI_NOOP +0x123003fc: 0x00000000: MI_NOOP +0x12300400: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300404: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300408: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230040c: 0x60020100: CONSTANT_BUFFER: valid +0x12300410: 0x00000382: offset: 0x00000380, length: 192 bytes +0x12300414: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300418: 0x0000002a: vertex count +0x1230041c: 0x00000052: start vertex +0x12300420: 0x00000001: instance count +0x12300424: 0x00000000: start instance +0x12300428: 0x00000000: index bias +0x1230042c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300430: 0x00007860: VS state +0x12300434: 0x000077a1: GS state +0x12300438: 0x00007821: Clip state +0x1230043c: 0x00007880: SF state +0x12300440: 0x000078a0: WM state +0x12300444: 0x00007cc0: CC state +0x12300448: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230044c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300450: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x12300454: 0x60020100: CONSTANT_BUFFER: valid +0x12300458: 0x00000382: offset: 0x00000380, length: 192 bytes +0x1230045c: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300460: 0x00000028: vertex count +0x12300464: 0x0000007c: start vertex +0x12300468: 0x00000001: instance count +0x1230046c: 0x00000000: start instance +0x12300470: 0x00000000: index bias +0x12300474: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300478: 0x00007860: VS state +0x1230047c: 0x00007781: GS state +0x12300480: 0x00007821: Clip state +0x12300484: 0x00007880: SF state +0x12300488: 0x000078a0: WM state +0x1230048c: 0x00007cc0: CC state +0x12300490: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300494: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300498: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230049c: 0x60020100: CONSTANT_BUFFER: valid +0x123004a0: 0x00000382: offset: 0x00000380, length: 192 bytes +0x123004a4: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123004a8: 0x00007760: VS state +0x123004ac: 0x00007781: GS state +0x123004b0: 0x00007821: Clip state +0x123004b4: 0x00007880: SF state +0x123004b8: 0x000078a0: WM state +0x123004bc: 0x00007cc0: CC state +0x123004c0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123004c4: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x123004c8: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x123004cc: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x123004d0: 0x00000018: buffer 0: sequential, pitch 24b +0x123004d4: 0x00002a30: buffer address +0x123004d8: 0x00000000: max index +0x123004dc: 0x00000000: mbz +0x123004e0: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x123004e4: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123004e8: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123004ec: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x123004f0: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes +0x123004f4: 0x60020100: CONSTANT_BUFFER: valid +0x123004f8: 0x00000442: offset: 0x00000440, length: 192 bytes +0x123004fc: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300500: 0x00000052: vertex count +0x12300504: 0x00000000: start vertex +0x12300508: 0x00000001: instance count +0x1230050c: 0x00000000: start instance +0x12300510: 0x00000000: index bias +0x12300514: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300518: 0x00007760: VS state +0x1230051c: 0x00000000: GS state +0x12300520: 0x000076c1: Clip state +0x12300524: 0x00007700: SF state +0x12300528: 0x00007720: WM state +0x1230052c: 0x00007cc0: CC state +0x12300530: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300534: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300538: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230053c: 0x60020100: CONSTANT_BUFFER: valid +0x12300540: 0x00000442: offset: 0x00000440, length: 192 bytes +0x12300544: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x12300548: 0x00000016: vertex count +0x1230054c: 0x00000052: start vertex +0x12300550: 0x00000001: instance count +0x12300554: 0x00000000: start instance +0x12300558: 0x00000000: index bias +0x1230055c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300560: 0x00007620: VS state +0x12300564: 0x000075c1: GS state +0x12300568: 0x000075e1: Clip state +0x1230056c: 0x00007640: SF state +0x12300570: 0x00007660: WM state +0x12300574: 0x00007cc0: CC state +0x12300578: 0x00000000: MI_NOOP +0x1230057c: 0x00000000: MI_NOOP +0x12300580: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300584: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300588: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230058c: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300590: 0x0000000c: buffer 0: sequential, pitch 12b +0x12300594: 0x000033f0: buffer address +0x12300598: 0x00000000: max index +0x1230059c: 0x00000000: mbz +0x123005a0: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x123005a4: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123005a8: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123005ac: 0x60020100: CONSTANT_BUFFER: valid +0x123005b0: 0x00000502: offset: 0x00000500, length: 192 bytes +0x123005b4: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x123005b8: 0x0000002a: vertex count +0x123005bc: 0x00000000: start vertex +0x123005c0: 0x00000001: instance count +0x123005c4: 0x00000000: start instance +0x123005c8: 0x00000000: index bias +0x123005cc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123005d0: 0x00007620: VS state +0x123005d4: 0x000075a1: GS state +0x123005d8: 0x000075e1: Clip state +0x123005dc: 0x00007640: SF state +0x123005e0: 0x00007660: WM state +0x123005e4: 0x00007cc0: CC state +0x123005e8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123005ec: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x123005f0: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x123005f4: 0x60020100: CONSTANT_BUFFER: valid +0x123005f8: 0x00000502: offset: 0x00000500, length: 192 bytes +0x123005fc: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300600: 0x00000028: vertex count +0x12300604: 0x0000002a: start vertex +0x12300608: 0x00000001: instance count +0x1230060c: 0x00000000: start instance +0x12300610: 0x00000000: index bias +0x12300614: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300618: 0x00007620: VS state +0x1230061c: 0x00007581: GS state +0x12300620: 0x000075e1: Clip state +0x12300624: 0x00007640: SF state +0x12300628: 0x00007660: WM state +0x1230062c: 0x00007cc0: CC state +0x12300630: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300634: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300638: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230063c: 0x60020100: CONSTANT_BUFFER: valid +0x12300640: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x12300644: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300648: 0x0000002a: vertex count +0x1230064c: 0x00000052: start vertex +0x12300650: 0x00000001: instance count +0x12300654: 0x00000000: start instance +0x12300658: 0x00000000: index bias +0x1230065c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300660: 0x00007620: VS state +0x12300664: 0x00007561: GS state +0x12300668: 0x000075e1: Clip state +0x1230066c: 0x00007640: SF state +0x12300670: 0x00007660: WM state +0x12300674: 0x00007cc0: CC state +0x12300678: 0x00000000: MI_NOOP +0x1230067c: 0x00000000: MI_NOOP +0x12300680: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300684: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300688: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230068c: 0x60020100: CONSTANT_BUFFER: valid +0x12300690: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x12300694: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300698: 0x00000028: vertex count +0x1230069c: 0x0000007c: start vertex +0x123006a0: 0x00000001: instance count +0x123006a4: 0x00000000: start instance +0x123006a8: 0x00000000: index bias +0x123006ac: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123006b0: 0x00007620: VS state +0x123006b4: 0x00007541: GS state +0x123006b8: 0x000075e1: Clip state +0x123006bc: 0x00007640: SF state +0x123006c0: 0x00007660: WM state +0x123006c4: 0x00007cc0: CC state +0x123006c8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123006cc: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x123006d0: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x123006d4: 0x60020100: CONSTANT_BUFFER: valid +0x123006d8: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x123006dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123006e0: 0x00007520: VS state +0x123006e4: 0x00007541: GS state +0x123006e8: 0x000075e1: Clip state +0x123006ec: 0x00007640: SF state +0x123006f0: 0x00007660: WM state +0x123006f4: 0x00007cc0: CC state +0x123006f8: 0x00000000: MI_NOOP +0x123006fc: 0x00000000: MI_NOOP +0x12300700: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300704: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300708: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230070c: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300710: 0x00000018: buffer 0: sequential, pitch 24b +0x12300714: 0x00003bb8: buffer address +0x12300718: 0x00000000: max index +0x1230071c: 0x00000000: mbz +0x12300720: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x12300724: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x12300728: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x1230072c: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x12300730: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes +0x12300734: 0x60020100: CONSTANT_BUFFER: valid +0x12300738: 0x00000682: offset: 0x00000680, length: 192 bytes +0x1230073c: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300740: 0x00000052: vertex count +0x12300744: 0x00000000: start vertex +0x12300748: 0x00000001: instance count +0x1230074c: 0x00000000: start instance +0x12300750: 0x00000000: index bias +0x12300754: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300758: 0x00007520: VS state +0x1230075c: 0x00000000: GS state +0x12300760: 0x00007481: Clip state +0x12300764: 0x000074c0: SF state +0x12300768: 0x000074e0: WM state +0x1230076c: 0x00007cc0: CC state +0x12300770: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300774: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300778: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230077c: 0x60020100: CONSTANT_BUFFER: valid +0x12300780: 0x00000682: offset: 0x00000680, length: 192 bytes +0x12300784: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x12300788: 0x00000016: vertex count +0x1230078c: 0x00000052: start vertex +0x12300790: 0x00000001: instance count +0x12300794: 0x00000000: start instance +0x12300798: 0x00000000: index bias +0x1230079c: 0x05000000: MI_BATCH_BUFFER_END diff --git a/intel/tests/gen4-3d.batch.sh b/intel/tests/gen4-3d.batch.sh new file mode 100644 index 0000000..a94057f --- /dev/null +++ b/intel/tests/gen4-3d.batch.sh @@ -0,0 +1,20 @@ +#!/bin/sh + +TEST_FILENAME=`echo "$0" | sed 's|.sh||'` +./test_decode $TEST_FILENAME + +ret=$? + +# pretty-print a diff showing what happened, and leave the dumped +# around for possibly moving over the ref. +if test $ret = 1; then + REF_FILENAME="$TEST_FILENAME-ref.txt" + NEW_FILENAME="$TEST_FILENAME-new.txt" + ./test_decode $TEST_FILENAME -dump > $NEW_FILENAME + if test $? = 0; then + echo "Differences:" + diff -u $REF_FILENAME $NEW_FILENAME + fi +fi + +exit $ret diff --git a/intel/tests/gen5-3d.batch b/intel/tests/gen5-3d.batch new file mode 100644 index 0000000000000000000000000000000000000000..cf9d8d8e2552984640301c8d7517f89fd737937a GIT binary patch literal 2048 zcma)6Jx|;~5S{h;5GRljBtjGvK12~gibyF_#D^#l6{4c_b{K;lfRLmEiy>{WG7wBx3Fi}=mxoeN+P}ewR%&Gc zf$!*d?(cJ);R60TkpB*gFp~7x9ogAV(>&dhJU%{aQLIf#j}S~ezZPt#Sf&Bi9)caO ze{-;2(D5eqlb>Q*es6Oy$0eA>T8V{`)dc^#81{by0S7D4g6)6H)55Z+i2y=k?W~)l zw2!JZyu%#B5}1GY8s}>i^(*dYNq6wFs;3FmX<%L0E$jhCT)%#&rPHmvmZGkoYz@rC zQC0(Uyzkn?c_5w8UJGHMz)Jv1&9#tYHJJCy&>>9`u`H)o6&kdJVB~Evlgi o{&g`Ixh<<~_s@72Z9slF|N&o-= literal 0 HcmV?d00001 diff --git a/intel/tests/gen5-3d.batch-ref.txt b/intel/tests/gen5-3d.batch-ref.txt new file mode 100644 index 0000000..a0271ab --- /dev/null +++ b/intel/tests/gen5-3d.batch-ref.txt @@ -0,0 +1,512 @@ +0x12300000: 0x69040000: 3DSTATE_PIPELINE_SELECT +0x12300004: 0x79090000: 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP +0x12300008: 0x00000000: dword 1 +0x1230000c: 0x61020000: STATE_SIP +0x12300010: 0x00000000: dword 1 +0x12300014: 0x680b0000: 3DSTATE_VF_STATISTICS +0x12300018: 0x61010006: STATE_BASE_ADDRESS +0x1230001c: 0x00000001: general state base address 0x00000000 +0x12300020: 0x00000001: surface state base address 0x00000000 +0x12300024: 0x00000001: indirect state base address 0x00000000 +0x12300028: 0x00000001: instruction state base address 0x00000000 +0x1230002c: 0x00000001: general state upper bound disabled +0x12300030: 0x00000001: indirect state upper bound disabled +0x12300034: 0x00000001: instruction state upper bound disabled +0x12300038: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS +0x1230003c: 0x00007e20: VS binding table +0x12300040: 0x00000000: GS binding table +0x12300044: 0x00000000: Clip binding table +0x12300048: 0x00000000: SF binding table +0x1230004c: 0x00007e20: WM binding table +0x12300050: 0x79010003: 3DSTATE_CONSTANT_COLOR +0x12300054: 0x00000000: dword 1 +0x12300058: 0x00000000: dword 2 +0x1230005c: 0x00000000: dword 3 +0x12300060: 0x00000000: dword 4 +0x12300064: 0x79050004: 3DSTATE_DEPTH_BUFFER +0x12300068: 0x2c0805ff: 2D, z24s8, pitch = 1536 bytes, tiled, HiZ 0, Seperate Stencil 0 +0x1230006c: 0x00000000: depth offset +0x12300070: 0x09584ac0: 300x300 +0x12300074: 0x00000000: volume depth +0x12300078: 0x00000000: +0x1230007c: 0x02000000: MI_FLUSH +0x12300080: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300084: 0x00007d60: VS state +0x12300088: 0x00000000: GS state +0x1230008c: 0x00007d21: Clip state +0x12300090: 0x00007d80: SF state +0x12300094: 0x00007de0: WM state +0x12300098: 0x00007fc0: CC state +0x1230009c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123000a0: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123000a4: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123000a8: 0x60010000: CS_URB_STATE +0x123000ac: 0x00000024: entry_size: 2 [192 bytes], n_entries: 4 +0x123000b0: 0x79000002: 3DSTATE_DRAWING_RECTANGLE +0x123000b4: 0x00000000: top left: 0,0 +0x123000b8: 0x012b012b: bottom right: 299,299 +0x123000bc: 0x00000000: origin: 0,0 +0x123000c0: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x123000c4: 0x0000000c: buffer 0: sequential, pitch 12b +0x123000c8: 0x00000000: buffer address +0x123000cc: 0x0000ffff: max index +0x123000d0: 0x00000000: mbz +0x123000d4: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x123000d8: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123000dc: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123000e0: 0x60020100: CONSTANT_BUFFER: valid +0x123000e4: 0x00000001: offset: 0x00000000, length: 128 bytes +0x123000e8: 0x7b001804: 3DPRIMITIVE: tri fan sequential +0x123000ec: 0x00000004: vertex count +0x123000f0: 0x00000000: start vertex +0x123000f4: 0x00000001: instance count +0x123000f8: 0x00000000: start instance +0x123000fc: 0x00000000: index bias +0x12300100: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS +0x12300104: 0x00007b40: VS binding table +0x12300108: 0x00000000: GS binding table +0x1230010c: 0x00000000: Clip binding table +0x12300110: 0x00000000: SF binding table +0x12300114: 0x00007b40: WM binding table +0x12300118: 0x02000000: MI_FLUSH +0x1230011c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300120: 0x00007aa0: VS state +0x12300124: 0x00007a41: GS state +0x12300128: 0x00007a61: Clip state +0x1230012c: 0x00007ac0: SF state +0x12300130: 0x00007b00: WM state +0x12300134: 0x00007cc0: CC state +0x12300138: 0x00000000: MI_NOOP +0x1230013c: 0x00000000: MI_NOOP +0x12300140: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300144: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300148: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x1230014c: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300150: 0x0000000c: buffer 0: sequential, pitch 12b +0x12300154: 0x00000000: buffer address +0x12300158: 0x00007fff: max index +0x1230015c: 0x00000000: mbz +0x12300160: 0x60020100: CONSTANT_BUFFER: valid +0x12300164: 0x00000082: offset: 0x00000080, length: 192 bytes +0x12300168: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x1230016c: 0x00000052: vertex count +0x12300170: 0x00000000: start vertex +0x12300174: 0x00000001: instance count +0x12300178: 0x00000000: start instance +0x1230017c: 0x00000000: index bias +0x12300180: 0x02000000: MI_FLUSH +0x12300184: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300188: 0x00007aa0: VS state +0x1230018c: 0x00007a21: GS state +0x12300190: 0x00007a61: Clip state +0x12300194: 0x00007ac0: SF state +0x12300198: 0x00007b00: WM state +0x1230019c: 0x00007cc0: CC state +0x123001a0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123001a4: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123001a8: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123001ac: 0x60020100: CONSTANT_BUFFER: valid +0x123001b0: 0x00000082: offset: 0x00000080, length: 192 bytes +0x123001b4: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x123001b8: 0x00000050: vertex count +0x123001bc: 0x00000052: start vertex +0x123001c0: 0x00000001: instance count +0x123001c4: 0x00000000: start instance +0x123001c8: 0x00000000: index bias +0x123001cc: 0x02000000: MI_FLUSH +0x123001d0: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123001d4: 0x00007aa0: VS state +0x123001d8: 0x00007a01: GS state +0x123001dc: 0x00007a61: Clip state +0x123001e0: 0x00007ac0: SF state +0x123001e4: 0x00007b00: WM state +0x123001e8: 0x00007cc0: CC state +0x123001ec: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123001f0: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123001f4: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123001f8: 0x60020100: CONSTANT_BUFFER: valid +0x123001fc: 0x00000142: offset: 0x00000140, length: 192 bytes +0x12300200: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300204: 0x00000052: vertex count +0x12300208: 0x000000a2: start vertex +0x1230020c: 0x00000001: instance count +0x12300210: 0x00000000: start instance +0x12300214: 0x00000000: index bias +0x12300218: 0x02000000: MI_FLUSH +0x1230021c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300220: 0x00007aa0: VS state +0x12300224: 0x000079e1: GS state +0x12300228: 0x00007a61: Clip state +0x1230022c: 0x00007ac0: SF state +0x12300230: 0x00007b00: WM state +0x12300234: 0x00007cc0: CC state +0x12300238: 0x00000000: MI_NOOP +0x1230023c: 0x00000000: MI_NOOP +0x12300240: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300244: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300248: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x1230024c: 0x60020100: CONSTANT_BUFFER: valid +0x12300250: 0x00000142: offset: 0x00000140, length: 192 bytes +0x12300254: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300258: 0x00000050: vertex count +0x1230025c: 0x000000f4: start vertex +0x12300260: 0x00000001: instance count +0x12300264: 0x00000000: start instance +0x12300268: 0x00000000: index bias +0x1230026c: 0x02000000: MI_FLUSH +0x12300270: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300274: 0x00007aa0: VS state +0x12300278: 0x000079c1: GS state +0x1230027c: 0x00007a61: Clip state +0x12300280: 0x00007ac0: SF state +0x12300284: 0x00007b00: WM state +0x12300288: 0x00007cc0: CC state +0x1230028c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300290: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300294: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300298: 0x60020100: CONSTANT_BUFFER: valid +0x1230029c: 0x00000142: offset: 0x00000140, length: 192 bytes +0x123002a0: 0x02000000: MI_FLUSH +0x123002a4: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123002a8: 0x000079a0: VS state +0x123002ac: 0x000079c1: GS state +0x123002b0: 0x00007a61: Clip state +0x123002b4: 0x00007ac0: SF state +0x123002b8: 0x00007b00: WM state +0x123002bc: 0x00007cc0: CC state +0x123002c0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123002c4: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123002c8: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123002cc: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x123002d0: 0x00000018: buffer 0: sequential, pitch 24b +0x123002d4: 0x00000f48: buffer address +0x123002d8: 0x00007fff: max index +0x123002dc: 0x00000000: mbz +0x123002e0: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x123002e4: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123002e8: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123002ec: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x123002f0: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123002f4: 0x60020100: CONSTANT_BUFFER: valid +0x123002f8: 0x00000202: offset: 0x00000200, length: 192 bytes +0x123002fc: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300300: 0x000000a2: vertex count +0x12300304: 0x00000000: start vertex +0x12300308: 0x00000001: instance count +0x1230030c: 0x00000000: start instance +0x12300310: 0x00000000: index bias +0x12300314: 0x02000000: MI_FLUSH +0x12300318: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x1230031c: 0x000079a0: VS state +0x12300320: 0x00000000: GS state +0x12300324: 0x00007901: Clip state +0x12300328: 0x00007940: SF state +0x1230032c: 0x00007960: WM state +0x12300330: 0x00007cc0: CC state +0x12300334: 0x00000000: MI_NOOP +0x12300338: 0x00000000: MI_NOOP +0x1230033c: 0x00000000: MI_NOOP +0x12300340: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300344: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300348: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x1230034c: 0x60020100: CONSTANT_BUFFER: valid +0x12300350: 0x00000202: offset: 0x00000200, length: 192 bytes +0x12300354: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x12300358: 0x0000002a: vertex count +0x1230035c: 0x000000a2: start vertex +0x12300360: 0x00000001: instance count +0x12300364: 0x00000000: start instance +0x12300368: 0x00000000: index bias +0x1230036c: 0x02000000: MI_FLUSH +0x12300370: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300374: 0x00007860: VS state +0x12300378: 0x00007801: GS state +0x1230037c: 0x00007821: Clip state +0x12300380: 0x00007880: SF state +0x12300384: 0x000078a0: WM state +0x12300388: 0x00007cc0: CC state +0x1230038c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300390: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300394: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300398: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x1230039c: 0x0000000c: buffer 0: sequential, pitch 12b +0x123003a0: 0x00002268: buffer address +0x123003a4: 0x00007fff: max index +0x123003a8: 0x00000000: mbz +0x123003ac: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x123003b0: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123003b4: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123003b8: 0x60020100: CONSTANT_BUFFER: valid +0x123003bc: 0x000002c2: offset: 0x000002c0, length: 192 bytes +0x123003c0: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x123003c4: 0x0000002a: vertex count +0x123003c8: 0x00000000: start vertex +0x123003cc: 0x00000001: instance count +0x123003d0: 0x00000000: start instance +0x123003d4: 0x00000000: index bias +0x123003d8: 0x02000000: MI_FLUSH +0x123003dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123003e0: 0x00007860: VS state +0x123003e4: 0x000077e1: GS state +0x123003e8: 0x00007821: Clip state +0x123003ec: 0x00007880: SF state +0x123003f0: 0x000078a0: WM state +0x123003f4: 0x00007cc0: CC state +0x123003f8: 0x00000000: MI_NOOP +0x123003fc: 0x00000000: MI_NOOP +0x12300400: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300404: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300408: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x1230040c: 0x60020100: CONSTANT_BUFFER: valid +0x12300410: 0x000002c2: offset: 0x000002c0, length: 192 bytes +0x12300414: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300418: 0x00000028: vertex count +0x1230041c: 0x0000002a: start vertex +0x12300420: 0x00000001: instance count +0x12300424: 0x00000000: start instance +0x12300428: 0x00000000: index bias +0x1230042c: 0x02000000: MI_FLUSH +0x12300430: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300434: 0x00007860: VS state +0x12300438: 0x000077c1: GS state +0x1230043c: 0x00007821: Clip state +0x12300440: 0x00007880: SF state +0x12300444: 0x000078a0: WM state +0x12300448: 0x00007cc0: CC state +0x1230044c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300450: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300454: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300458: 0x60020100: CONSTANT_BUFFER: valid +0x1230045c: 0x00000382: offset: 0x00000380, length: 192 bytes +0x12300460: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300464: 0x0000002a: vertex count +0x12300468: 0x00000052: start vertex +0x1230046c: 0x00000001: instance count +0x12300470: 0x00000000: start instance +0x12300474: 0x00000000: index bias +0x12300478: 0x02000000: MI_FLUSH +0x1230047c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300480: 0x00007860: VS state +0x12300484: 0x000077a1: GS state +0x12300488: 0x00007821: Clip state +0x1230048c: 0x00007880: SF state +0x12300490: 0x000078a0: WM state +0x12300494: 0x00007cc0: CC state +0x12300498: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230049c: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123004a0: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123004a4: 0x60020100: CONSTANT_BUFFER: valid +0x123004a8: 0x00000382: offset: 0x00000380, length: 192 bytes +0x123004ac: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x123004b0: 0x00000028: vertex count +0x123004b4: 0x0000007c: start vertex +0x123004b8: 0x00000001: instance count +0x123004bc: 0x00000000: start instance +0x123004c0: 0x00000000: index bias +0x123004c4: 0x02000000: MI_FLUSH +0x123004c8: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123004cc: 0x00007860: VS state +0x123004d0: 0x00007781: GS state +0x123004d4: 0x00007821: Clip state +0x123004d8: 0x00007880: SF state +0x123004dc: 0x000078a0: WM state +0x123004e0: 0x00007cc0: CC state +0x123004e4: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123004e8: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123004ec: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123004f0: 0x60020100: CONSTANT_BUFFER: valid +0x123004f4: 0x00000382: offset: 0x00000380, length: 192 bytes +0x123004f8: 0x02000000: MI_FLUSH +0x123004fc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300500: 0x00007760: VS state +0x12300504: 0x00007781: GS state +0x12300508: 0x00007821: Clip state +0x1230050c: 0x00007880: SF state +0x12300510: 0x000078a0: WM state +0x12300514: 0x00007cc0: CC state +0x12300518: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230051c: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300520: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300524: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300528: 0x00000018: buffer 0: sequential, pitch 24b +0x1230052c: 0x00002a30: buffer address +0x12300530: 0x00007fff: max index +0x12300534: 0x00000000: mbz +0x12300538: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x1230053c: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x12300540: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x12300544: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x12300548: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x1230054c: 0x60020100: CONSTANT_BUFFER: valid +0x12300550: 0x00000442: offset: 0x00000440, length: 192 bytes +0x12300554: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300558: 0x00000052: vertex count +0x1230055c: 0x00000000: start vertex +0x12300560: 0x00000001: instance count +0x12300564: 0x00000000: start instance +0x12300568: 0x00000000: index bias +0x1230056c: 0x02000000: MI_FLUSH +0x12300570: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300574: 0x00007760: VS state +0x12300578: 0x00000000: GS state +0x1230057c: 0x000076c1: Clip state +0x12300580: 0x00007700: SF state +0x12300584: 0x00007720: WM state +0x12300588: 0x00007cc0: CC state +0x1230058c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300590: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300594: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300598: 0x60020100: CONSTANT_BUFFER: valid +0x1230059c: 0x00000442: offset: 0x00000440, length: 192 bytes +0x123005a0: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x123005a4: 0x00000016: vertex count +0x123005a8: 0x00000052: start vertex +0x123005ac: 0x00000001: instance count +0x123005b0: 0x00000000: start instance +0x123005b4: 0x00000000: index bias +0x123005b8: 0x02000000: MI_FLUSH +0x123005bc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123005c0: 0x00007620: VS state +0x123005c4: 0x000075c1: GS state +0x123005c8: 0x000075e1: Clip state +0x123005cc: 0x00007640: SF state +0x123005d0: 0x00007660: WM state +0x123005d4: 0x00007cc0: CC state +0x123005d8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123005dc: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123005e0: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123005e4: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x123005e8: 0x0000000c: buffer 0: sequential, pitch 12b +0x123005ec: 0x000033f0: buffer address +0x123005f0: 0x00007fff: max index +0x123005f4: 0x00000000: mbz +0x123005f8: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x123005fc: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x12300600: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x12300604: 0x60020100: CONSTANT_BUFFER: valid +0x12300608: 0x00000502: offset: 0x00000500, length: 192 bytes +0x1230060c: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300610: 0x0000002a: vertex count +0x12300614: 0x00000000: start vertex +0x12300618: 0x00000001: instance count +0x1230061c: 0x00000000: start instance +0x12300620: 0x00000000: index bias +0x12300624: 0x02000000: MI_FLUSH +0x12300628: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x1230062c: 0x00007620: VS state +0x12300630: 0x000075a1: GS state +0x12300634: 0x000075e1: Clip state +0x12300638: 0x00007640: SF state +0x1230063c: 0x00007660: WM state +0x12300640: 0x00007cc0: CC state +0x12300644: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300648: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x1230064c: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300650: 0x60020100: CONSTANT_BUFFER: valid +0x12300654: 0x00000502: offset: 0x00000500, length: 192 bytes +0x12300658: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x1230065c: 0x00000028: vertex count +0x12300660: 0x0000002a: start vertex +0x12300664: 0x00000001: instance count +0x12300668: 0x00000000: start instance +0x1230066c: 0x00000000: index bias +0x12300670: 0x02000000: MI_FLUSH +0x12300674: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300678: 0x00007620: VS state +0x1230067c: 0x00007581: GS state +0x12300680: 0x000075e1: Clip state +0x12300684: 0x00007640: SF state +0x12300688: 0x00007660: WM state +0x1230068c: 0x00007cc0: CC state +0x12300690: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300694: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300698: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x1230069c: 0x60020100: CONSTANT_BUFFER: valid +0x123006a0: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x123006a4: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x123006a8: 0x0000002a: vertex count +0x123006ac: 0x00000052: start vertex +0x123006b0: 0x00000001: instance count +0x123006b4: 0x00000000: start instance +0x123006b8: 0x00000000: index bias +0x123006bc: 0x02000000: MI_FLUSH +0x123006c0: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123006c4: 0x00007620: VS state +0x123006c8: 0x00007561: GS state +0x123006cc: 0x000075e1: Clip state +0x123006d0: 0x00007640: SF state +0x123006d4: 0x00007660: WM state +0x123006d8: 0x00007cc0: CC state +0x123006dc: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123006e0: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123006e4: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123006e8: 0x60020100: CONSTANT_BUFFER: valid +0x123006ec: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x123006f0: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x123006f4: 0x00000028: vertex count +0x123006f8: 0x0000007c: start vertex +0x123006fc: 0x00000001: instance count +0x12300700: 0x00000000: start instance +0x12300704: 0x00000000: index bias +0x12300708: 0x02000000: MI_FLUSH +0x1230070c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300710: 0x00007620: VS state +0x12300714: 0x00007541: GS state +0x12300718: 0x000075e1: Clip state +0x1230071c: 0x00007640: SF state +0x12300720: 0x00007660: WM state +0x12300724: 0x00007cc0: CC state +0x12300728: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230072c: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300730: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300734: 0x60020100: CONSTANT_BUFFER: valid +0x12300738: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x1230073c: 0x02000000: MI_FLUSH +0x12300740: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300744: 0x00007520: VS state +0x12300748: 0x00007541: GS state +0x1230074c: 0x000075e1: Clip state +0x12300750: 0x00007640: SF state +0x12300754: 0x00007660: WM state +0x12300758: 0x00007cc0: CC state +0x1230075c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300760: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300764: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300768: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x1230076c: 0x00000018: buffer 0: sequential, pitch 24b +0x12300770: 0x00003bb8: buffer address +0x12300774: 0x00007fff: max index +0x12300778: 0x00000000: mbz +0x1230077c: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x12300780: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x12300784: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x12300788: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x1230078c: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x12300790: 0x60020100: CONSTANT_BUFFER: valid +0x12300794: 0x00000682: offset: 0x00000680, length: 192 bytes +0x12300798: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x1230079c: 0x00000052: vertex count +0x123007a0: 0x00000000: start vertex +0x123007a4: 0x00000001: instance count +0x123007a8: 0x00000000: start instance +0x123007ac: 0x00000000: index bias +0x123007b0: 0x02000000: MI_FLUSH +0x123007b4: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123007b8: 0x00007520: VS state +0x123007bc: 0x00000000: GS state +0x123007c0: 0x00007481: Clip state +0x123007c4: 0x000074c0: SF state +0x123007c8: 0x000074e0: WM state +0x123007cc: 0x00007cc0: CC state +0x123007d0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123007d4: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123007d8: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123007dc: 0x60020100: CONSTANT_BUFFER: valid +0x123007e0: 0x00000682: offset: 0x00000680, length: 192 bytes +0x123007e4: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x123007e8: 0x00000016: vertex count +0x123007ec: 0x00000052: start vertex +0x123007f0: 0x00000001: instance count +0x123007f4: 0x00000000: start instance +0x123007f8: 0x00000000: index bias +0x123007fc: 0x05000000: MI_BATCH_BUFFER_END diff --git a/intel/tests/gen5-3d.batch.sh b/intel/tests/gen5-3d.batch.sh new file mode 100644 index 0000000..a94057f --- /dev/null +++ b/intel/tests/gen5-3d.batch.sh @@ -0,0 +1,20 @@ +#!/bin/sh + +TEST_FILENAME=`echo "$0" | sed 's|.sh||'` +./test_decode $TEST_FILENAME + +ret=$? + +# pretty-print a diff showing what happened, and leave the dumped +# around for possibly moving over the ref. +if test $ret = 1; then + REF_FILENAME="$TEST_FILENAME-ref.txt" + NEW_FILENAME="$TEST_FILENAME-new.txt" + ./test_decode $TEST_FILENAME -dump > $NEW_FILENAME + if test $? = 0; then + echo "Differences:" + diff -u $REF_FILENAME $NEW_FILENAME + fi +fi + +exit $ret diff --git a/intel/tests/gen6-3d.batch b/intel/tests/gen6-3d.batch new file mode 100644 index 0000000000000000000000000000000000000000..d57147e9a338c513030c39b481a45de935d8511a GIT binary patch literal 3960 zcmd5;y>8S%5FW4X;3z-m%d&De_QL{Usa3TsMa#bfZ)qqSis>1huO zMJs2r8OW~ttmmwg!umkgxZ#lJL@R@cyhFZo9;@9oJv}9wfWLx03bi?evx?UBCzgS4 zf>l>(zFo+tt=yXB0mXS)6q6UwF~=adEGLP4+Rp1?E2NE_jBSU|kfKeE%jpu)m+8!> zP3r16>XQ!{XfKNBj+xbb`0RvZ(iZzi1mDm z^r}5Eo23(vmJ#a&N4pzAk49-2Q@mJJytj;nAMc?9KmB-1e;$cuI&$v$#*>Ends1K%~Pow+k z6!FU_*rm}uEP2nBa~yvbtZ6Eab^R0{z7=d0AAT3)E=~+C-a)}38+ok6is?k+<OSBIlH)Tykd=vnu=*%p9KrW9w$EF(~kCj;YhrY3m^F^$bF!9`do5h4;nT=r0Z%G?*$>nsB ze~f2v&$9H5U)M8iE!;N-?ZmVa3v+tq!hPe(IsW{w{~M2Ct7YjM-*05Ot@_`n>>H2T S@x6`ua4oIGO3l83yTd $NEW_FILENAME + if test $? = 0; then + echo "Differences:" + diff -u $REF_FILENAME $NEW_FILENAME + fi +fi + +exit $ret diff --git a/intel/tests/gen7-2d-copy.batch b/intel/tests/gen7-2d-copy.batch new file mode 100644 index 0000000000000000000000000000000000000000..ce7fc292b5d01010762d64d44098ae3c6dbdafc4 GIT binary patch literal 56 qcmZQ;_z*II@eDHq5TpPh!vsAc5W4|H2>fSaVqg#kF_8c(hz$T0j|Of4 literal 0 HcmV?d00001 diff --git a/intel/tests/gen7-2d-copy.batch-ref.txt b/intel/tests/gen7-2d-copy.batch-ref.txt new file mode 100644 index 0000000..0d621d3 --- /dev/null +++ b/intel/tests/gen7-2d-copy.batch-ref.txt @@ -0,0 +1,14 @@ +0x12300000: 0x54f08006: XY_SRC_COPY_BLT (rgb enabled, alpha enabled, src tile 1, dst tile 0) +0x12300004: 0x03cc0190: format 8888, pitch 400, rop 0xcc, clipping disabled, +0x12300008: 0x00000000: dst (0,0) +0x1230000c: 0x00640064: dst (100,100) +0x12300010: 0x122e9000: dst offset 0x122e9000 +0x12300014: 0x00000000: src (0,0) +0x12300018: 0x00000080: src pitch 128 +0x1230001c: 0x02ff1000: src offset 0x02ff1000 +0x12300020: 0x13000002: MI_FLUSH_DW post_sync_op='no write' +0x12300024: 0x00000000: address +0x12300028: 0x00000000: dword +0x1230002c: 0x00000000: upper dword +0x12300030: 0x05000000: MI_BATCH_BUFFER_END +0x12300034: 0x00000000: diff --git a/intel/tests/gen7-2d-copy.batch.sh b/intel/tests/gen7-2d-copy.batch.sh new file mode 100644 index 0000000..a94057f --- /dev/null +++ b/intel/tests/gen7-2d-copy.batch.sh @@ -0,0 +1,20 @@ +#!/bin/sh + +TEST_FILENAME=`echo "$0" | sed 's|.sh||'` +./test_decode $TEST_FILENAME + +ret=$? + +# pretty-print a diff showing what happened, and leave the dumped +# around for possibly moving over the ref. +if test $ret = 1; then + REF_FILENAME="$TEST_FILENAME-ref.txt" + NEW_FILENAME="$TEST_FILENAME-new.txt" + ./test_decode $TEST_FILENAME -dump > $NEW_FILENAME + if test $? = 0; then + echo "Differences:" + diff -u $REF_FILENAME $NEW_FILENAME + fi +fi + +exit $ret diff --git a/intel/tests/gen7-3d.batch b/intel/tests/gen7-3d.batch new file mode 100644 index 0000000000000000000000000000000000000000..328ec88170c586e89f2bc85ebce7f4f350d0e545 GIT binary patch literal 848 zcmb7COIE@_5UfdNV0ixc1wWuhQT#1Hy+GW%buT+TfsOdojVnEXOOB#9$w|bXP6CNf z7xsIhdaAlRU1R`#>tShxLadRJvo}oWg&PYsbex*BEAqHJ>{NuyP>Q=0Ke=Rwo&^W= z;XwoE#3bWsif1YA(S_74lM>vg&qu(Z<@8^}pjOZnPj!=%I14h`CWYQTYL z9y)~@gN?#DKTl)x5A87JdlWsmjuQ$6>mw_B1mtCd*mFKKs@Y6e3fL;x=a<4(#=}FM zpab-P_ju}K5!+O?*HZqUAA<(@P3hRR7MJ;6g(gK7lY~1?ee_cwE%ssg|6HBzl<#$U z2_Z$vWfC90##Jf(Sdo}tp?D1Tf_sGXZg)=F67HvNVECOno_EYMh4O44g;Flpvz+J2 toxejv8hu!5Mw|{_gK7UQaHNk4*S~OSw`SqCZPW}fF0+ $NEW_FILENAME + if test $? = 0; then + echo "Differences:" + diff -u $REF_FILENAME $NEW_FILENAME + fi +fi + +exit $ret diff --git a/intel/tests/gm45-3d.batch b/intel/tests/gm45-3d.batch new file mode 100644 index 0000000000000000000000000000000000000000..549608bb2cabe558bc9e75044f04b124b98dedbe GIT binary patch literal 1952 zcma)7yH3L}6un6kLui7{n@okvP|w0sHh6^u#0g#G~o zJDlU#RR~U6t2d7A>vQhCK2AlvE0N|vRCD`zzjWz|(|0f^8|LHSDfco@jvL}=3^Oa@ zi9h)97xy@mo}4$$iZ2pJkNK#LehB-7rO)6yk|+$?{)I>jqi7p$u86|!I30!quElsc z-#&dh(u_qyPh@RX95=jm}kISu`L-7=1XHCaCX7c3g`UM?pM4riAJMswn*dcb#B`ytnLPJpqCA}+3FQwe|CejgoSvIU`BhyFV@X`SH2FolDG1A%|$U7w@I;F zSMt4C_=-G?TjA8`hB%`+aK?prs`Bq!aHjc{?w`V|(GBD3TJXyG5eL6GfUnKp#&7iV iacEYn_4Be&uOITVjjnOtuut}-{}G;p!l}>?w)?+8F literal 0 HcmV?d00001 diff --git a/intel/tests/gm45-3d.batch-ref.txt b/intel/tests/gm45-3d.batch-ref.txt new file mode 100644 index 0000000..5a47d77 --- /dev/null +++ b/intel/tests/gm45-3d.batch-ref.txt @@ -0,0 +1,488 @@ +0x12300000: 0x69040000: 3DSTATE_PIPELINE_SELECT +0x12300004: 0x79090000: 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP +0x12300008: 0x00000000: dword 1 +0x1230000c: 0x61020000: STATE_SIP +0x12300010: 0x00000000: dword 1 +0x12300014: 0x680b0000: 3DSTATE_VF_STATISTICS +0x12300018: 0x61010004: STATE_BASE_ADDRESS +0x1230001c: 0x00000001: general state base address 0x00000000 +0x12300020: 0x00000001: surface state base address 0x00000000 +0x12300024: 0x00000001: indirect state base address 0x00000000 +0x12300028: 0x00000001: general state upper bound disabled +0x1230002c: 0x00000001: indirect state upper bound disabled +0x12300030: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS +0x12300034: 0x00007e20: VS binding table +0x12300038: 0x00000000: GS binding table +0x1230003c: 0x00000000: Clip binding table +0x12300040: 0x00000000: SF binding table +0x12300044: 0x00007e20: WM binding table +0x12300048: 0x79010003: 3DSTATE_CONSTANT_COLOR +0x1230004c: 0x00000000: dword 1 +0x12300050: 0x00000000: dword 2 +0x12300054: 0x00000000: dword 3 +0x12300058: 0x00000000: dword 4 +0x1230005c: 0x79050004: 3DSTATE_DEPTH_BUFFER +0x12300060: 0x2c0805ff: 2D, z24s8, pitch = 1536 bytes, tiled +0x12300064: 0x00000000: depth offset +0x12300068: 0x09584ac0: 300x300 +0x1230006c: 0x00000000: volume depth +0x12300070: 0x00000000: +0x12300074: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300078: 0x00007d60: VS state +0x1230007c: 0x00000000: GS state +0x12300080: 0x00007d21: Clip state +0x12300084: 0x00007d80: SF state +0x12300088: 0x00007de0: WM state +0x1230008c: 0x00007fc0: CC state +0x12300090: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300094: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300098: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x1230009c: 0x60010000: CS_URB_STATE +0x123000a0: 0x00000024: entry_size: 2 [192 bytes], n_entries: 4 +0x123000a4: 0x79000002: 3DSTATE_DRAWING_RECTANGLE +0x123000a8: 0x00000000: top left: 0,0 +0x123000ac: 0x012b012b: bottom right: 299,299 +0x123000b0: 0x00000000: origin: 0,0 +0x123000b4: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x123000b8: 0x0000000c: buffer 0: sequential, pitch 12b +0x123000bc: 0x00000000: buffer address +0x123000c0: 0x00000000: max index +0x123000c4: 0x00000000: mbz +0x123000c8: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x123000cc: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123000d0: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123000d4: 0x60020100: CONSTANT_BUFFER: valid +0x123000d8: 0x00000001: offset: 0x00000000, length: 128 bytes +0x123000dc: 0x7b001804: 3DPRIMITIVE: tri fan sequential +0x123000e0: 0x00000004: vertex count +0x123000e4: 0x00000000: start vertex +0x123000e8: 0x00000001: instance count +0x123000ec: 0x00000000: start instance +0x123000f0: 0x00000000: index bias +0x123000f4: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS +0x123000f8: 0x00007b40: VS binding table +0x123000fc: 0x00000000: GS binding table +0x12300100: 0x00000000: Clip binding table +0x12300104: 0x00000000: SF binding table +0x12300108: 0x00007b40: WM binding table +0x1230010c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300110: 0x00007aa0: VS state +0x12300114: 0x00007a41: GS state +0x12300118: 0x00007a61: Clip state +0x1230011c: 0x00007ac0: SF state +0x12300120: 0x00007b00: WM state +0x12300124: 0x00007cc0: CC state +0x12300128: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230012c: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300130: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x12300134: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300138: 0x0000000c: buffer 0: sequential, pitch 12b +0x1230013c: 0x00000000: buffer address +0x12300140: 0x00000000: max index +0x12300144: 0x00000000: mbz +0x12300148: 0x60020100: CONSTANT_BUFFER: valid +0x1230014c: 0x00000082: offset: 0x00000080, length: 192 bytes +0x12300150: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300154: 0x00000052: vertex count +0x12300158: 0x00000000: start vertex +0x1230015c: 0x00000001: instance count +0x12300160: 0x00000000: start instance +0x12300164: 0x00000000: index bias +0x12300168: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x1230016c: 0x00007aa0: VS state +0x12300170: 0x00007a21: GS state +0x12300174: 0x00007a61: Clip state +0x12300178: 0x00007ac0: SF state +0x1230017c: 0x00007b00: WM state +0x12300180: 0x00007cc0: CC state +0x12300184: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300188: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x1230018c: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x12300190: 0x60020100: CONSTANT_BUFFER: valid +0x12300194: 0x00000082: offset: 0x00000080, length: 192 bytes +0x12300198: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x1230019c: 0x00000050: vertex count +0x123001a0: 0x00000052: start vertex +0x123001a4: 0x00000001: instance count +0x123001a8: 0x00000000: start instance +0x123001ac: 0x00000000: index bias +0x123001b0: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123001b4: 0x00007aa0: VS state +0x123001b8: 0x00007a01: GS state +0x123001bc: 0x00007a61: Clip state +0x123001c0: 0x00007ac0: SF state +0x123001c4: 0x00007b00: WM state +0x123001c8: 0x00007cc0: CC state +0x123001cc: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123001d0: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x123001d4: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x123001d8: 0x60020100: CONSTANT_BUFFER: valid +0x123001dc: 0x00000142: offset: 0x00000140, length: 192 bytes +0x123001e0: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x123001e4: 0x00000052: vertex count +0x123001e8: 0x000000a2: start vertex +0x123001ec: 0x00000001: instance count +0x123001f0: 0x00000000: start instance +0x123001f4: 0x00000000: index bias +0x123001f8: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123001fc: 0x00007aa0: VS state +0x12300200: 0x000079e1: GS state +0x12300204: 0x00007a61: Clip state +0x12300208: 0x00007ac0: SF state +0x1230020c: 0x00007b00: WM state +0x12300210: 0x00007cc0: CC state +0x12300214: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300218: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x1230021c: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x12300220: 0x60020100: CONSTANT_BUFFER: valid +0x12300224: 0x00000142: offset: 0x00000140, length: 192 bytes +0x12300228: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x1230022c: 0x00000050: vertex count +0x12300230: 0x000000f4: start vertex +0x12300234: 0x00000001: instance count +0x12300238: 0x00000000: start instance +0x1230023c: 0x00000000: index bias +0x12300240: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300244: 0x00007aa0: VS state +0x12300248: 0x000079c1: GS state +0x1230024c: 0x00007a61: Clip state +0x12300250: 0x00007ac0: SF state +0x12300254: 0x00007b00: WM state +0x12300258: 0x00007cc0: CC state +0x1230025c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300260: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300264: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x12300268: 0x60020100: CONSTANT_BUFFER: valid +0x1230026c: 0x00000142: offset: 0x00000140, length: 192 bytes +0x12300270: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300274: 0x000079a0: VS state +0x12300278: 0x000079c1: GS state +0x1230027c: 0x00007a61: Clip state +0x12300280: 0x00007ac0: SF state +0x12300284: 0x00007b00: WM state +0x12300288: 0x00007cc0: CC state +0x1230028c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300290: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300294: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x12300298: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x1230029c: 0x00000018: buffer 0: sequential, pitch 24b +0x123002a0: 0x00000f48: buffer address +0x123002a4: 0x00000000: max index +0x123002a8: 0x00000000: mbz +0x123002ac: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x123002b0: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123002b4: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123002b8: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x123002bc: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes +0x123002c0: 0x60020100: CONSTANT_BUFFER: valid +0x123002c4: 0x00000202: offset: 0x00000200, length: 192 bytes +0x123002c8: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x123002cc: 0x000000a2: vertex count +0x123002d0: 0x00000000: start vertex +0x123002d4: 0x00000001: instance count +0x123002d8: 0x00000000: start instance +0x123002dc: 0x00000000: index bias +0x123002e0: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123002e4: 0x000079a0: VS state +0x123002e8: 0x00000000: GS state +0x123002ec: 0x00007901: Clip state +0x123002f0: 0x00007940: SF state +0x123002f4: 0x00007960: WM state +0x123002f8: 0x00007cc0: CC state +0x123002fc: 0x00000000: MI_NOOP +0x12300300: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300304: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300308: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x1230030c: 0x60020100: CONSTANT_BUFFER: valid +0x12300310: 0x00000202: offset: 0x00000200, length: 192 bytes +0x12300314: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x12300318: 0x0000002a: vertex count +0x1230031c: 0x000000a2: start vertex +0x12300320: 0x00000001: instance count +0x12300324: 0x00000000: start instance +0x12300328: 0x00000000: index bias +0x1230032c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300330: 0x00007860: VS state +0x12300334: 0x00007801: GS state +0x12300338: 0x00007821: Clip state +0x1230033c: 0x00007880: SF state +0x12300340: 0x000078a0: WM state +0x12300344: 0x00007cc0: CC state +0x12300348: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230034c: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300350: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x12300354: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300358: 0x0000000c: buffer 0: sequential, pitch 12b +0x1230035c: 0x00002268: buffer address +0x12300360: 0x00000000: max index +0x12300364: 0x00000000: mbz +0x12300368: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x1230036c: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x12300370: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x12300374: 0x60020100: CONSTANT_BUFFER: valid +0x12300378: 0x000002c2: offset: 0x000002c0, length: 192 bytes +0x1230037c: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300380: 0x0000002a: vertex count +0x12300384: 0x00000000: start vertex +0x12300388: 0x00000001: instance count +0x1230038c: 0x00000000: start instance +0x12300390: 0x00000000: index bias +0x12300394: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300398: 0x00007860: VS state +0x1230039c: 0x000077e1: GS state +0x123003a0: 0x00007821: Clip state +0x123003a4: 0x00007880: SF state +0x123003a8: 0x000078a0: WM state +0x123003ac: 0x00007cc0: CC state +0x123003b0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123003b4: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x123003b8: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x123003bc: 0x60020100: CONSTANT_BUFFER: valid +0x123003c0: 0x000002c2: offset: 0x000002c0, length: 192 bytes +0x123003c4: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x123003c8: 0x00000028: vertex count +0x123003cc: 0x0000002a: start vertex +0x123003d0: 0x00000001: instance count +0x123003d4: 0x00000000: start instance +0x123003d8: 0x00000000: index bias +0x123003dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123003e0: 0x00007860: VS state +0x123003e4: 0x000077c1: GS state +0x123003e8: 0x00007821: Clip state +0x123003ec: 0x00007880: SF state +0x123003f0: 0x000078a0: WM state +0x123003f4: 0x00007cc0: CC state +0x123003f8: 0x00000000: MI_NOOP +0x123003fc: 0x00000000: MI_NOOP +0x12300400: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300404: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300408: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x1230040c: 0x60020100: CONSTANT_BUFFER: valid +0x12300410: 0x00000382: offset: 0x00000380, length: 192 bytes +0x12300414: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300418: 0x0000002a: vertex count +0x1230041c: 0x00000052: start vertex +0x12300420: 0x00000001: instance count +0x12300424: 0x00000000: start instance +0x12300428: 0x00000000: index bias +0x1230042c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300430: 0x00007860: VS state +0x12300434: 0x000077a1: GS state +0x12300438: 0x00007821: Clip state +0x1230043c: 0x00007880: SF state +0x12300440: 0x000078a0: WM state +0x12300444: 0x00007cc0: CC state +0x12300448: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230044c: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300450: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x12300454: 0x60020100: CONSTANT_BUFFER: valid +0x12300458: 0x00000382: offset: 0x00000380, length: 192 bytes +0x1230045c: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300460: 0x00000028: vertex count +0x12300464: 0x0000007c: start vertex +0x12300468: 0x00000001: instance count +0x1230046c: 0x00000000: start instance +0x12300470: 0x00000000: index bias +0x12300474: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300478: 0x00007860: VS state +0x1230047c: 0x00007781: GS state +0x12300480: 0x00007821: Clip state +0x12300484: 0x00007880: SF state +0x12300488: 0x000078a0: WM state +0x1230048c: 0x00007cc0: CC state +0x12300490: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300494: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300498: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x1230049c: 0x60020100: CONSTANT_BUFFER: valid +0x123004a0: 0x00000382: offset: 0x00000380, length: 192 bytes +0x123004a4: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123004a8: 0x00007760: VS state +0x123004ac: 0x00007781: GS state +0x123004b0: 0x00007821: Clip state +0x123004b4: 0x00007880: SF state +0x123004b8: 0x000078a0: WM state +0x123004bc: 0x00007cc0: CC state +0x123004c0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123004c4: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x123004c8: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x123004cc: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x123004d0: 0x00000018: buffer 0: sequential, pitch 24b +0x123004d4: 0x00002a30: buffer address +0x123004d8: 0x00000000: max index +0x123004dc: 0x00000000: mbz +0x123004e0: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x123004e4: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123004e8: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123004ec: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x123004f0: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes +0x123004f4: 0x60020100: CONSTANT_BUFFER: valid +0x123004f8: 0x00000442: offset: 0x00000440, length: 192 bytes +0x123004fc: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300500: 0x00000052: vertex count +0x12300504: 0x00000000: start vertex +0x12300508: 0x00000001: instance count +0x1230050c: 0x00000000: start instance +0x12300510: 0x00000000: index bias +0x12300514: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300518: 0x00007760: VS state +0x1230051c: 0x00000000: GS state +0x12300520: 0x000076c1: Clip state +0x12300524: 0x00007700: SF state +0x12300528: 0x00007720: WM state +0x1230052c: 0x00007cc0: CC state +0x12300530: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300534: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300538: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x1230053c: 0x60020100: CONSTANT_BUFFER: valid +0x12300540: 0x00000442: offset: 0x00000440, length: 192 bytes +0x12300544: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x12300548: 0x00000016: vertex count +0x1230054c: 0x00000052: start vertex +0x12300550: 0x00000001: instance count +0x12300554: 0x00000000: start instance +0x12300558: 0x00000000: index bias +0x1230055c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300560: 0x00007620: VS state +0x12300564: 0x000075c1: GS state +0x12300568: 0x000075e1: Clip state +0x1230056c: 0x00007640: SF state +0x12300570: 0x00007660: WM state +0x12300574: 0x00007cc0: CC state +0x12300578: 0x00000000: MI_NOOP +0x1230057c: 0x00000000: MI_NOOP +0x12300580: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300584: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300588: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x1230058c: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300590: 0x0000000c: buffer 0: sequential, pitch 12b +0x12300594: 0x000033f0: buffer address +0x12300598: 0x00000000: max index +0x1230059c: 0x00000000: mbz +0x123005a0: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x123005a4: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123005a8: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123005ac: 0x60020100: CONSTANT_BUFFER: valid +0x123005b0: 0x00000502: offset: 0x00000500, length: 192 bytes +0x123005b4: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x123005b8: 0x0000002a: vertex count +0x123005bc: 0x00000000: start vertex +0x123005c0: 0x00000001: instance count +0x123005c4: 0x00000000: start instance +0x123005c8: 0x00000000: index bias +0x123005cc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123005d0: 0x00007620: VS state +0x123005d4: 0x000075a1: GS state +0x123005d8: 0x000075e1: Clip state +0x123005dc: 0x00007640: SF state +0x123005e0: 0x00007660: WM state +0x123005e4: 0x00007cc0: CC state +0x123005e8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123005ec: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x123005f0: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x123005f4: 0x60020100: CONSTANT_BUFFER: valid +0x123005f8: 0x00000502: offset: 0x00000500, length: 192 bytes +0x123005fc: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300600: 0x00000028: vertex count +0x12300604: 0x0000002a: start vertex +0x12300608: 0x00000001: instance count +0x1230060c: 0x00000000: start instance +0x12300610: 0x00000000: index bias +0x12300614: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300618: 0x00007620: VS state +0x1230061c: 0x00007581: GS state +0x12300620: 0x000075e1: Clip state +0x12300624: 0x00007640: SF state +0x12300628: 0x00007660: WM state +0x1230062c: 0x00007cc0: CC state +0x12300630: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300634: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300638: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x1230063c: 0x60020100: CONSTANT_BUFFER: valid +0x12300640: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x12300644: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300648: 0x0000002a: vertex count +0x1230064c: 0x00000052: start vertex +0x12300650: 0x00000001: instance count +0x12300654: 0x00000000: start instance +0x12300658: 0x00000000: index bias +0x1230065c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300660: 0x00007620: VS state +0x12300664: 0x00007561: GS state +0x12300668: 0x000075e1: Clip state +0x1230066c: 0x00007640: SF state +0x12300670: 0x00007660: WM state +0x12300674: 0x00007cc0: CC state +0x12300678: 0x00000000: MI_NOOP +0x1230067c: 0x00000000: MI_NOOP +0x12300680: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300684: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300688: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x1230068c: 0x60020100: CONSTANT_BUFFER: valid +0x12300690: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x12300694: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300698: 0x00000028: vertex count +0x1230069c: 0x0000007c: start vertex +0x123006a0: 0x00000001: instance count +0x123006a4: 0x00000000: start instance +0x123006a8: 0x00000000: index bias +0x123006ac: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123006b0: 0x00007620: VS state +0x123006b4: 0x00007541: GS state +0x123006b8: 0x000075e1: Clip state +0x123006bc: 0x00007640: SF state +0x123006c0: 0x00007660: WM state +0x123006c4: 0x00007cc0: CC state +0x123006c8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123006cc: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x123006d0: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x123006d4: 0x60020100: CONSTANT_BUFFER: valid +0x123006d8: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x123006dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123006e0: 0x00007520: VS state +0x123006e4: 0x00007541: GS state +0x123006e8: 0x000075e1: Clip state +0x123006ec: 0x00007640: SF state +0x123006f0: 0x00007660: WM state +0x123006f4: 0x00007cc0: CC state +0x123006f8: 0x00000000: MI_NOOP +0x123006fc: 0x00000000: MI_NOOP +0x12300700: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300704: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300708: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x1230070c: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300710: 0x00000018: buffer 0: sequential, pitch 24b +0x12300714: 0x00003bb8: buffer address +0x12300718: 0x00000000: max index +0x1230071c: 0x00000000: mbz +0x12300720: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x12300724: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x12300728: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x1230072c: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x12300730: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes +0x12300734: 0x60020100: CONSTANT_BUFFER: valid +0x12300738: 0x00000682: offset: 0x00000680, length: 192 bytes +0x1230073c: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300740: 0x00000052: vertex count +0x12300744: 0x00000000: start vertex +0x12300748: 0x00000001: instance count +0x1230074c: 0x00000000: start instance +0x12300750: 0x00000000: index bias +0x12300754: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300758: 0x00007520: VS state +0x1230075c: 0x00000000: GS state +0x12300760: 0x00007481: Clip state +0x12300764: 0x000074c0: SF state +0x12300768: 0x000074e0: WM state +0x1230076c: 0x00007cc0: CC state +0x12300770: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300774: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 +0x12300778: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 +0x1230077c: 0x60020100: CONSTANT_BUFFER: valid +0x12300780: 0x00000682: offset: 0x00000680, length: 192 bytes +0x12300784: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x12300788: 0x00000016: vertex count +0x1230078c: 0x00000052: start vertex +0x12300790: 0x00000001: instance count +0x12300794: 0x00000000: start instance +0x12300798: 0x00000000: index bias +0x1230079c: 0x05000000: MI_BATCH_BUFFER_END diff --git a/intel/tests/gm45-3d.batch.sh b/intel/tests/gm45-3d.batch.sh new file mode 100644 index 0000000..a94057f --- /dev/null +++ b/intel/tests/gm45-3d.batch.sh @@ -0,0 +1,20 @@ +#!/bin/sh + +TEST_FILENAME=`echo "$0" | sed 's|.sh||'` +./test_decode $TEST_FILENAME + +ret=$? + +# pretty-print a diff showing what happened, and leave the dumped +# around for possibly moving over the ref. +if test $ret = 1; then + REF_FILENAME="$TEST_FILENAME-ref.txt" + NEW_FILENAME="$TEST_FILENAME-new.txt" + ./test_decode $TEST_FILENAME -dump > $NEW_FILENAME + if test $? = 0; then + echo "Differences:" + diff -u $REF_FILENAME $NEW_FILENAME + fi +fi + +exit $ret diff --git a/intel/tests/test-batch.sh b/intel/tests/test-batch.sh new file mode 100644 index 0000000..a94057f --- /dev/null +++ b/intel/tests/test-batch.sh @@ -0,0 +1,20 @@ +#!/bin/sh + +TEST_FILENAME=`echo "$0" | sed 's|.sh||'` +./test_decode $TEST_FILENAME + +ret=$? + +# pretty-print a diff showing what happened, and leave the dumped +# around for possibly moving over the ref. +if test $ret = 1; then + REF_FILENAME="$TEST_FILENAME-ref.txt" + NEW_FILENAME="$TEST_FILENAME-new.txt" + ./test_decode $TEST_FILENAME -dump > $NEW_FILENAME + if test $? = 0; then + echo "Differences:" + diff -u $REF_FILENAME $NEW_FILENAME + fi +fi + +exit $ret diff --git a/libdrm.pc.in b/libdrm.pc.in new file mode 100644 index 0000000..fdd911f --- /dev/null +++ b/libdrm.pc.in @@ -0,0 +1,10 @@ +prefix=@prefix@ +exec_prefix=@exec_prefix@ +libdir=@libdir@ +includedir=@includedir@ + +Name: libdrm +Description: Userspace interface to kernel DRM services +Version: @PACKAGE_VERSION@ +Libs: -L${libdir} -ldrm +Cflags: -I${includedir} -I${includedir}/libdrm -I${includedir}/exynos diff --git a/libdrm_lists.h b/libdrm_lists.h new file mode 100644 index 0000000..8926d8d --- /dev/null +++ b/libdrm_lists.h @@ -0,0 +1,118 @@ +/************************************************************************** + * + * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND. USA. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ + +/* + * List macros heavily inspired by the Linux kernel + * list handling. No list looping yet. + */ + +#include + +typedef struct _drmMMListHead +{ + struct _drmMMListHead *prev; + struct _drmMMListHead *next; +} drmMMListHead; + +#define DRMINITLISTHEAD(__item) \ + do{ \ + (__item)->prev = (__item); \ + (__item)->next = (__item); \ + } while (0) + +#define DRMLISTADD(__item, __list) \ + do { \ + (__item)->prev = (__list); \ + (__item)->next = (__list)->next; \ + (__list)->next->prev = (__item); \ + (__list)->next = (__item); \ + } while (0) + +#define DRMLISTADDTAIL(__item, __list) \ + do { \ + (__item)->next = (__list); \ + (__item)->prev = (__list)->prev; \ + (__list)->prev->next = (__item); \ + (__list)->prev = (__item); \ + } while(0) + +#define DRMLISTDEL(__item) \ + do { \ + (__item)->prev->next = (__item)->next; \ + (__item)->next->prev = (__item)->prev; \ + } while(0) + +#define DRMLISTDELINIT(__item) \ + do { \ + (__item)->prev->next = (__item)->next; \ + (__item)->next->prev = (__item)->prev; \ + (__item)->next = (__item); \ + (__item)->prev = (__item); \ + } while(0) + +#define DRMLISTENTRY(__type, __item, __field) \ + ((__type *)(((char *) (__item)) - offsetof(__type, __field))) + +#define DRMLISTEMPTY(__item) ((__item)->next == (__item)) + +#define DRMLISTSINGLE(__list) \ + (!DRMLISTEMPTY(__list) && ((__list)->next == (__list)->prev)) + +#define DRMLISTFOREACH(__item, __list) \ + for ((__item) = (__list)->next; \ + (__item) != (__list); (__item) = (__item)->next) + +#define DRMLISTFOREACHSAFE(__item, __temp, __list) \ + for ((__item) = (__list)->next, (__temp) = (__item)->next; \ + (__item) != (__list); \ + (__item) = (__temp), (__temp) = (__item)->next) + +#define DRMLISTFOREACHSAFEREVERSE(__item, __temp, __list) \ + for ((__item) = (__list)->prev, (__temp) = (__item)->prev; \ + (__item) != (__list); \ + (__item) = (__temp), (__temp) = (__item)->prev) + +#define DRMLISTFOREACHENTRY(__item, __list, __head) \ + for ((__item) = DRMLISTENTRY(typeof(*__item), (__list)->next, __head); \ + &(__item)->__head != (__list); \ + (__item) = DRMLISTENTRY(typeof(*__item), \ + (__item)->__head.next, __head)) + +#define DRMLISTFOREACHENTRYSAFE(__item, __temp, __list, __head) \ + for ((__item) = DRMLISTENTRY(typeof(*__item), (__list)->next, __head), \ + (__temp) = DRMLISTENTRY(typeof(*__item), \ + (__item)->__head.next, __head); \ + &(__item)->__head != (__list); \ + (__item) = (__temp), \ + (__temp) = DRMLISTENTRY(typeof(*__item), \ + (__temp)->__head.next, __head)) + +#define DRMLISTJOIN(__list, __join) if (!DRMLISTEMPTY(__list)) { \ + (__list)->next->prev = (__join); \ + (__list)->prev->next = (__join)->next; \ + (__join)->next->prev = (__list)->prev; \ + (__join)->next = (__list)->next; \ +} diff --git a/libkms/Makefile.am b/libkms/Makefile.am new file mode 100644 index 0000000..df74b7e --- /dev/null +++ b/libkms/Makefile.am @@ -0,0 +1,45 @@ +AM_CFLAGS = \ + $(WARN_CFLAGS) \ + -I$(top_srcdir)/include/drm \ + -I$(top_srcdir) + +libkms_la_LTLIBRARIES = libkms.la +libkms_ladir = $(libdir) +libkms_la_LDFLAGS = -version-number 1:0:0 -no-undefined +libkms_la_LIBADD = + +#if HAVE_LIBUDEV +#libkms_la_LIBADD += $(LIBUDEV_LIBS) +#endif + +libkms_la_SOURCES = \ + internal.h \ + linux.c \ + intel.c \ + dumb.c \ + api.c + +if HAVE_VMWGFX +libkms_la_SOURCES += vmwgfx.c +endif + +if HAVE_NOUVEAU +libkms_la_SOURCES += nouveau.c +endif + +if HAVE_RADEON +libkms_la_SOURCES += radeon.c +endif + +if HAVE_SLP +libkms_la_SOURCES += slp.c +AM_CFLAGS += -I$(top_srcdir)/exynos +endif + +libkmsincludedir = ${includedir}/libkms +libkmsinclude_HEADERS = libkms.h + +pkgconfigdir = @pkgconfigdir@ +pkgconfig_DATA = libkms.pc + +EXTRA_DIST = libkms.pc.in diff --git a/libkms/api.c b/libkms/api.c new file mode 100644 index 0000000..4a05f3d --- /dev/null +++ b/libkms/api.c @@ -0,0 +1,138 @@ +/************************************************************************** + * + * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + + +#include "config.h" +#include +#include +#include +#include "internal.h" + +int kms_create(int fd, struct kms_driver **out) +{ + return linux_create(fd, out); +} + +int kms_get_prop(struct kms_driver *kms, unsigned key, unsigned *out) +{ + switch (key) { + case KMS_BO_TYPE: + break; + default: + return -EINVAL; + } + return kms->get_prop(kms, key, out); +} + +int kms_destroy(struct kms_driver **kms) +{ + if (!(*kms)) + return 0; + + free(*kms); + *kms = NULL; + return 0; +} + +int kms_bo_create(struct kms_driver *kms, const unsigned *attr, struct kms_bo **out) +{ + unsigned width = 0; + unsigned height = 0; + enum kms_bo_type type = KMS_BO_TYPE_SCANOUT_X8R8G8B8; + int i; + + for (i = 0; attr[i];) { + unsigned key = attr[i++]; + unsigned value = attr[i++]; + + switch (key) { + case KMS_WIDTH: + width = value; + break; + case KMS_HEIGHT: + height = value; + break; + case KMS_BO_TYPE: + type = value; + break; + default: + return EINVAL; + } + } + + if (width == 0 || height == 0) + return -EINVAL; + + /* XXX sanity check type */ + + if (type == KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8 && + (width != 64 || height != 64)) + return -EINVAL; + + return kms->bo_create(kms, width, height, type, attr, out); +} + +int kms_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out) +{ + switch (key) { + case KMS_PITCH: + *out = bo->pitch; + break; + case KMS_HANDLE: + *out = bo->handle; + break; + default: + return -EINVAL; + } + + return 0; +} + +int kms_bo_map(struct kms_bo *bo, void **out) +{ + return bo->kms->bo_map(bo, out); +} + +int kms_bo_unmap(struct kms_bo *bo) +{ + return bo->kms->bo_unmap(bo); +} + +int kms_bo_destroy(struct kms_bo **bo) +{ + int ret; + + if (!(*bo)) + return 0; + + ret = (*bo)->kms->bo_destroy(*bo); + if (ret) + return ret; + + *bo = NULL; + return 0; +} diff --git a/libkms/dumb.c b/libkms/dumb.c new file mode 100644 index 0000000..440efb3 --- /dev/null +++ b/libkms/dumb.c @@ -0,0 +1,221 @@ +/************************************************************************** + * + * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + + +#define HAVE_STDINT_H +#define _FILE_OFFSET_BITS 64 + +#include +#include +#include +#include +#include "internal.h" + +#include +#include +#include "xf86drm.h" + +#include "i915_drm.h" + +struct dumb_bo +{ + struct kms_bo base; + unsigned map_count; +}; + +static int +dumb_get_prop(struct kms_driver *kms, unsigned key, unsigned *out) +{ + switch (key) { + case KMS_BO_TYPE: + *out = KMS_BO_TYPE_SCANOUT_X8R8G8B8 | KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8; + break; + default: + return -EINVAL; + } + return 0; +} + +static int +dumb_destroy(struct kms_driver *kms) +{ + free(kms); + return 0; +} + +static int +dumb_bo_create(struct kms_driver *kms, + const unsigned width, const unsigned height, + const enum kms_bo_type type, const unsigned *attr, + struct kms_bo **out) +{ + struct drm_mode_create_dumb arg; + struct dumb_bo *bo; + int i, ret; + + for (i = 0; attr[i]; i += 2) { + switch (attr[i]) { + case KMS_WIDTH: + case KMS_HEIGHT: + break; + case KMS_BO_TYPE: + break; + default: + return -EINVAL; + } + } + + bo = calloc(1, sizeof(*bo)); + if (!bo) + return -ENOMEM; + + memset(&arg, 0, sizeof(arg)); + + /* All BO_TYPE currently are 32bpp formats */ + arg.bpp = 32; + arg.width = width; + arg.height = height; + + ret = drmIoctl(kms->fd, DRM_IOCTL_MODE_CREATE_DUMB, &arg); + if (ret) + goto err_free; + + bo->base.kms = kms; + bo->base.handle = arg.handle; + bo->base.size = arg.size; + bo->base.pitch = arg.pitch; + + *out = &bo->base; + + return 0; + +err_free: + free(bo); + return ret; +} + +static int +dumb_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out) +{ + switch (key) { + default: + return -EINVAL; + } +} + +static int +dumb_bo_map(struct kms_bo *_bo, void **out) +{ + struct dumb_bo *bo = (struct dumb_bo *)_bo; + struct drm_mode_map_dumb arg; + void *map = NULL; + int ret; + + if (bo->base.ptr) { + bo->map_count++; + *out = bo->base.ptr; + return 0; + } + + memset(&arg, 0, sizeof(arg)); + arg.handle = bo->base.handle; + + ret = drmIoctl(bo->base.kms->fd, DRM_IOCTL_MODE_MAP_DUMB, &arg); + if (ret) + return ret; + + map = mmap(0, bo->base.size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->base.kms->fd, arg.offset); + if (map == MAP_FAILED) + return -errno; + + bo->base.ptr = map; + bo->map_count++; + *out = bo->base.ptr; + + return 0; +} + +static int +dumb_bo_unmap(struct kms_bo *_bo) +{ + struct dumb_bo *bo = (struct dumb_bo *)_bo; + bo->map_count--; + return 0; +} + +static int +dumb_bo_destroy(struct kms_bo *_bo) +{ + struct dumb_bo *bo = (struct dumb_bo *)_bo; + struct drm_mode_destroy_dumb arg; + int ret; + + if (bo->base.ptr) { + /* XXX Sanity check map_count */ + munmap(bo->base.ptr, bo->base.size); + bo->base.ptr = NULL; + } + + memset(&arg, 0, sizeof(arg)); + arg.handle = bo->base.handle; + + ret = drmIoctl(bo->base.kms->fd, DRM_IOCTL_MODE_DESTROY_DUMB, &arg); + if (ret) + return -errno; + + free(bo); + return 0; +} + +int +dumb_create(int fd, struct kms_driver **out) +{ + struct kms_driver *kms; + int ret; + uint64_t cap = 0; + + ret = drmGetCap(fd, DRM_CAP_DUMB_BUFFER, &cap); + if (ret || cap == 0) + return -EINVAL; + + kms = calloc(1, sizeof(*kms)); + if (!kms) + return -ENOMEM; + + kms->fd = fd; + + kms->bo_create = dumb_bo_create; + kms->bo_map = dumb_bo_map; + kms->bo_unmap = dumb_bo_unmap; + kms->bo_get_prop = dumb_bo_get_prop; + kms->bo_destroy = dumb_bo_destroy; + kms->get_prop = dumb_get_prop; + kms->destroy = dumb_destroy; + *out = kms; + + return 0; +} diff --git a/libkms/intel.c b/libkms/intel.c new file mode 100644 index 0000000..8b8249b --- /dev/null +++ b/libkms/intel.c @@ -0,0 +1,238 @@ +/************************************************************************** + * + * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + + +#define HAVE_STDINT_H +#define _FILE_OFFSET_BITS 64 + +#include +#include +#include +#include +#include "internal.h" + +#include +#include +#include "xf86drm.h" + +#include "i915_drm.h" + +struct intel_bo +{ + struct kms_bo base; + unsigned map_count; +}; + +static int +intel_get_prop(struct kms_driver *kms, unsigned key, unsigned *out) +{ + switch (key) { + case KMS_BO_TYPE: + *out = KMS_BO_TYPE_SCANOUT_X8R8G8B8 | KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8; + break; + default: + return -EINVAL; + } + return 0; +} + +static int +intel_destroy(struct kms_driver *kms) +{ + free(kms); + return 0; +} + +static int +intel_bo_create(struct kms_driver *kms, + const unsigned width, const unsigned height, + const enum kms_bo_type type, const unsigned *attr, + struct kms_bo **out) +{ + struct drm_i915_gem_create arg; + unsigned size, pitch; + struct intel_bo *bo; + int i, ret; + + for (i = 0; attr[i]; i += 2) { + switch (attr[i]) { + case KMS_WIDTH: + case KMS_HEIGHT: + case KMS_BO_TYPE: + break; + default: + return -EINVAL; + } + } + + bo = calloc(1, sizeof(*bo)); + if (!bo) + return -ENOMEM; + + if (type == KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8) { + pitch = 64 * 4; + size = 64 * 64 * 4; + } else if (type == KMS_BO_TYPE_SCANOUT_X8R8G8B8) { + pitch = width * 4; + pitch = (pitch + 512 - 1) & ~(512 - 1); + size = pitch * ((height + 4 - 1) & ~(4 - 1)); + } else { + return -EINVAL; + } + + memset(&arg, 0, sizeof(arg)); + arg.size = size; + + ret = drmCommandWriteRead(kms->fd, DRM_I915_GEM_CREATE, &arg, sizeof(arg)); + if (ret) + goto err_free; + + bo->base.kms = kms; + bo->base.handle = arg.handle; + bo->base.size = size; + bo->base.pitch = pitch; + + *out = &bo->base; + if (type == KMS_BO_TYPE_SCANOUT_X8R8G8B8 && pitch > 512) { + struct drm_i915_gem_set_tiling tile; + + memset(&tile, 0, sizeof(tile)); + tile.handle = bo->base.handle; + tile.tiling_mode = I915_TILING_X; + tile.stride = bo->base.pitch; + + ret = drmCommandWriteRead(kms->fd, DRM_I915_GEM_SET_TILING, &tile, sizeof(tile)); +#if 0 + if (ret) { + kms_bo_destroy(out); + return ret; + } +#endif + } + + return 0; + +err_free: + free(bo); + return ret; +} + +static int +intel_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out) +{ + switch (key) { + default: + return -EINVAL; + } +} + +static int +intel_bo_map(struct kms_bo *_bo, void **out) +{ + struct intel_bo *bo = (struct intel_bo *)_bo; + struct drm_i915_gem_mmap_gtt arg; + void *map = NULL; + int ret; + + if (bo->base.ptr) { + bo->map_count++; + *out = bo->base.ptr; + return 0; + } + + memset(&arg, 0, sizeof(arg)); + arg.handle = bo->base.handle; + + ret = drmCommandWriteRead(bo->base.kms->fd, DRM_I915_GEM_MMAP_GTT, &arg, sizeof(arg)); + if (ret) + return ret; + + map = mmap(0, bo->base.size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->base.kms->fd, arg.offset); + if (map == MAP_FAILED) + return -errno; + + bo->base.ptr = map; + bo->map_count++; + *out = bo->base.ptr; + + return 0; +} + +static int +intel_bo_unmap(struct kms_bo *_bo) +{ + struct intel_bo *bo = (struct intel_bo *)_bo; + bo->map_count--; + return 0; +} + +static int +intel_bo_destroy(struct kms_bo *_bo) +{ + struct intel_bo *bo = (struct intel_bo *)_bo; + struct drm_gem_close arg; + int ret; + + if (bo->base.ptr) { + /* XXX Sanity check map_count */ + munmap(bo->base.ptr, bo->base.size); + bo->base.ptr = NULL; + } + + memset(&arg, 0, sizeof(arg)); + arg.handle = bo->base.handle; + + ret = drmIoctl(bo->base.kms->fd, DRM_IOCTL_GEM_CLOSE, &arg); + if (ret) + return -errno; + + free(bo); + return 0; +} + +int +intel_create(int fd, struct kms_driver **out) +{ + struct kms_driver *kms; + + kms = calloc(1, sizeof(*kms)); + if (!kms) + return -ENOMEM; + + kms->fd = fd; + + kms->bo_create = intel_bo_create; + kms->bo_map = intel_bo_map; + kms->bo_unmap = intel_bo_unmap; + kms->bo_get_prop = intel_bo_get_prop; + kms->bo_destroy = intel_bo_destroy; + kms->get_prop = intel_get_prop; + kms->destroy = intel_destroy; + *out = kms; + + return 0; +} diff --git a/libkms/internal.h b/libkms/internal.h new file mode 100644 index 0000000..5e2501e --- /dev/null +++ b/libkms/internal.h @@ -0,0 +1,77 @@ +/************************************************************************** + * + * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + + +#ifndef INTERNAL_H_ +#define INTERNAL_H_ + +#include "libkms.h" + +struct kms_driver +{ + int (*get_prop)(struct kms_driver *kms, const unsigned key, + unsigned *out); + int (*destroy)(struct kms_driver *kms); + + int (*bo_create)(struct kms_driver *kms, + unsigned width, + unsigned height, + enum kms_bo_type type, + const unsigned *attr, + struct kms_bo **out); + int (*bo_get_prop)(struct kms_bo *bo, const unsigned key, + unsigned *out); + int (*bo_map)(struct kms_bo *bo, void **out); + int (*bo_unmap)(struct kms_bo *bo); + int (*bo_destroy)(struct kms_bo *bo); + + int fd; +}; + +struct kms_bo +{ + struct kms_driver *kms; + void *ptr; + size_t size; + size_t offset; + size_t pitch; + unsigned handle; +}; + +int linux_create(int fd, struct kms_driver **out); + +int vmwgfx_create(int fd, struct kms_driver **out); + +int intel_create(int fd, struct kms_driver **out); + +int dumb_create(int fd, struct kms_driver **out); + +int nouveau_create(int fd, struct kms_driver **out); + +int radeon_create(int fd, struct kms_driver **out); + +#endif diff --git a/libkms/libkms.h b/libkms/libkms.h new file mode 100644 index 0000000..4664442 --- /dev/null +++ b/libkms/libkms.h @@ -0,0 +1,74 @@ +/************************************************************************** + * + * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + + +#ifndef _LIBKMS_H_ +#define _LIBKMS_H_ + +/** + * \file + * + */ + +struct kms_driver; +struct kms_bo; + +enum kms_attrib +{ + KMS_TERMINATE_PROP_LIST, +#define KMS_TERMINATE_PROP_LIST KMS_TERMINATE_PROP_LIST + KMS_BO_TYPE, +#define KMS_BO_TYPE KMS_BO_TYPE + KMS_WIDTH, +#define KMS_WIDTH KMS_WIDTH + KMS_HEIGHT, +#define KMS_HEIGHT KMS_HEIGHT + KMS_PITCH, +#define KMS_PITCH KMS_PITCH + KMS_HANDLE, +#define KMS_HANDLE KMS_HANDLE +}; + +enum kms_bo_type +{ + KMS_BO_TYPE_SCANOUT_X8R8G8B8 = (1 << 0), +#define KMS_BO_TYPE_SCANOUT_X8R8G8B8 KMS_BO_TYPE_SCANOUT_X8R8G8B8 + KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8 = (1 << 1), +#define KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8 KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8 +}; + +int kms_create(int fd, struct kms_driver **out); +int kms_get_prop(struct kms_driver *kms, unsigned key, unsigned *out); +int kms_destroy(struct kms_driver **kms); + +int kms_bo_create(struct kms_driver *kms, const unsigned *attr, struct kms_bo **out); +int kms_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out); +int kms_bo_map(struct kms_bo *bo, void **out); +int kms_bo_unmap(struct kms_bo *bo); +int kms_bo_destroy(struct kms_bo **bo); + +#endif diff --git a/libkms/libkms.pc.in b/libkms/libkms.pc.in new file mode 100644 index 0000000..511535a --- /dev/null +++ b/libkms/libkms.pc.in @@ -0,0 +1,10 @@ +prefix=@prefix@ +exec_prefix=@exec_prefix@ +libdir=@libdir@ +includedir=@includedir@ + +Name: libkms +Description: Library that abstract aways the different mm interface for kernel drivers +Version: 1.0.0 +Libs: -L${libdir} -lkms +Cflags: -I${includedir}/libkms diff --git a/libkms/linux.c b/libkms/linux.c new file mode 100644 index 0000000..fc4f205 --- /dev/null +++ b/libkms/linux.c @@ -0,0 +1,226 @@ +/************************************************************************** + * + * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ +/* + * Thanks to krh and jcristau for the tips on + * going from fd to pci id via fstat and udev. + */ + + +#include "config.h" +#include +#include +#include +#include +#include +#include + +#include + +#include "internal.h" + +#define PATH_SIZE 512 + +static int +linux_name_from_sysfs(int fd, char **out) +{ + char path[PATH_SIZE+1] = ""; /* initialize to please valgrind */ + char link[PATH_SIZE+1] = ""; + struct stat buffer; + unsigned maj, min; + char* slash_name; + int ret; + + /* + * Inside the sysfs directory for the device there is a symlink + * to the directory representing the driver module, that path + * happens to hold the name of the driver. + * + * So lets get the symlink for the drm device. Then read the link + * and filter out the last directory which happens to be the name + * of the driver, which we can use to load the correct interface. + * + * Thanks to Ray Strode of Plymouth for the code. + */ + + ret = fstat(fd, &buffer); + if (ret) + return ret; + + if (!S_ISCHR(buffer.st_mode)) + return -EINVAL; + + maj = major(buffer.st_rdev); + min = minor(buffer.st_rdev); + + snprintf(path, PATH_SIZE, "/sys/dev/char/%d:%d/device/driver", maj, min); + + if (readlink(path, link, PATH_SIZE) < 0) + return -EINVAL; + + /* link looks something like this: ../../../bus/pci/drivers/intel */ + slash_name = strrchr(link, '/'); + if (!slash_name) + return -EINVAL; + + /* copy name and at the same time remove the slash */ + *out = strdup(slash_name + 1); + return 0; +} + +static int +linux_from_sysfs(int fd, struct kms_driver **out) +{ + char *name; + int ret; + + ret = linux_name_from_sysfs(fd, &name); + if (ret) + return ret; + + if (!strcmp(name, "intel")) + ret = intel_create(fd, out); +#ifdef HAVE_VMWGFX + else if (!strcmp(name, "vmwgfx")) + ret = vmwgfx_create(fd, out); +#endif +#ifdef HAVE_NOUVEAU + else if (!strcmp(name, "nouveau")) + ret = nouveau_create(fd, out); +#endif +#ifdef HAVE_RADEON + else if (!strcmp(name, "radeon")) + ret = radeon_create(fd, out); +#endif + else + ret = -ENOSYS; + + free(name); + return ret; +} + +#if 0 +#define LIBUDEV_I_KNOW_THE_API_IS_SUBJECT_TO_CHANGE +#include + +struct create_record +{ + unsigned vendor; + unsigned chip; + int (*func)(int fd, struct kms_driver **out); +}; + +static struct create_record table[] = { + { 0x8086, 0x2a42, intel_create }, /* i965 */ +#ifdef HAVE_VMWGFX + { 0x15ad, 0x0405, vmwgfx_create }, /* VMware vGPU */ +#endif + { 0, 0, NULL }, +}; + +static int +linux_get_pciid_from_fd(int fd, unsigned *vendor_id, unsigned *chip_id) +{ + struct udev *udev; + struct udev_device *device; + struct udev_device *parent; + const char *pci_id; + struct stat buffer; + int ret; + + ret = fstat(fd, &buffer); + if (ret) + return -EINVAL; + + if (!S_ISCHR(buffer.st_mode)) + return -EINVAL; + + udev = udev_new(); + if (!udev) + return -ENOMEM; + + device = udev_device_new_from_devnum(udev, 'c', buffer.st_rdev); + if (!device) + goto err_free_udev; + + parent = udev_device_get_parent(device); + if (!parent) + goto err_free_device; + + pci_id = udev_device_get_property_value(parent, "PCI_ID"); + if (!pci_id) + goto err_free_device; + + if (sscanf(pci_id, "%x:%x", vendor_id, chip_id) != 2) + goto err_free_device; + + udev_device_unref(device); + udev_unref(udev); + + return 0; + +err_free_device: + udev_device_unref(device); +err_free_udev: + udev_unref(udev); + return -EINVAL; +} + +static int +linux_from_udev(int fd, struct kms_driver **out) +{ + unsigned vendor_id, chip_id; + int ret, i; + + ret = linux_get_pciid_from_fd(fd, &vendor_id, &chip_id); + if (ret) + return ret; + + for (i = 0; table[i].func; i++) + if (table[i].vendor == vendor_id && table[i].chip == chip_id) + return table[i].func(fd, out); + + return -ENOSYS; +} +#else +static int +linux_from_udev(int fd, struct kms_driver **out) +{ + return -ENOSYS; +} +#endif + +int +linux_create(int fd, struct kms_driver **out) +{ + if (!dumb_create(fd, out)) + return 0; + + if (!linux_from_udev(fd, out)) + return 0; + + return linux_from_sysfs(fd, out); +} diff --git a/libkms/nouveau.c b/libkms/nouveau.c new file mode 100644 index 0000000..0e24a15 --- /dev/null +++ b/libkms/nouveau.c @@ -0,0 +1,220 @@ +/************************************************************************** + * + * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + + +#define HAVE_STDINT_H +#define _FILE_OFFSET_BITS 64 + +#include +#include +#include +#include +#include "internal.h" + +#include +#include +#include "xf86drm.h" + +#include "nouveau_drm.h" + +struct nouveau_bo +{ + struct kms_bo base; + uint64_t map_handle; + unsigned map_count; +}; + +static int +nouveau_get_prop(struct kms_driver *kms, unsigned key, unsigned *out) +{ + switch (key) { + case KMS_BO_TYPE: + *out = KMS_BO_TYPE_SCANOUT_X8R8G8B8 | KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8; + break; + default: + return -EINVAL; + } + return 0; +} + +static int +nouveau_destroy(struct kms_driver *kms) +{ + free(kms); + return 0; +} + +static int +nouveau_bo_create(struct kms_driver *kms, + const unsigned width, const unsigned height, + const enum kms_bo_type type, const unsigned *attr, + struct kms_bo **out) +{ + struct drm_nouveau_gem_new arg; + unsigned size, pitch; + struct nouveau_bo *bo; + int i, ret; + + for (i = 0; attr[i]; i += 2) { + switch (attr[i]) { + case KMS_WIDTH: + case KMS_HEIGHT: + case KMS_BO_TYPE: + break; + default: + return -EINVAL; + } + } + + bo = calloc(1, sizeof(*bo)); + if (!bo) + return -ENOMEM; + + if (type == KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8) { + pitch = 64 * 4; + size = 64 * 64 * 4; + } else if (type == KMS_BO_TYPE_SCANOUT_X8R8G8B8) { + pitch = width * 4; + pitch = (pitch + 512 - 1) & ~(512 - 1); + size = pitch * height; + } else { + return -EINVAL; + } + + memset(&arg, 0, sizeof(arg)); + arg.info.size = size; + arg.info.domain = NOUVEAU_GEM_DOMAIN_MAPPABLE | NOUVEAU_GEM_DOMAIN_VRAM; + arg.info.tile_mode = 0; + arg.info.tile_flags = 0; + arg.align = 512; + arg.channel_hint = 0; + + ret = drmCommandWriteRead(kms->fd, DRM_NOUVEAU_GEM_NEW, &arg, sizeof(arg)); + if (ret) + goto err_free; + + bo->base.kms = kms; + bo->base.handle = arg.info.handle; + bo->base.size = size; + bo->base.pitch = pitch; + bo->map_handle = arg.info.map_handle; + + *out = &bo->base; + + return 0; + +err_free: + free(bo); + return ret; +} + +static int +nouveau_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out) +{ + switch (key) { + default: + return -EINVAL; + } +} + +static int +nouveau_bo_map(struct kms_bo *_bo, void **out) +{ + struct nouveau_bo *bo = (struct nouveau_bo *)_bo; + void *map = NULL; + + if (bo->base.ptr) { + bo->map_count++; + *out = bo->base.ptr; + return 0; + } + + map = mmap(0, bo->base.size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->base.kms->fd, bo->map_handle); + if (map == MAP_FAILED) + return -errno; + + bo->base.ptr = map; + bo->map_count++; + *out = bo->base.ptr; + + return 0; +} + +static int +nouveau_bo_unmap(struct kms_bo *_bo) +{ + struct nouveau_bo *bo = (struct nouveau_bo *)_bo; + bo->map_count--; + return 0; +} + +static int +nouveau_bo_destroy(struct kms_bo *_bo) +{ + struct nouveau_bo *bo = (struct nouveau_bo *)_bo; + struct drm_gem_close arg; + int ret; + + if (bo->base.ptr) { + /* XXX Sanity check map_count */ + munmap(bo->base.ptr, bo->base.size); + bo->base.ptr = NULL; + } + + memset(&arg, 0, sizeof(arg)); + arg.handle = bo->base.handle; + + ret = drmIoctl(bo->base.kms->fd, DRM_IOCTL_GEM_CLOSE, &arg); + if (ret) + return -errno; + + free(bo); + return 0; +} + +int +nouveau_create(int fd, struct kms_driver **out) +{ + struct kms_driver *kms; + + kms = calloc(1, sizeof(*kms)); + if (!kms) + return -ENOMEM; + + kms->fd = fd; + + kms->bo_create = nouveau_bo_create; + kms->bo_map = nouveau_bo_map; + kms->bo_unmap = nouveau_bo_unmap; + kms->bo_get_prop = nouveau_bo_get_prop; + kms->bo_destroy = nouveau_bo_destroy; + kms->get_prop = nouveau_get_prop; + kms->destroy = nouveau_destroy; + *out = kms; + + return 0; +} diff --git a/libkms/radeon.c b/libkms/radeon.c new file mode 100644 index 0000000..f5e382a --- /dev/null +++ b/libkms/radeon.c @@ -0,0 +1,242 @@ +/************************************************************************** + * + * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + + +#define HAVE_STDINT_H +#define _FILE_OFFSET_BITS 64 + +#include +#include +#include +#include +#include "internal.h" + +#include +#include +#include "xf86drm.h" + +#include "radeon_drm.h" + + +#define ALIGNMENT 512 + +struct radeon_bo +{ + struct kms_bo base; + unsigned map_count; +}; + +static int +radeon_get_prop(struct kms_driver *kms, unsigned key, unsigned *out) +{ + switch (key) { + case KMS_BO_TYPE: + *out = KMS_BO_TYPE_SCANOUT_X8R8G8B8 | KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8; + break; + default: + return -EINVAL; + } + return 0; +} + +static int +radeon_destroy(struct kms_driver *kms) +{ + free(kms); + return 0; +} + +static int +radeon_bo_create(struct kms_driver *kms, + const unsigned width, const unsigned height, + const enum kms_bo_type type, const unsigned *attr, + struct kms_bo **out) +{ + struct drm_radeon_gem_create arg; + unsigned size, pitch; + struct radeon_bo *bo; + int i, ret; + + for (i = 0; attr[i]; i += 2) { + switch (attr[i]) { + case KMS_WIDTH: + case KMS_HEIGHT: + case KMS_BO_TYPE: + break; + default: + return -EINVAL; + } + } + + switch (type) { + case KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8: + pitch = 4 * 64; + size = 4 * 64 * 64; + break; + case KMS_BO_TYPE_SCANOUT_X8R8G8B8: + pitch = width * 4; + pitch = (pitch + ALIGNMENT - 1) & ~(ALIGNMENT - 1); + size = pitch * height; + break; + default: + return -EINVAL; + } + + bo = calloc(1, sizeof(*bo)); + if (!bo) + return -ENOMEM; + + memset(&arg, 0, sizeof(arg)); + arg.size = size; + arg.alignment = ALIGNMENT; + arg.initial_domain = RADEON_GEM_DOMAIN_CPU; + arg.flags = 0; + arg.handle = 0; + + ret = drmCommandWriteRead(kms->fd, DRM_RADEON_GEM_CREATE, + &arg, sizeof(arg)); + if (ret) + goto err_free; + + bo->base.kms = kms; + bo->base.handle = arg.handle; + bo->base.size = size; + bo->base.pitch = pitch; + bo->base.offset = 0; + bo->map_count = 0; + + *out = &bo->base; + + return 0; + +err_free: + free(bo); + return ret; +} + +static int +radeon_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out) +{ + switch (key) { + default: + return -EINVAL; + } +} + +static int +radeon_bo_map(struct kms_bo *_bo, void **out) +{ + struct radeon_bo *bo = (struct radeon_bo *)_bo; + struct drm_radeon_gem_mmap arg; + void *map = NULL; + int ret; + + if (bo->base.ptr) { + bo->map_count++; + *out = bo->base.ptr; + return 0; + } + + memset(&arg, 0, sizeof(arg)); + arg.handle = bo->base.handle; + arg.offset = bo->base.offset; + arg.size = (uint64_t)bo->base.size; + + ret = drmCommandWriteRead(bo->base.kms->fd, DRM_RADEON_GEM_MMAP, + &arg, sizeof(arg)); + if (ret) + return -errno; + + map = mmap(0, arg.size, PROT_READ | PROT_WRITE, MAP_SHARED, + bo->base.kms->fd, arg.addr_ptr); + if (map == MAP_FAILED) + return -errno; + + bo->base.ptr = map; + bo->map_count++; + *out = bo->base.ptr; + + return 0; +} + +static int +radeon_bo_unmap(struct kms_bo *_bo) +{ + struct radeon_bo *bo = (struct radeon_bo *)_bo; + if (--bo->map_count == 0) { + munmap(bo->base.ptr, bo->base.size); + bo->base.ptr = NULL; + } + return 0; +} + +static int +radeon_bo_destroy(struct kms_bo *_bo) +{ + struct radeon_bo *bo = (struct radeon_bo *)_bo; + struct drm_gem_close arg; + int ret; + + if (bo->base.ptr) { + /* XXX Sanity check map_count */ + munmap(bo->base.ptr, bo->base.size); + bo->base.ptr = NULL; + } + + memset(&arg, 0, sizeof(arg)); + arg.handle = bo->base.handle; + + ret = drmIoctl(bo->base.kms->fd, DRM_IOCTL_GEM_CLOSE, &arg); + if (ret) + return -errno; + + free(bo); + return 0; +} + +int +radeon_create(int fd, struct kms_driver **out) +{ + struct kms_driver *kms; + + kms = calloc(1, sizeof(*kms)); + if (!kms) + return -ENOMEM; + + kms->fd = fd; + + kms->bo_create = radeon_bo_create; + kms->bo_map = radeon_bo_map; + kms->bo_unmap = radeon_bo_unmap; + kms->bo_get_prop = radeon_bo_get_prop; + kms->bo_destroy = radeon_bo_destroy; + kms->get_prop = radeon_get_prop; + kms->destroy = radeon_destroy; + *out = kms; + + return 0; +} diff --git a/libkms/slp.c b/libkms/slp.c new file mode 100644 index 0000000..263f2ab --- /dev/null +++ b/libkms/slp.c @@ -0,0 +1,222 @@ +/************************************************************************** + * + * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + + +#define HAVE_STDINT_H +#define _FILE_OFFSET_BITS 64 + +#include +#include +#include +#include +#include "internal.h" + +#include +#include +#include "xf86drm.h" + +#include "exynos_drm.h" + +struct slp_bo +{ + struct kms_bo base; + unsigned map_count; +}; + +static int +slp_get_prop(struct kms_driver *kms, unsigned key, unsigned *out) +{ + switch (key) { + case KMS_BO_TYPE: + *out = KMS_BO_TYPE_SCANOUT_X8R8G8B8 | KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8; + break; + default: + return -EINVAL; + } + return 0; +} + +static int +slp_destroy(struct kms_driver *kms) +{ + free(kms); + return 0; +} + +static int +slp_bo_create(struct kms_driver *kms, + const unsigned width, const unsigned height, + const enum kms_bo_type type, const unsigned *attr, + struct kms_bo **out) +{ + struct drm_exynos_gem_create arg; + unsigned size, pitch; + struct slp_bo *bo; + int i, ret; + + for (i = 0; attr[i]; i += 2) { + switch (attr[i]) { + case KMS_WIDTH: + case KMS_HEIGHT: + case KMS_BO_TYPE: + break; + default: + return -EINVAL; + } + } + + bo = calloc(1, sizeof(*bo)); + if (!bo) + return -ENOMEM; + + if (type == KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8) { + pitch = 64 * 4; + size = 64 * 64 * 4; + } else if (type == KMS_BO_TYPE_SCANOUT_X8R8G8B8) { + pitch = width * 4; + pitch = (pitch + 512 - 1) & ~(512 - 1); + size = pitch * ((height + 4 - 1) & ~(4 - 1)); + } else { + return -EINVAL; + } + + memset(&arg, 0, sizeof(arg)); + arg.size = size; + + ret = drmCommandWriteRead(kms->fd, DRM_EXYNOS_GEM_CREATE, &arg, sizeof(arg)); + if (ret) + goto err_free; + + bo->base.kms = kms; + bo->base.handle = arg.handle; + bo->base.size = size; + bo->base.pitch = pitch; + + *out = &bo->base; + + return 0; + +err_free: + free(bo); + return ret; +} + +static int +slp_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out) +{ + switch (key) { + default: + return -EINVAL; + } +} + +static int +slp_bo_map(struct kms_bo *_bo, void **out) +{ + struct slp_bo *bo = (struct slp_bo *)_bo; + struct drm_exynos_gem_map_off arg; + void *map = NULL; + int ret; + + if (bo->base.ptr) { + bo->map_count++; + *out = bo->base.ptr; + return 0; + } + + memset(&arg, 0, sizeof(arg)); + arg.handle = bo->base.handle; + + ret = drmCommandWriteRead(bo->base.kms->fd, DRM_EXYNOS_GEM_MAP_OFFSET, &arg, sizeof(arg)); + if (ret) + return ret; + + map = mmap(0, bo->base.size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->base.kms->fd, arg.offset); + if (map == MAP_FAILED) + return -errno; + + bo->base.ptr = map; + bo->map_count++; + *out = bo->base.ptr; + + return 0; +} + +static int +slp_bo_unmap(struct kms_bo *_bo) +{ + struct slp_bo *bo = (struct slp_bo *)_bo; + bo->map_count--; + return 0; +} + +static int +slp_bo_destroy(struct kms_bo *_bo) +{ + struct slp_bo *bo = (struct slp_bo *)_bo; + struct drm_gem_close arg; + int ret; + + if (bo->base.ptr) { + /* XXX Sanity check map_count */ + munmap(bo->base.ptr, bo->base.size); + bo->base.ptr = NULL; + } + + memset(&arg, 0, sizeof(arg)); + arg.handle = bo->base.handle; + + ret = drmIoctl(bo->base.kms->fd, DRM_IOCTL_GEM_CLOSE, &arg); + if (ret) + return -errno; + + free(bo); + return 0; +} + +int +slp_create(int fd, struct kms_driver **out) +{ + struct kms_driver *kms; + + kms = calloc(1, sizeof(*kms)); + if (!kms) + return -ENOMEM; + + kms->fd = fd; + + kms->bo_create = slp_bo_create; + kms->bo_map = slp_bo_map; + kms->bo_unmap = slp_bo_unmap; + kms->bo_get_prop = slp_bo_get_prop; + kms->bo_destroy = slp_bo_destroy; + kms->get_prop = slp_get_prop; + kms->destroy = slp_destroy; + *out = kms; + + return 0; +} diff --git a/libkms/vmwgfx.c b/libkms/vmwgfx.c new file mode 100644 index 0000000..d594b3b --- /dev/null +++ b/libkms/vmwgfx.c @@ -0,0 +1,207 @@ +/************************************************************************** + * + * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + + +#define HAVE_STDINT_H +#define _FILE_OFFSET_BITS 64 + +#include +#include +#include +#include "internal.h" + +#include +#include "xf86drm.h" +#include "vmwgfx_drm.h" + +struct vmwgfx_bo +{ + struct kms_bo base; + uint64_t map_handle; + unsigned map_count; +}; + +static int +vmwgfx_get_prop(struct kms_driver *kms, unsigned key, unsigned *out) +{ + switch (key) { + case KMS_BO_TYPE: + *out = KMS_BO_TYPE_SCANOUT_X8R8G8B8 | KMS_BO_TYPE_CURSOR_64X64_A8R8G8B8; + break; + default: + return -EINVAL; + } + return 0; +} + +static int +vmwgfx_destroy(struct kms_driver *kms) +{ + free(kms); + return 0; +} + +static int +vmwgfx_bo_create(struct kms_driver *kms, + const unsigned width, const unsigned height, + const enum kms_bo_type type, const unsigned *attr, + struct kms_bo **out) +{ + struct vmwgfx_bo *bo; + int i, ret; + + for (i = 0; attr[i]; i += 2) { + switch (attr[i]) { + case KMS_WIDTH: + case KMS_HEIGHT: + case KMS_BO_TYPE: + break; + default: + return -EINVAL; + } + } + + bo = calloc(1, sizeof(*bo)); + if (!bo) + return -EINVAL; + + { + union drm_vmw_alloc_dmabuf_arg arg; + struct drm_vmw_alloc_dmabuf_req *req = &arg.req; + struct drm_vmw_dmabuf_rep *rep = &arg.rep; + + memset(&arg, 0, sizeof(arg)); + req->size = width * height * 4; + bo->base.size = req->size; + bo->base.pitch = width * 4; + bo->base.kms = kms; + + do { + ret = drmCommandWriteRead(bo->base.kms->fd, + DRM_VMW_ALLOC_DMABUF, + &arg, sizeof(arg)); + } while (ret == -ERESTART); + + if (ret) + goto err_free; + + bo->base.handle = rep->handle; + bo->map_handle = rep->map_handle; + bo->base.handle = rep->cur_gmr_id; + bo->base.offset = rep->cur_gmr_offset; + } + + *out = &bo->base; + + return 0; + +err_free: + free(bo); + return ret; +} + +static int +vmwgfx_bo_get_prop(struct kms_bo *bo, unsigned key, unsigned *out) +{ + switch (key) { + default: + return -EINVAL; + } +} + +static int +vmwgfx_bo_map(struct kms_bo *_bo, void **out) +{ + struct vmwgfx_bo *bo = (struct vmwgfx_bo *)_bo; + void *map; + + if (bo->base.ptr) { + bo->map_count++; + *out = bo->base.ptr; + return 0; + } + + map = mmap(NULL, bo->base.size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->base.kms->fd, bo->map_handle); + if (map == MAP_FAILED) + return -errno; + + bo->base.ptr = map; + bo->map_count++; + *out = bo->base.ptr; + + return 0; +} + +static int +vmwgfx_bo_unmap(struct kms_bo *_bo) +{ + struct vmwgfx_bo *bo = (struct vmwgfx_bo *)_bo; + bo->map_count--; + return 0; +} + +static int +vmwgfx_bo_destroy(struct kms_bo *_bo) +{ + struct vmwgfx_bo *bo = (struct vmwgfx_bo *)_bo; + struct drm_vmw_unref_dmabuf_arg arg; + + if (bo->base.ptr) { + /* XXX Sanity check map_count */ + munmap(bo->base.ptr, bo->base.size); + bo->base.ptr = NULL; + } + + memset(&arg, 0, sizeof(arg)); + arg.handle = bo->base.handle; + drmCommandWrite(bo->base.kms->fd, DRM_VMW_UNREF_DMABUF, &arg, sizeof(arg)); + + free(bo); + return 0; +} + +int +vmwgfx_create(int fd, struct kms_driver **out) +{ + struct kms_driver *kms; + + kms = calloc(1, sizeof(*kms)); + if (!kms) + return -ENOMEM; + + kms->fd = fd; + + kms->bo_create = vmwgfx_bo_create; + kms->bo_map = vmwgfx_bo_map; + kms->bo_unmap = vmwgfx_bo_unmap; + kms->bo_get_prop = vmwgfx_bo_get_prop; + kms->bo_destroy = vmwgfx_bo_destroy; + kms->get_prop = vmwgfx_get_prop; + kms->destroy = vmwgfx_destroy; + *out = kms; + return 0; +} diff --git a/m4/.gitignore b/m4/.gitignore new file mode 100644 index 0000000..464ba5c --- /dev/null +++ b/m4/.gitignore @@ -0,0 +1,5 @@ +libtool.m4 +lt~obsolete.m4 +ltoptions.m4 +ltsugar.m4 +ltversion.m4 diff --git a/nouveau/Makefile.am b/nouveau/Makefile.am new file mode 100644 index 0000000..206e892 --- /dev/null +++ b/nouveau/Makefile.am @@ -0,0 +1,25 @@ +AM_CFLAGS = \ + $(WARN_CFLAGS) \ + -I$(top_srcdir) \ + -I$(top_srcdir)/nouveau \ + $(PTHREADSTUBS_CFLAGS) \ + -I$(top_srcdir)/include/drm \ + -DDEBUG + +libdrm_nouveau_la_LTLIBRARIES = libdrm_nouveau.la +libdrm_nouveau_ladir = $(libdir) +libdrm_nouveau_la_LDFLAGS = -version-number 2:0:0 -no-undefined +libdrm_nouveau_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@ + +libdrm_nouveau_la_SOURCES = nouveau.c \ + pushbuf.c \ + bufctx.c \ + abi16.c \ + private.h + + +libdrm_nouveauincludedir = ${includedir}/libdrm +libdrm_nouveauinclude_HEADERS = nouveau.h + +pkgconfigdir = @pkgconfigdir@ +pkgconfig_DATA = libdrm_nouveau.pc diff --git a/nouveau/abi16.c b/nouveau/abi16.c new file mode 100644 index 0000000..69a0a9b --- /dev/null +++ b/nouveau/abi16.c @@ -0,0 +1,198 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#include +#include + +#include "private.h" + +int +abi16_chan_nv04(struct nouveau_object *obj) +{ + struct nouveau_device *dev = (struct nouveau_device *)obj->parent; + struct drm_nouveau_channel_alloc req; + struct nv04_fifo *nv04 = obj->data; + int ret; + + req.fb_ctxdma_handle = nv04->vram; + req.tt_ctxdma_handle = nv04->gart; + + ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_CHANNEL_ALLOC, + &req, sizeof(req)); + if (ret) + return ret; + + nv04->base.channel = req.channel; + nv04->base.pushbuf = req.pushbuf_domains; + nv04->notify = req.notifier_handle; + nv04->base.object->handle = req.channel; + nv04->base.object->length = sizeof(*nv04); + return 0; +} + +int +abi16_chan_nvc0(struct nouveau_object *obj) +{ + struct nouveau_device *dev = (struct nouveau_device *)obj->parent; + struct drm_nouveau_channel_alloc req = {}; + struct nvc0_fifo *nvc0 = obj->data; + int ret; + + ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_CHANNEL_ALLOC, + &req, sizeof(req)); + if (ret) + return ret; + + nvc0->base.channel = req.channel; + nvc0->base.pushbuf = req.pushbuf_domains; + nvc0->notify = req.notifier_handle; + nvc0->base.object->handle = req.channel; + nvc0->base.object->length = sizeof(*nvc0); + return 0; +} + +int +abi16_engobj(struct nouveau_object *obj) +{ + struct drm_nouveau_grobj_alloc req = { + obj->parent->handle, obj->handle, obj->oclass + }; + struct nouveau_device *dev; + int ret; + + dev = nouveau_object_find(obj, NOUVEAU_DEVICE_CLASS); + ret = drmCommandWrite(dev->fd, DRM_NOUVEAU_GROBJ_ALLOC, + &req, sizeof(req)); + if (ret) + return ret; + + obj->length = sizeof(struct nouveau_object *); + return 0; +} + +int +abi16_ntfy(struct nouveau_object *obj) +{ + struct nv04_notify *ntfy = obj->data; + struct drm_nouveau_notifierobj_alloc req = { + obj->parent->handle, ntfy->object->handle, ntfy->length + }; + struct nouveau_device *dev; + int ret; + + dev = nouveau_object_find(obj, NOUVEAU_DEVICE_CLASS); + ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, + &req, sizeof(req)); + if (ret) + return ret; + + ntfy->offset = req.offset; + ntfy->object->length = sizeof(*ntfy); + return 0; +} + +void +abi16_bo_info(struct nouveau_bo *bo, struct drm_nouveau_gem_info *info) +{ + struct nouveau_bo_priv *nvbo = nouveau_bo(bo); + + nvbo->map_handle = info->map_handle; + bo->handle = info->handle; + bo->size = info->size; + bo->offset = info->offset; + + bo->flags = 0; + if (info->domain & NOUVEAU_GEM_DOMAIN_VRAM) + bo->flags |= NOUVEAU_BO_VRAM; + if (info->domain & NOUVEAU_GEM_DOMAIN_GART) + bo->flags |= NOUVEAU_BO_GART; + if (!(info->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)) + bo->flags |= NOUVEAU_BO_CONTIG; + if (nvbo->map_handle) + bo->flags |= NOUVEAU_BO_MAP; + + if (bo->device->chipset >= 0xc0) { + bo->config.nvc0.memtype = (info->tile_flags & 0xff00) >> 8; + bo->config.nvc0.tile_mode = info->tile_mode; + } else + if (bo->device->chipset >= 0x80 || bo->device->chipset == 0x50) { + bo->config.nv50.memtype = (info->tile_flags & 0x07f00) >> 8 | + (info->tile_flags & 0x30000) >> 9; + bo->config.nv50.tile_mode = info->tile_mode << 4; + } else { + bo->config.nv04.surf_flags = info->tile_flags & 7; + bo->config.nv04.surf_pitch = info->tile_mode; + } +} + +int +abi16_bo_init(struct nouveau_bo *bo, uint32_t alignment, + union nouveau_bo_config *config) +{ + struct nouveau_device *dev = bo->device; + struct drm_nouveau_gem_new req = {}; + struct drm_nouveau_gem_info *info = &req.info; + int ret; + + if (bo->flags & NOUVEAU_BO_VRAM) + info->domain |= NOUVEAU_GEM_DOMAIN_VRAM; + if (bo->flags & NOUVEAU_BO_GART) + info->domain |= NOUVEAU_GEM_DOMAIN_GART; + if (!info->domain) + info->domain |= NOUVEAU_GEM_DOMAIN_VRAM | + NOUVEAU_GEM_DOMAIN_GART; + + if (bo->flags & NOUVEAU_BO_MAP) + info->domain |= NOUVEAU_GEM_DOMAIN_MAPPABLE; + + if (!(bo->flags & NOUVEAU_BO_CONTIG)) + info->tile_flags = NOUVEAU_GEM_TILE_NONCONTIG; + + info->size = bo->size; + req.align = alignment; + + if (config) { + if (dev->chipset >= 0xc0) { + info->tile_flags = (config->nvc0.memtype & 0xff) << 8; + info->tile_mode = config->nvc0.tile_mode; + } else + if (dev->chipset >= 0x80 || dev->chipset == 0x50) { + info->tile_flags = (config->nv50.memtype & 0x07f) << 8 | + (config->nv50.memtype & 0x180) << 9; + info->tile_mode = config->nv50.tile_mode >> 4; + } else { + info->tile_flags = config->nv04.surf_flags & 7; + info->tile_mode = config->nv04.surf_pitch; + } + } + + if (!nouveau_device(dev)->have_bo_usage) + info->tile_flags &= 0x0000ff00; + + ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_GEM_NEW, + &req, sizeof(req)); + if (ret == 0) + abi16_bo_info(bo, &req.info); + return ret; +} diff --git a/nouveau/bufctx.c b/nouveau/bufctx.c new file mode 100644 index 0000000..23d6f09 --- /dev/null +++ b/nouveau/bufctx.c @@ -0,0 +1,170 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include +#include +#include +#include +#include +#include + +#include "libdrm_lists.h" + +#include "nouveau.h" +#include "private.h" + +struct nouveau_bufref_priv { + struct nouveau_bufref base; + struct nouveau_bufref_priv *next; + struct nouveau_bufctx *bufctx; +}; + +static inline struct nouveau_bufref_priv * +nouveau_bufref(struct nouveau_bufref *bctx) +{ + return (struct nouveau_bufref_priv *)bctx; +} + +struct nouveau_bufbin_priv { + struct nouveau_bufref_priv *list; + int relocs; +}; + +struct nouveau_bufctx_priv { + struct nouveau_bufctx base; + struct nouveau_bufref_priv *free; + int nr_bins; + struct nouveau_bufbin_priv bins[]; +}; + +static inline struct nouveau_bufctx_priv * +nouveau_bufctx(struct nouveau_bufctx *bctx) +{ + return (struct nouveau_bufctx_priv *)bctx; +} + +int +nouveau_bufctx_new(struct nouveau_client *client, int bins, + struct nouveau_bufctx **pbctx) +{ + struct nouveau_bufctx_priv *priv; + + priv = calloc(1, sizeof(*priv) + sizeof(priv->bins[0]) * bins); + if (priv) { + DRMINITLISTHEAD(&priv->base.head); + DRMINITLISTHEAD(&priv->base.pending); + DRMINITLISTHEAD(&priv->base.current); + priv->base.client = client; + priv->nr_bins = bins; + *pbctx = &priv->base; + return 0; + } + + return -ENOMEM; +} + +void +nouveau_bufctx_del(struct nouveau_bufctx **pbctx) +{ + struct nouveau_bufctx_priv *pctx = nouveau_bufctx(*pbctx); + struct nouveau_bufref_priv *pref; + if (pctx) { + while (pctx->nr_bins--) + nouveau_bufctx_reset(&pctx->base, pctx->nr_bins); + while ((pref = pctx->free)) { + pctx->free = pref->next; + free(pref); + } + free(pctx); + *pbctx = NULL; + } +} + +void +nouveau_bufctx_reset(struct nouveau_bufctx *bctx, int bin) +{ + struct nouveau_bufctx_priv *pctx = nouveau_bufctx(bctx); + struct nouveau_bufbin_priv *pbin = &pctx->bins[bin]; + struct nouveau_bufref_priv *pref; + + while ((pref = pbin->list)) { + DRMLISTDELINIT(&pref->base.thead); + pbin->list = pref->next; + pref->next = pctx->free; + pctx->free = pref; + } + + bctx->relocs -= pbin->relocs; + pbin->relocs = 0; +} + +struct nouveau_bufref * +nouveau_bufctx_refn(struct nouveau_bufctx *bctx, int bin, + struct nouveau_bo *bo, uint32_t flags) +{ + struct nouveau_bufctx_priv *pctx = nouveau_bufctx(bctx); + struct nouveau_bufbin_priv *pbin = &pctx->bins[bin]; + struct nouveau_bufref_priv *pref = pctx->free; + + if (!pref) + pref = malloc(sizeof(*pref)); + else + pctx->free = pref->next; + + if (pref) { + pref->base.bo = bo; + pref->base.flags = flags; + pref->base.packet = 0; + + DRMLISTADDTAIL(&pref->base.thead, &bctx->pending); + pref->bufctx = bctx; + pref->next = pbin->list; + pbin->list = pref; + } + + return &pref->base; +} + +struct nouveau_bufref * +nouveau_bufctx_mthd(struct nouveau_bufctx *bctx, int bin, uint32_t packet, + struct nouveau_bo *bo, uint64_t data, uint32_t flags, + uint32_t vor, uint32_t tor) +{ + struct nouveau_bufctx_priv *pctx = nouveau_bufctx(bctx); + struct nouveau_bufbin_priv *pbin = &pctx->bins[bin]; + struct nouveau_bufref *bref = nouveau_bufctx_refn(bctx, bin, bo, flags); + if (bref) { + bref->packet = packet; + bref->data = data; + bref->vor = vor; + bref->tor = tor; + pbin->relocs++; + bctx->relocs++; + } + return bref; +} diff --git a/nouveau/libdrm_nouveau.pc.in b/nouveau/libdrm_nouveau.pc.in new file mode 100644 index 0000000..6170613 --- /dev/null +++ b/nouveau/libdrm_nouveau.pc.in @@ -0,0 +1,11 @@ +prefix=@prefix@ +exec_prefix=@exec_prefix@ +libdir=@libdir@ +includedir=@includedir@ + +Name: libdrm_nouveau +Description: Userspace interface to nouveau kernel DRM services +Version: 2.4.33 +Libs: -L${libdir} -ldrm_nouveau +Cflags: -I${includedir} -I${includedir}/libdrm -I${includedir}/nouveau +Requires.private: libdrm diff --git a/nouveau/nouveau.c b/nouveau/nouveau.c new file mode 100644 index 0000000..5aa4107 --- /dev/null +++ b/nouveau/nouveau.c @@ -0,0 +1,492 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "libdrm_lists.h" +#include "nouveau_drm.h" + +#include "nouveau.h" +#include "private.h" + +#ifdef DEBUG +uint32_t nouveau_debug = 0; + +static void +debug_init(char *args) +{ + if (args) { + int n = strtol(args, NULL, 0); + if (n >= 0) + nouveau_debug = n; + } +} +#endif + +/* this is the old libdrm's version of nouveau_device_wrap(), the symbol + * is kept here to prevent AIGLX from crashing if the DDX is linked against + * the new libdrm, but the DRI driver against the old + */ +int +nouveau_device_open_existing(struct nouveau_device **pdev, int close, int fd, + drm_context_t ctx) +{ + return -EACCES; +} + +int +nouveau_device_wrap(int fd, int close, struct nouveau_device **pdev) +{ + struct nouveau_device_priv *nvdev = calloc(1, sizeof(*nvdev)); + struct nouveau_device *dev = &nvdev->base; + uint64_t chipset, vram, gart, bousage; + drmVersionPtr ver; + int ret; + +#ifdef DEBUG + debug_init(getenv("NOUVEAU_LIBDRM_DEBUG")); +#endif + + if (!nvdev) + return -ENOMEM; + nvdev->base.fd = fd; + + ver = drmGetVersion(fd); + if (ver) dev->drm_version = (ver->version_major << 24) | + (ver->version_minor << 8) | + ver->version_patchlevel; + drmFreeVersion(ver); + + if ( dev->drm_version != 0x00000010 && + (dev->drm_version < 0x01000000 || + dev->drm_version >= 0x02000000)) { + nouveau_device_del(&dev); + return -EINVAL; + } + + ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_CHIPSET_ID, &chipset); + if (ret == 0) + ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_FB_SIZE, &vram); + if (ret == 0) + ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_AGP_SIZE, &gart); + if (ret) { + nouveau_device_del(&dev); + return ret; + } + + ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_HAS_BO_USAGE, &bousage); + if (ret == 0) + nvdev->have_bo_usage = (bousage != 0); + + nvdev->close = close; + DRMINITLISTHEAD(&nvdev->bo_list); + nvdev->base.object.oclass = NOUVEAU_DEVICE_CLASS; + nvdev->base.lib_version = 0x01000000; + nvdev->base.chipset = chipset; + nvdev->base.vram_size = vram; + nvdev->base.gart_size = gart; + nvdev->base.vram_limit = (nvdev->base.vram_size * 80) / 100; + nvdev->base.gart_limit = (nvdev->base.gart_size * 80) / 100; + + *pdev = &nvdev->base; + return 0; +} + +int +nouveau_device_open(const char *busid, struct nouveau_device **pdev) +{ + int ret = -ENODEV, fd = drmOpen("nouveau", busid); + if (fd >= 0) { + ret = nouveau_device_wrap(fd, 1, pdev); + if (ret) + drmClose(fd); + } + return ret; +} + +void +nouveau_device_del(struct nouveau_device **pdev) +{ + struct nouveau_device_priv *nvdev = nouveau_device(*pdev); + if (nvdev) { + if (nvdev->close) + drmClose(nvdev->base.fd); + free(nvdev->client); + free(nvdev); + *pdev = NULL; + } +} + +int +nouveau_getparam(struct nouveau_device *dev, uint64_t param, uint64_t *value) +{ + struct drm_nouveau_getparam r = { param, 0 }; + int fd = dev->fd, ret = + drmCommandWriteRead(fd, DRM_NOUVEAU_GETPARAM, &r, sizeof(r)); + *value = r.value; + return ret; +} + +int +nouveau_setparam(struct nouveau_device *dev, uint64_t param, uint64_t value) +{ + struct drm_nouveau_setparam r = { param, value }; + return drmCommandWrite(dev->fd, DRM_NOUVEAU_SETPARAM, &r, sizeof(r)); +} + +int +nouveau_client_new(struct nouveau_device *dev, struct nouveau_client **pclient) +{ + struct nouveau_device_priv *nvdev = nouveau_device(dev); + struct nouveau_client_priv *pcli; + int id = 0, i, ret = -ENOMEM; + uint32_t *clients; + + for (i = 0; i < nvdev->nr_client; i++) { + id = ffs(nvdev->client[i]) - 1; + if (id >= 0) + goto out; + } + + clients = realloc(nvdev->client, sizeof(uint32_t) * (i + 1)); + if (!clients) + return ret; + nvdev->client = clients; + nvdev->client[i] = 0; + nvdev->nr_client++; + +out: + pcli = calloc(1, sizeof(*pcli)); + if (pcli) { + nvdev->client[i] |= (1 << id); + pcli->base.device = dev; + pcli->base.id = (i * 32) + id; + ret = 0; + } + + *pclient = &pcli->base; + return ret; +} + +void +nouveau_client_del(struct nouveau_client **pclient) +{ + struct nouveau_client_priv *pcli = nouveau_client(*pclient); + struct nouveau_device_priv *nvdev; + if (pcli) { + int id = pcli->base.id; + nvdev = nouveau_device(pcli->base.device); + nvdev->client[id / 32] &= ~(1 << (id % 32)); + free(pcli->kref); + free(pcli); + } +} + +int +nouveau_object_new(struct nouveau_object *parent, uint64_t handle, + uint32_t oclass, void *data, uint32_t length, + struct nouveau_object **pobj) +{ + struct nouveau_device *dev; + struct nouveau_object *obj; + int ret = -EINVAL; + + if (length == 0) + length = sizeof(struct nouveau_object *); + obj = malloc(sizeof(*obj) + length); + obj->parent = parent; + obj->handle = handle; + obj->oclass = oclass; + obj->length = length; + obj->data = obj + 1; + if (data) + memcpy(obj->data, data, length); + *(struct nouveau_object **)obj->data = obj; + + dev = nouveau_object_find(obj, NOUVEAU_DEVICE_CLASS); + switch (parent->oclass) { + case NOUVEAU_DEVICE_CLASS: + switch (obj->oclass) { + case NOUVEAU_FIFO_CHANNEL_CLASS: + { + if (dev->chipset < 0xc0) + ret = abi16_chan_nv04(obj); + else + ret = abi16_chan_nvc0(obj); + } + break; + default: + break; + } + break; + case NOUVEAU_FIFO_CHANNEL_CLASS: + switch (obj->oclass) { + case NOUVEAU_NOTIFIER_CLASS: + ret = abi16_ntfy(obj); + break; + default: + ret = abi16_engobj(obj); + break; + } + default: + break; + } + + if (ret) { + free(obj); + return ret; + } + + *pobj = obj; + return 0; +} + +void +nouveau_object_del(struct nouveau_object **pobj) +{ + struct nouveau_object *obj = *pobj; + struct nouveau_device *dev; + if (obj) { + dev = nouveau_object_find(obj, NOUVEAU_DEVICE_CLASS); + if (obj->oclass == NOUVEAU_FIFO_CHANNEL_CLASS) { + struct drm_nouveau_channel_free req; + req.channel = obj->handle; + drmCommandWrite(dev->fd, DRM_NOUVEAU_CHANNEL_FREE, + &req, sizeof(req)); + } else { + struct drm_nouveau_gpuobj_free req; + req.channel = obj->parent->handle; + req.handle = obj->handle; + drmCommandWrite(dev->fd, DRM_NOUVEAU_GPUOBJ_FREE, + &req, sizeof(req)); + } + } + free(obj); + *pobj = NULL; +} + +void * +nouveau_object_find(struct nouveau_object *obj, uint32_t pclass) +{ + while (obj && obj->oclass != pclass) { + obj = obj->parent; + if (pclass == NOUVEAU_PARENT_CLASS) + break; + } + return obj; +} + +static void +nouveau_bo_del(struct nouveau_bo *bo) +{ + struct nouveau_bo_priv *nvbo = nouveau_bo(bo); + struct drm_gem_close req = { bo->handle }; + DRMLISTDEL(&nvbo->head); + if (bo->map) + munmap(bo->map, bo->size); + drmIoctl(bo->device->fd, DRM_IOCTL_GEM_CLOSE, &req); + free(nvbo); +} + +int +nouveau_bo_new(struct nouveau_device *dev, uint32_t flags, uint32_t align, + uint64_t size, union nouveau_bo_config *config, + struct nouveau_bo **pbo) +{ + struct nouveau_device_priv *nvdev = nouveau_device(dev); + struct nouveau_bo_priv *nvbo = calloc(1, sizeof(*nvbo)); + struct nouveau_bo *bo = &nvbo->base; + int ret; + + if (!nvbo) + return -ENOMEM; + atomic_set(&nvbo->refcnt, 1); + bo->device = dev; + bo->flags = flags; + bo->size = size; + + ret = abi16_bo_init(bo, align, config); + if (ret) { + free(nvbo); + return ret; + } + + DRMLISTADD(&nvbo->head, &nvdev->bo_list); + + *pbo = bo; + return 0; +} + +int +nouveau_bo_wrap(struct nouveau_device *dev, uint32_t handle, + struct nouveau_bo **pbo) +{ + struct nouveau_device_priv *nvdev = nouveau_device(dev); + struct drm_nouveau_gem_info req = { .handle = handle }; + struct nouveau_bo_priv *nvbo; + int ret; + + DRMLISTFOREACHENTRY(nvbo, &nvdev->bo_list, head) { + if (nvbo->base.handle == handle) { + *pbo = NULL; + nouveau_bo_ref(&nvbo->base, pbo); + return 0; + } + } + + ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_GEM_INFO, + &req, sizeof(req)); + if (ret) + return ret; + + nvbo = calloc(1, sizeof(*nvbo)); + if (nvbo) { + atomic_set(&nvbo->refcnt, 1); + nvbo->base.device = dev; + abi16_bo_info(&nvbo->base, &req); + DRMLISTADD(&nvbo->head, &nvdev->bo_list); + *pbo = &nvbo->base; + return 0; + } + + return -ENOMEM; +} + +int +nouveau_bo_name_ref(struct nouveau_device *dev, uint32_t name, + struct nouveau_bo **pbo) +{ + struct nouveau_device_priv *nvdev = nouveau_device(dev); + struct nouveau_bo_priv *nvbo; + struct drm_gem_open req = { .name = name }; + int ret; + + DRMLISTFOREACHENTRY(nvbo, &nvdev->bo_list, head) { + if (nvbo->name == name) { + *pbo = NULL; + nouveau_bo_ref(&nvbo->base, pbo); + return 0; + } + } + + ret = drmIoctl(dev->fd, DRM_IOCTL_GEM_OPEN, &req); + if (ret == 0) { + ret = nouveau_bo_wrap(dev, req.handle, pbo); + nouveau_bo((*pbo))->name = name; + } + + return ret; +} + +int +nouveau_bo_name_get(struct nouveau_bo *bo, uint32_t *name) +{ + struct drm_gem_flink req = { .handle = bo->handle }; + struct nouveau_bo_priv *nvbo = nouveau_bo(bo); + if (!nvbo->name) { + int ret = drmIoctl(bo->device->fd, DRM_IOCTL_GEM_FLINK, &req); + if (ret) + return ret; + nvbo->name = req.name; + } + *name = nvbo->name; + return 0; +} + +void +nouveau_bo_ref(struct nouveau_bo *bo, struct nouveau_bo **pref) +{ + struct nouveau_bo *ref = *pref; + if (bo) { + atomic_inc(&nouveau_bo(bo)->refcnt); + } + if (ref) { + if (atomic_dec_and_test(&nouveau_bo(ref)->refcnt)) + nouveau_bo_del(ref); + } + *pref = bo; +} + +int +nouveau_bo_wait(struct nouveau_bo *bo, uint32_t access, + struct nouveau_client *client) +{ + struct nouveau_bo_priv *nvbo = nouveau_bo(bo); + struct drm_nouveau_gem_cpu_prep req; + struct nouveau_pushbuf *push; + int ret = 0; + + if (!(access & NOUVEAU_BO_RDWR)) + return 0; + + push = cli_push_get(client, bo); + if (push && push->channel) + nouveau_pushbuf_kick(push, push->channel); + + if (!nvbo->name && !(nvbo->access & NOUVEAU_BO_WR) && + !( access & NOUVEAU_BO_WR)) + return 0; + + req.handle = bo->handle; + req.flags = 0; + if (access & NOUVEAU_BO_WR) + req.flags |= NOUVEAU_GEM_CPU_PREP_WRITE; + if (access & NOUVEAU_BO_NOBLOCK) + req.flags |= NOUVEAU_GEM_CPU_PREP_NOWAIT; + + ret = drmCommandWrite(bo->device->fd, DRM_NOUVEAU_GEM_CPU_PREP, + &req, sizeof(req)); + if (ret == 0) + nvbo->access = 0; + return ret; +} + +int +nouveau_bo_map(struct nouveau_bo *bo, uint32_t access, + struct nouveau_client *client) +{ + struct nouveau_bo_priv *nvbo = nouveau_bo(bo); + if (bo->map == NULL) { + bo->map = mmap(0, bo->size, PROT_READ | PROT_WRITE, + MAP_SHARED, bo->device->fd, nvbo->map_handle); + if (bo->map == MAP_FAILED) { + bo->map = NULL; + return -errno; + } + } + return nouveau_bo_wait(bo, access, client); +} diff --git a/nouveau/nouveau.h b/nouveau/nouveau.h new file mode 100644 index 0000000..51a9598 --- /dev/null +++ b/nouveau/nouveau.h @@ -0,0 +1,212 @@ +#ifndef __NOUVEAU_H__ +#define __NOUVEAU_H__ + +#include +#include + +#define NOUVEAU_DEVICE_CLASS 0x80000000 +#define NOUVEAU_FIFO_CHANNEL_CLASS 0x80000001 +#define NOUVEAU_NOTIFIER_CLASS 0x80000002 +#define NOUVEAU_PARENT_CLASS 0xffffffff + +struct nouveau_list { + struct nouveau_list *prev; + struct nouveau_list *next; +}; + +struct nouveau_object { + struct nouveau_object *parent; + uint64_t handle; + uint32_t oclass; + uint32_t length; + void *data; +}; + +struct nouveau_fifo { + struct nouveau_object *object; + uint32_t channel; + uint32_t pushbuf; + uint64_t unused1[3]; +}; + +struct nv04_fifo { + struct nouveau_fifo base; + uint32_t vram; + uint32_t gart; + uint32_t notify; +}; + +struct nvc0_fifo { + struct nouveau_fifo base; + uint32_t notify; +}; + +struct nv04_notify { + struct nouveau_object *object; + uint32_t offset; + uint32_t length; +}; + +int nouveau_object_new(struct nouveau_object *parent, uint64_t handle, + uint32_t oclass, void *data, uint32_t length, + struct nouveau_object **); +void nouveau_object_del(struct nouveau_object **); +void *nouveau_object_find(struct nouveau_object *, uint32_t parent_class); + +struct nouveau_device { + struct nouveau_object object; + int fd; + uint32_t lib_version; + uint32_t drm_version; + uint32_t chipset; + uint64_t vram_size; + uint64_t gart_size; + uint64_t vram_limit; + uint64_t gart_limit; +}; + +int nouveau_device_wrap(int fd, int close, struct nouveau_device **); +int nouveau_device_open(const char *busid, struct nouveau_device **); +void nouveau_device_del(struct nouveau_device **); +int nouveau_getparam(struct nouveau_device *, uint64_t param, uint64_t *value); +int nouveau_setparam(struct nouveau_device *, uint64_t param, uint64_t value); + +struct nouveau_client { + struct nouveau_device *device; + int id; +}; + +int nouveau_client_new(struct nouveau_device *, struct nouveau_client **); +void nouveau_client_del(struct nouveau_client **); + +union nouveau_bo_config { + struct { +#define NV04_BO_16BPP 0x00000001 +#define NV04_BO_32BPP 0x00000002 +#define NV04_BO_ZETA 0x00000004 + uint32_t surf_flags; + uint32_t surf_pitch; + } nv04; + struct { + uint32_t memtype; + uint32_t tile_mode; + } nv50; + struct { + uint32_t memtype; + uint32_t tile_mode; + } nvc0; + uint32_t data[8]; +}; + +#define NOUVEAU_BO_VRAM 0x00000001 +#define NOUVEAU_BO_GART 0x00000002 +#define NOUVEAU_BO_APER (NOUVEAU_BO_VRAM | NOUVEAU_BO_GART) +#define NOUVEAU_BO_RD 0x00000100 +#define NOUVEAU_BO_WR 0x00000200 +#define NOUVEAU_BO_RDWR (NOUVEAU_BO_RD | NOUVEAU_BO_WR) +#define NOUVEAU_BO_NOBLOCK 0x00000400 +#define NOUVEAU_BO_LOW 0x00001000 +#define NOUVEAU_BO_HIGH 0x00002000 +#define NOUVEAU_BO_OR 0x00004000 +#define NOUVEAU_BO_MAP 0x80000000 +#define NOUVEAU_BO_CONTIG 0x40000000 +#define NOUVEAU_BO_NOSNOOP 0x20000000 + +struct nouveau_bo { + struct nouveau_device *device; + uint32_t handle; + uint64_t size; + uint32_t flags; + uint64_t offset; + void *map; + union nouveau_bo_config config; +}; + +int nouveau_bo_new(struct nouveau_device *, uint32_t flags, uint32_t align, + uint64_t size, union nouveau_bo_config *, + struct nouveau_bo **); +int nouveau_bo_wrap(struct nouveau_device *, uint32_t handle, + struct nouveau_bo **); +int nouveau_bo_name_ref(struct nouveau_device *dev, uint32_t name, + struct nouveau_bo **); +int nouveau_bo_name_get(struct nouveau_bo *, uint32_t *name); +void nouveau_bo_ref(struct nouveau_bo *, struct nouveau_bo **); +int nouveau_bo_map(struct nouveau_bo *, uint32_t access, + struct nouveau_client *); +int nouveau_bo_wait(struct nouveau_bo *, uint32_t access, + struct nouveau_client *); + +struct nouveau_bufref { + struct nouveau_list thead; + struct nouveau_bo *bo; + uint32_t packet; + uint32_t flags; + uint32_t data; + uint32_t vor; + uint32_t tor; + uint32_t priv_data; + void *priv; +}; + +struct nouveau_bufctx { + struct nouveau_client *client; + struct nouveau_list head; + struct nouveau_list pending; + struct nouveau_list current; + int relocs; +}; + +int nouveau_bufctx_new(struct nouveau_client *, int bins, + struct nouveau_bufctx **); +void nouveau_bufctx_del(struct nouveau_bufctx **); +struct nouveau_bufref * +nouveau_bufctx_refn(struct nouveau_bufctx *, int bin, + struct nouveau_bo *, uint32_t flags); +struct nouveau_bufref * +nouveau_bufctx_mthd(struct nouveau_bufctx *, int bin, uint32_t packet, + struct nouveau_bo *, uint64_t data, uint32_t flags, + uint32_t vor, uint32_t tor); +void nouveau_bufctx_reset(struct nouveau_bufctx *, int bin); + +struct nouveau_pushbuf_krec; +struct nouveau_pushbuf { + struct nouveau_client *client; + struct nouveau_object *channel; + struct nouveau_bufctx *bufctx; + void (*kick_notify)(struct nouveau_pushbuf *); + void *user_priv; + uint32_t rsvd_kick; + uint32_t flags; + uint32_t *cur; + uint32_t *end; +}; + +struct nouveau_pushbuf_refn { + struct nouveau_bo *bo; + uint32_t flags; +}; + +int nouveau_pushbuf_new(struct nouveau_client *, struct nouveau_object *channel, + int nr, uint32_t size, bool immediate, + struct nouveau_pushbuf **); +void nouveau_pushbuf_del(struct nouveau_pushbuf **); +int nouveau_pushbuf_space(struct nouveau_pushbuf *, uint32_t dwords, + uint32_t relocs, uint32_t pushes); +void nouveau_pushbuf_data(struct nouveau_pushbuf *, struct nouveau_bo *, + uint64_t offset, uint64_t length); +int nouveau_pushbuf_refn(struct nouveau_pushbuf *, + struct nouveau_pushbuf_refn *, int nr); +/* Emits a reloc into the push buffer at the current position, you *must* + * have previously added the referenced buffer to a buffer context, and + * validated it against the current push buffer. + */ +void nouveau_pushbuf_reloc(struct nouveau_pushbuf *, struct nouveau_bo *, + uint32_t data, uint32_t flags, + uint32_t vor, uint32_t tor); +int nouveau_pushbuf_validate(struct nouveau_pushbuf *); +uint32_t nouveau_pushbuf_refd(struct nouveau_pushbuf *, struct nouveau_bo *); +int nouveau_pushbuf_kick(struct nouveau_pushbuf *, struct nouveau_object *channel); +struct nouveau_bufctx * +nouveau_pushbuf_bufctx(struct nouveau_pushbuf *, struct nouveau_bufctx *); + +#endif diff --git a/nouveau/private.h b/nouveau/private.h new file mode 100644 index 0000000..b409cc8 --- /dev/null +++ b/nouveau/private.h @@ -0,0 +1,122 @@ +#ifndef __NOUVEAU_LIBDRM_PRIVATE_H__ +#define __NOUVEAU_LIBDRM_PRIVATE_H__ + +#include +#include +#include "nouveau_drm.h" + +#include "nouveau.h" + +#ifdef DEBUG +uint32_t nouveau_debug; +#define dbg_on(lvl) (nouveau_debug & (1 << lvl)) +#define dbg(lvl, fmt, args...) do { \ + if (dbg_on((lvl))) \ + fprintf(stderr, "nouveau: "fmt, ##args); \ +} while(0) +#else +#define dbg_on(lvl) (0) +#define dbg(lvl, fmt, args...) +#endif +#define err(fmt, args...) fprintf(stderr, "nouveau: "fmt, ##args) + +struct nouveau_client_kref { + struct drm_nouveau_gem_pushbuf_bo *kref; + struct nouveau_pushbuf *push; +}; + +struct nouveau_client_priv { + struct nouveau_client base; + struct nouveau_client_kref *kref; + unsigned kref_nr; +}; + +static inline struct nouveau_client_priv * +nouveau_client(struct nouveau_client *client) +{ + return (struct nouveau_client_priv *)client; +} + +static inline struct drm_nouveau_gem_pushbuf_bo * +cli_kref_get(struct nouveau_client *client, struct nouveau_bo *bo) +{ + struct nouveau_client_priv *pcli = nouveau_client(client); + struct drm_nouveau_gem_pushbuf_bo *kref = NULL; + if (pcli->kref_nr > bo->handle) + kref = pcli->kref[bo->handle].kref; + return kref; +} + +static inline struct nouveau_pushbuf * +cli_push_get(struct nouveau_client *client, struct nouveau_bo *bo) +{ + struct nouveau_client_priv *pcli = nouveau_client(client); + struct nouveau_pushbuf *push = NULL; + if (pcli->kref_nr > bo->handle) + push = pcli->kref[bo->handle].push; + return push; +} + +static inline void +cli_kref_set(struct nouveau_client *client, struct nouveau_bo *bo, + struct drm_nouveau_gem_pushbuf_bo *kref, + struct nouveau_pushbuf *push) +{ + struct nouveau_client_priv *pcli = nouveau_client(client); + if (pcli->kref_nr <= bo->handle) { + pcli->kref = realloc(pcli->kref, + sizeof(*pcli->kref) * bo->handle * 2); + while (pcli->kref_nr < bo->handle * 2) { + pcli->kref[pcli->kref_nr].kref = NULL; + pcli->kref[pcli->kref_nr].push = NULL; + pcli->kref_nr++; + } + } + pcli->kref[bo->handle].kref = kref; + pcli->kref[bo->handle].push = push; +} + +struct nouveau_bo_priv { + struct nouveau_bo base; + struct nouveau_list head; + atomic_t refcnt; + uint64_t map_handle; + uint32_t name; + uint32_t access; +}; + +static inline struct nouveau_bo_priv * +nouveau_bo(struct nouveau_bo *bo) +{ + return (struct nouveau_bo_priv *)bo; +} + +struct nouveau_device_priv { + struct nouveau_device base; + int close; + atomic_t lock; + struct nouveau_list bo_list; + uint32_t *client; + int nr_client; + bool have_bo_usage; +}; + +static inline struct nouveau_device_priv * +nouveau_device(struct nouveau_device *dev) +{ + return (struct nouveau_device_priv *)dev; +} + +int +nouveau_device_open_existing(struct nouveau_device **, int, int, drm_context_t); + +/* abi16.c */ +int abi16_chan_nv04(struct nouveau_object *); +int abi16_chan_nvc0(struct nouveau_object *); +int abi16_engobj(struct nouveau_object *); +int abi16_ntfy(struct nouveau_object *); +void abi16_bo_info(struct nouveau_bo *, struct drm_nouveau_gem_info *); +int abi16_bo_init(struct nouveau_bo *, uint32_t alignment, + union nouveau_bo_config *); + +#endif diff --git a/nouveau/pushbuf.c b/nouveau/pushbuf.c new file mode 100644 index 0000000..7b9dbaa --- /dev/null +++ b/nouveau/pushbuf.c @@ -0,0 +1,771 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#ifdef HAVE_CONFIG_H +#include +#endif + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "libdrm_lists.h" +#include "nouveau_drm.h" + +#include "nouveau.h" +#include "private.h" + +struct nouveau_pushbuf_krec { + struct nouveau_pushbuf_krec *next; + struct drm_nouveau_gem_pushbuf_bo buffer[NOUVEAU_GEM_MAX_BUFFERS]; + struct drm_nouveau_gem_pushbuf_reloc reloc[NOUVEAU_GEM_MAX_RELOCS]; + struct drm_nouveau_gem_pushbuf_push push[NOUVEAU_GEM_MAX_PUSH]; + int nr_buffer; + int nr_reloc; + int nr_push; + uint64_t vram_used; + uint64_t gart_used; +}; + +struct nouveau_pushbuf_priv { + struct nouveau_pushbuf base; + struct nouveau_pushbuf_krec *list; + struct nouveau_pushbuf_krec *krec; + struct nouveau_list bctx_list; + struct nouveau_bo *bo; + uint32_t type; + uint32_t suffix0; + uint32_t suffix1; + uint32_t *ptr; + uint32_t *bgn; + int bo_next; + int bo_nr; + struct nouveau_bo *bos[]; +}; + +static inline struct nouveau_pushbuf_priv * +nouveau_pushbuf(struct nouveau_pushbuf *push) +{ + return (struct nouveau_pushbuf_priv *)push; +} + +static int pushbuf_validate(struct nouveau_pushbuf *, bool); +static int pushbuf_flush(struct nouveau_pushbuf *); + +static bool +pushbuf_kref_fits(struct nouveau_pushbuf *push, struct nouveau_bo *bo, + uint32_t *domains) +{ + struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(push); + struct nouveau_pushbuf_krec *krec = nvpb->krec; + struct nouveau_device *dev = push->client->device; + struct nouveau_bo *kbo; + struct drm_nouveau_gem_pushbuf_bo *kref; + int i; + + /* VRAM is the only valid domain. GART and VRAM|GART buffers + * are all accounted to GART, so if this doesn't fit in VRAM + * straight up, a flush is needed. + */ + if (*domains == NOUVEAU_GEM_DOMAIN_VRAM) { + if (krec->vram_used + bo->size > dev->vram_limit) + return false; + krec->vram_used += bo->size; + return true; + } + + /* GART or VRAM|GART buffer. Account both of these buffer types + * to GART only for the moment, which simplifies things. If the + * buffer can fit already, we're done here. + */ + if (krec->gart_used + bo->size <= dev->gart_limit) { + krec->gart_used += bo->size; + return true; + } + + /* Ran out of GART space, if it's a VRAM|GART buffer and it'll + * fit into available VRAM, turn it into a VRAM buffer + */ + if ((*domains & NOUVEAU_GEM_DOMAIN_VRAM) && + krec->vram_used + bo->size <= dev->vram_limit) { + *domains &= NOUVEAU_GEM_DOMAIN_VRAM; + krec->vram_used += bo->size; + return true; + } + + /* Still couldn't fit the buffer in anywhere, so as a last resort; + * scan the buffer list for VRAM|GART buffers and turn them into + * VRAM buffers until we have enough space in GART for this one + */ + kref = krec->buffer; + for (i = 0; i < krec->nr_buffer; i++, kref++) { + if (!(kref->valid_domains & NOUVEAU_GEM_DOMAIN_GART)) + continue; + + kbo = (void *)(unsigned long)kref->user_priv; + if (!(kref->valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) || + krec->vram_used + kbo->size > dev->vram_limit) + continue; + + kref->valid_domains &= NOUVEAU_GEM_DOMAIN_VRAM; + krec->gart_used -= kbo->size; + krec->vram_used += kbo->size; + if (krec->gart_used + bo->size <= dev->gart_limit) { + krec->gart_used += bo->size; + return true; + } + } + + /* Couldn't resolve a placement, need to force a flush */ + return false; +} + +static struct drm_nouveau_gem_pushbuf_bo * +pushbuf_kref(struct nouveau_pushbuf *push, struct nouveau_bo *bo, + uint32_t flags) +{ + struct nouveau_device *dev = push->client->device; + struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(push); + struct nouveau_pushbuf_krec *krec = nvpb->krec; + struct nouveau_pushbuf *fpush; + struct drm_nouveau_gem_pushbuf_bo *kref; + uint32_t domains, domains_wr, domains_rd; + + domains = 0; + if (flags & NOUVEAU_BO_VRAM) + domains |= NOUVEAU_GEM_DOMAIN_VRAM; + if (flags & NOUVEAU_BO_GART) + domains |= NOUVEAU_GEM_DOMAIN_GART; + domains_wr = domains * !!(flags & NOUVEAU_BO_WR); + domains_rd = domains * !!(flags & NOUVEAU_BO_RD); + + /* if buffer is referenced on another pushbuf that is owned by the + * same client, we need to flush the other pushbuf first to ensure + * the correct ordering of commands + */ + fpush = cli_push_get(push->client, bo); + if (fpush && fpush != push) + pushbuf_flush(fpush); + + kref = cli_kref_get(push->client, bo); + if (kref) { + /* possible conflict in memory types - flush and retry */ + if (!(kref->valid_domains & domains)) + return NULL; + + /* VRAM|GART buffer turning into a VRAM buffer. Make sure + * it'll fit in VRAM and force a flush if not. + */ + if ((kref->valid_domains & NOUVEAU_GEM_DOMAIN_GART) && + ( domains == NOUVEAU_GEM_DOMAIN_VRAM)) { + if (krec->vram_used + bo->size > dev->vram_limit) + return NULL; + krec->vram_used += bo->size; + krec->gart_used -= bo->size; + } + + kref->valid_domains &= domains; + kref->write_domains |= domains_wr; + kref->read_domains |= domains_rd; + } else { + if (krec->nr_buffer == NOUVEAU_GEM_MAX_BUFFERS || + !pushbuf_kref_fits(push, bo, &domains)) + return NULL; + + kref = &krec->buffer[krec->nr_buffer++]; + kref->user_priv = (unsigned long)bo; + kref->handle = bo->handle; + kref->valid_domains = domains; + kref->write_domains = domains_wr; + kref->read_domains = domains_rd; + kref->presumed.valid = 1; + kref->presumed.offset = bo->offset; + if (bo->flags & NOUVEAU_BO_VRAM) + kref->presumed.domain = NOUVEAU_GEM_DOMAIN_VRAM; + else + kref->presumed.domain = NOUVEAU_GEM_DOMAIN_GART; + + cli_kref_set(push->client, bo, kref, push); + atomic_inc(&nouveau_bo(bo)->refcnt); + } + + return kref; +} + +static uint32_t +pushbuf_krel(struct nouveau_pushbuf *push, struct nouveau_bo *bo, + uint32_t data, uint32_t flags, uint32_t vor, uint32_t tor) +{ + struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(push); + struct nouveau_pushbuf_krec *krec = nvpb->krec; + struct drm_nouveau_gem_pushbuf_reloc *krel; + struct drm_nouveau_gem_pushbuf_bo *pkref; + struct drm_nouveau_gem_pushbuf_bo *bkref; + uint32_t reloc = data; + + pkref = cli_kref_get(push->client, nvpb->bo); + bkref = cli_kref_get(push->client, bo); + krel = &krec->reloc[krec->nr_reloc++]; + + krel->reloc_bo_index = pkref - krec->buffer; + krel->reloc_bo_offset = (push->cur - nvpb->ptr) * 4; + krel->bo_index = bkref - krec->buffer; + krel->flags = 0; + krel->data = data; + krel->vor = vor; + krel->tor = tor; + + if (flags & NOUVEAU_BO_LOW) { + reloc = (bkref->presumed.offset + data); + krel->flags |= NOUVEAU_GEM_RELOC_LOW; + } else + if (flags & NOUVEAU_BO_HIGH) { + reloc = (bkref->presumed.offset + data) >> 32; + krel->flags |= NOUVEAU_GEM_RELOC_HIGH; + } + if (flags & NOUVEAU_BO_OR) { + if (bkref->presumed.domain & NOUVEAU_GEM_DOMAIN_VRAM) + reloc |= vor; + else + reloc |= tor; + krel->flags |= NOUVEAU_GEM_RELOC_OR; + } + + return reloc; +} + +static void +pushbuf_dump(struct nouveau_pushbuf_krec *krec, int krec_id, int chid) +{ + struct drm_nouveau_gem_pushbuf_reloc *krel; + struct drm_nouveau_gem_pushbuf_push *kpsh; + struct drm_nouveau_gem_pushbuf_bo *kref; + struct nouveau_bo *bo; + uint32_t *bgn, *end; + int i; + + err("ch%d: krec %d pushes %d bufs %d relocs %d\n", chid, + krec_id, krec->nr_push, krec->nr_buffer, krec->nr_reloc); + + kref = krec->buffer; + for (i = 0; i < krec->nr_buffer; i++, kref++) { + err("ch%d: buf %08x %08x %08x %08x %08x\n", chid, i, + kref->handle, kref->valid_domains, + kref->read_domains, kref->write_domains); + } + + krel = krec->reloc; + for (i = 0; i < krec->nr_reloc; i++, krel++) { + err("ch%d: rel %08x %08x %08x %08x %08x %08x %08x\n", + chid, krel->reloc_bo_index, krel->reloc_bo_offset, + krel->bo_index, krel->flags, krel->data, + krel->vor, krel->tor); + } + + kpsh = krec->push; + for (i = 0; i < krec->nr_push; i++, kpsh++) { + kref = krec->buffer + kpsh->bo_index; + bo = (void *)(unsigned long)kref->user_priv; + bgn = (uint32_t *)((char *)bo->map + kpsh->offset); + end = bgn + (kpsh->length /4); + + err("ch%d: psh %08x %010llx %010llx\n", chid, kpsh->bo_index, + (unsigned long long)kpsh->offset, + (unsigned long long)(kpsh->offset + kpsh->length)); + while (bgn < end) + err("\t0x%08x\n", *bgn++); + } +} + +static int +pushbuf_submit(struct nouveau_pushbuf *push, struct nouveau_object *chan) +{ + struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(push); + struct nouveau_pushbuf_krec *krec = nvpb->list; + struct nouveau_device *dev = push->client->device; + struct drm_nouveau_gem_pushbuf_bo_presumed *info; + struct drm_nouveau_gem_pushbuf_bo *kref; + struct drm_nouveau_gem_pushbuf req; + struct nouveau_fifo *fifo = chan->data; + struct nouveau_bo *bo; + int krec_id = 0; + int ret = 0, i; + + if (chan->oclass != NOUVEAU_FIFO_CHANNEL_CLASS) + return -EINVAL; + + if (push->kick_notify) + push->kick_notify(push); + + nouveau_pushbuf_data(push, NULL, 0, 0); + + while (krec && krec->nr_push) { + req.channel = fifo->channel; + req.nr_buffers = krec->nr_buffer; + req.buffers = (uint64_t)(unsigned long)krec->buffer; + req.nr_relocs = krec->nr_reloc; + req.nr_push = krec->nr_push; + req.relocs = (uint64_t)(unsigned long)krec->reloc; + req.push = (uint64_t)(unsigned long)krec->push; + req.suffix0 = nvpb->suffix0; + req.suffix1 = nvpb->suffix1; + + if (dbg_on(0)) + pushbuf_dump(krec, krec_id++, fifo->channel); + +#ifndef SIMULATE + ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_GEM_PUSHBUF, + &req, sizeof(req)); + nvpb->suffix0 = req.suffix0; + nvpb->suffix1 = req.suffix1; + dev->vram_limit = (req.vram_available * 80) / 100; + dev->gart_limit = (req.gart_available * 80) / 100; +#else + if (dbg_on(31)) + ret = -EINVAL; +#endif + + if (ret) { + err("kernel rejected pushbuf: %s\n", strerror(-ret)); + pushbuf_dump(krec, krec_id++, fifo->channel); + break; + } + + kref = krec->buffer; + for (i = 0; i < krec->nr_buffer; i++, kref++) { + bo = (void *)(unsigned long)kref->user_priv; + + info = &kref->presumed; + if (!info->valid) { + bo->flags &= ~NOUVEAU_BO_APER; + if (info->domain == NOUVEAU_GEM_DOMAIN_VRAM) + bo->flags |= NOUVEAU_BO_VRAM; + else + bo->flags |= NOUVEAU_BO_GART; + bo->offset = info->offset; + } + + if (kref->write_domains) + nouveau_bo(bo)->access |= NOUVEAU_BO_WR; + if (kref->read_domains) + nouveau_bo(bo)->access |= NOUVEAU_BO_RD; + } + + krec = krec->next; + } + + return ret; +} + +static int +pushbuf_flush(struct nouveau_pushbuf *push) +{ + struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(push); + struct nouveau_pushbuf_krec *krec = nvpb->krec; + struct drm_nouveau_gem_pushbuf_bo *kref; + struct nouveau_bufctx *bctx, *btmp; + struct nouveau_bo *bo; + int ret = 0, i; + + if (push->channel) { + ret = pushbuf_submit(push, push->channel); + } else { + nouveau_pushbuf_data(push, NULL, 0, 0); + krec->next = malloc(sizeof(*krec)); + nvpb->krec = krec->next; + } + + kref = krec->buffer; + for (i = 0; i < krec->nr_buffer; i++, kref++) { + bo = (void *)(unsigned long)kref->user_priv; + cli_kref_set(push->client, bo, NULL, NULL); + if (push->channel) + nouveau_bo_ref(NULL, &bo); + } + + krec = nvpb->krec; + krec->vram_used = 0; + krec->gart_used = 0; + krec->nr_buffer = 0; + krec->nr_reloc = 0; + krec->nr_push = 0; + + DRMLISTFOREACHENTRYSAFE(bctx, btmp, &nvpb->bctx_list, head) { + DRMLISTJOIN(&bctx->current, &bctx->pending); + DRMINITLISTHEAD(&bctx->current); + DRMLISTDELINIT(&bctx->head); + } + + return ret; +} + +static void +pushbuf_refn_fail(struct nouveau_pushbuf *push, int sref, int srel) +{ + struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(push); + struct nouveau_pushbuf_krec *krec = nvpb->krec; + struct drm_nouveau_gem_pushbuf_bo *kref; + + kref = krec->buffer + sref; + while (krec->nr_buffer-- > sref) { + struct nouveau_bo *bo = (void *)(unsigned long)kref->user_priv; + cli_kref_set(push->client, bo, NULL, NULL); + nouveau_bo_ref(NULL, &bo); + kref++; + } + krec->nr_buffer = sref; + krec->nr_reloc = srel; +} + +static int +pushbuf_refn(struct nouveau_pushbuf *push, bool retry, + struct nouveau_pushbuf_refn *refs, int nr) +{ + struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(push); + struct nouveau_pushbuf_krec *krec = nvpb->krec; + struct drm_nouveau_gem_pushbuf_bo *kref; + int sref = krec->nr_buffer; + int ret = 0, i; + + for (i = 0; i < nr; i++) { + kref = pushbuf_kref(push, refs[i].bo, refs[i].flags); + if (!kref) { + ret = -ENOSPC; + break; + } + } + + if (ret) { + pushbuf_refn_fail(push, sref, krec->nr_reloc); + if (retry) { + pushbuf_flush(push); + nouveau_pushbuf_space(push, 0, 0, 0); + return pushbuf_refn(push, false, refs, nr); + } + } + + return ret; +} + +static int +pushbuf_validate(struct nouveau_pushbuf *push, bool retry) +{ + struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(push); + struct nouveau_pushbuf_krec *krec = nvpb->krec; + struct drm_nouveau_gem_pushbuf_bo *kref; + struct nouveau_bufctx *bctx = push->bufctx; + struct nouveau_bufref *bref; + int relocs = bctx ? bctx->relocs * 2: 0; + int sref, srel, ret; + + ret = nouveau_pushbuf_space(push, relocs, relocs, 0); + if (ret || bctx == NULL) + return ret; + + sref = krec->nr_buffer; + srel = krec->nr_reloc; + + DRMLISTDEL(&bctx->head); + DRMLISTADD(&bctx->head, &nvpb->bctx_list); + + DRMLISTFOREACHENTRY(bref, &bctx->pending, thead) { + kref = pushbuf_kref(push, bref->bo, bref->flags); + if (!kref) { + ret = -ENOSPC; + break; + } + + if (bref->packet) { + pushbuf_krel(push, bref->bo, bref->packet, 0, 0, 0); + *push->cur++ = 0; + pushbuf_krel(push, bref->bo, bref->data, bref->flags, + bref->vor, bref->tor); + *push->cur++ = 0; + } + } + + DRMLISTJOIN(&bctx->pending, &bctx->current); + DRMINITLISTHEAD(&bctx->pending); + + if (ret) { + pushbuf_refn_fail(push, sref, srel); + if (retry) { + pushbuf_flush(push); + return pushbuf_validate(push, false); + } + } + + return 0; +} + +int +nouveau_pushbuf_new(struct nouveau_client *client, struct nouveau_object *chan, + int nr, uint32_t size, bool immediate, + struct nouveau_pushbuf **ppush) +{ + struct nouveau_device *dev = client->device; + struct nouveau_fifo *fifo = chan->data; + struct nouveau_pushbuf_priv *nvpb; + struct nouveau_pushbuf *push; + struct drm_nouveau_gem_pushbuf req; + int ret; + + if (chan->oclass != NOUVEAU_FIFO_CHANNEL_CLASS) + return -EINVAL; + + /* nop pushbuf call, to get the current "return to main" sequence + * we need to append to the pushbuf on early chipsets + */ + req.channel = fifo->channel; + req.nr_push = 0; + ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_GEM_PUSHBUF, + &req, sizeof(req)); + if (ret) + return ret; + + nvpb = calloc(1, sizeof(*nvpb) + nr * sizeof(*nvpb->bos)); + if (!nvpb) + return -ENOMEM; + +#ifndef SIMULATE + nvpb->suffix0 = req.suffix0; + nvpb->suffix1 = req.suffix1; +#else + nvpb->suffix0 = 0xffffffff; + nvpb->suffix1 = 0xffffffff; +#endif + nvpb->krec = calloc(1, sizeof(*nvpb->krec)); + nvpb->list = nvpb->krec; + if (!nvpb->krec) { + free(nvpb); + return -ENOMEM; + } + + push = &nvpb->base; + push->client = client; + push->channel = immediate ? chan : NULL; + push->flags = NOUVEAU_BO_RD; + if (fifo->pushbuf & NOUVEAU_GEM_DOMAIN_VRAM) { + push->flags |= NOUVEAU_BO_VRAM; + nvpb->type = NOUVEAU_BO_VRAM; + } + if (fifo->pushbuf & NOUVEAU_GEM_DOMAIN_GART) { + push->flags |= NOUVEAU_BO_GART; + nvpb->type = NOUVEAU_BO_GART; + } + nvpb->type |= NOUVEAU_BO_MAP; + + for (nvpb->bo_nr = 0; nvpb->bo_nr < nr; nvpb->bo_nr++) { + ret = nouveau_bo_new(client->device, nvpb->type, 0, size, + NULL, &nvpb->bos[nvpb->bo_nr]); + if (ret) { + nouveau_pushbuf_del(&push); + return ret; + } + } + + DRMINITLISTHEAD(&nvpb->bctx_list); + *ppush = push; + return 0; +} + +void +nouveau_pushbuf_del(struct nouveau_pushbuf **ppush) +{ + struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(*ppush); + if (nvpb) { + struct drm_nouveau_gem_pushbuf_bo *kref; + struct nouveau_pushbuf_krec *krec; + while ((krec = nvpb->list)) { + kref = krec->buffer; + while (krec->nr_buffer--) { + unsigned long priv = kref++->user_priv; + struct nouveau_bo *bo = (void *)priv; + cli_kref_set(nvpb->base.client, bo, NULL, NULL); + nouveau_bo_ref(NULL, &bo); + } + nvpb->list = krec->next; + free(krec); + } + while (nvpb->bo_nr--) + nouveau_bo_ref(NULL, &nvpb->bos[nvpb->bo_nr]); + nouveau_bo_ref(NULL, &nvpb->bo); + free(nvpb); + } + *ppush = NULL; +} + +struct nouveau_bufctx * +nouveau_pushbuf_bufctx(struct nouveau_pushbuf *push, struct nouveau_bufctx *ctx) +{ + struct nouveau_bufctx *prev = push->bufctx; + push->bufctx = ctx; + return prev; +} + +int +nouveau_pushbuf_space(struct nouveau_pushbuf *push, + uint32_t dwords, uint32_t relocs, uint32_t pushes) +{ + struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(push); + struct nouveau_pushbuf_krec *krec = nvpb->krec; + struct nouveau_client *client = push->client; + struct nouveau_bo *bo = NULL; + bool flushed = false; + int ret = 0; + + /* switch to next buffer if insufficient space in the current one */ + if (push->cur + dwords >= push->end) { + if (nvpb->bo_next < nvpb->bo_nr) { + nouveau_bo_ref(nvpb->bos[nvpb->bo_next++], &bo); + if (nvpb->bo_next == nvpb->bo_nr && push->channel) + nvpb->bo_next = 0; + } else { + ret = nouveau_bo_new(client->device, nvpb->type, 0, + nvpb->bos[0]->size, NULL, &bo); + if (ret) + return ret; + } + } + + /* make sure there's always enough space to queue up the pending + * data in the pushbuf proper + */ + pushes++; + + /* need to flush if we've run out of space on an immediate pushbuf, + * if the new buffer won't fit, or if the kernel push/reloc limits + * have been hit + */ + if ((bo && ( push->channel || + !pushbuf_kref(push, bo, push->flags))) || + krec->nr_reloc + relocs >= NOUVEAU_GEM_MAX_RELOCS || + krec->nr_push + pushes >= NOUVEAU_GEM_MAX_PUSH) { + if (nvpb->bo && krec->nr_buffer) + pushbuf_flush(push); + flushed = true; + } + + /* if necessary, switch to new buffer */ + if (bo) { + ret = nouveau_bo_map(bo, NOUVEAU_BO_WR, push->client); + if (ret) + return ret; + + nouveau_pushbuf_data(push, NULL, 0, 0); + nouveau_bo_ref(bo, &nvpb->bo); + nouveau_bo_ref(NULL, &bo); + + nvpb->bgn = nvpb->bo->map; + nvpb->ptr = nvpb->bgn; + push->cur = nvpb->bgn; + push->end = push->cur + (nvpb->bo->size / 4); + push->end -= 2 + push->rsvd_kick; /* space for suffix */ + } + + pushbuf_kref(push, nvpb->bo, push->flags); + return flushed ? pushbuf_validate(push, false) : 0; +} + +void +nouveau_pushbuf_data(struct nouveau_pushbuf *push, struct nouveau_bo *bo, + uint64_t offset, uint64_t length) +{ + struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(push); + struct nouveau_pushbuf_krec *krec = nvpb->krec; + struct drm_nouveau_gem_pushbuf_push *kpsh; + struct drm_nouveau_gem_pushbuf_bo *kref; + + if (bo != nvpb->bo && nvpb->bgn != push->cur) { + if (nvpb->suffix0 || nvpb->suffix1) { + *push->cur++ = nvpb->suffix0; + *push->cur++ = nvpb->suffix1; + } + + nouveau_pushbuf_data(push, nvpb->bo, + (nvpb->bgn - nvpb->ptr) * 4, + (push->cur - nvpb->bgn) * 4); + nvpb->bgn = push->cur; + } + + if (bo) { + kref = cli_kref_get(push->client, bo); + kpsh = &krec->push[krec->nr_push++]; + kpsh->bo_index = kref - krec->buffer; + kpsh->offset = offset; + kpsh->length = length; + } +} + +int +nouveau_pushbuf_refn(struct nouveau_pushbuf *push, + struct nouveau_pushbuf_refn *refs, int nr) +{ + return pushbuf_refn(push, true, refs, nr); +} + +void +nouveau_pushbuf_reloc(struct nouveau_pushbuf *push, struct nouveau_bo *bo, + uint32_t data, uint32_t flags, uint32_t vor, uint32_t tor) +{ + *push->cur++ = pushbuf_krel(push, bo, data, flags, vor, tor); +} + +int +nouveau_pushbuf_validate(struct nouveau_pushbuf *push) +{ + return pushbuf_validate(push, true); +} + +uint32_t +nouveau_pushbuf_refd(struct nouveau_pushbuf *push, struct nouveau_bo *bo) +{ + struct drm_nouveau_gem_pushbuf_bo *kref; + uint32_t flags = 0; + + if (cli_push_get(push->client, bo) == push) { + kref = cli_kref_get(push->client, bo); + if (kref->read_domains) + flags |= NOUVEAU_BO_RD; + if (kref->write_domains) + flags |= NOUVEAU_BO_WR; + } + + return flags; +} + +int +nouveau_pushbuf_kick(struct nouveau_pushbuf *push, struct nouveau_object *chan) +{ + if (!push->channel) + return pushbuf_submit(push, chan); + pushbuf_flush(push); + return pushbuf_validate(push, false); +} diff --git a/omap/Makefile.am b/omap/Makefile.am new file mode 100644 index 0000000..c77520b --- /dev/null +++ b/omap/Makefile.am @@ -0,0 +1,22 @@ +AM_CFLAGS = \ + $(WARN_CFLAGS) \ + -I$(top_srcdir) \ + -I$(top_srcdir)/omap \ + $(PTHREADSTUBS_CFLAGS) \ + -I$(top_srcdir)/include/drm + +libdrm_omap_la_LTLIBRARIES = libdrm_omap.la +libdrm_omap_ladir = $(libdir) +libdrm_omap_la_LDFLAGS = -version-number 1:0:0 -no-undefined +libdrm_omap_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@ + +libdrm_omap_la_SOURCES = omap_drm.c + +libdrm_omapcommonincludedir = ${includedir}/omap +libdrm_omapcommoninclude_HEADERS = omap_drm.h + +libdrm_omapincludedir = ${includedir}/libdrm +libdrm_omapinclude_HEADERS = omap_drmif.h + +pkgconfigdir = @pkgconfigdir@ +pkgconfig_DATA = libdrm_omap.pc diff --git a/omap/libdrm_omap.pc.in b/omap/libdrm_omap.pc.in new file mode 100644 index 0000000..024533b --- /dev/null +++ b/omap/libdrm_omap.pc.in @@ -0,0 +1,11 @@ +prefix=@prefix@ +exec_prefix=@exec_prefix@ +libdir=@libdir@ +includedir=@includedir@ + +Name: libdrm_omap +Description: Userspace interface to omap kernel DRM services +Version: 0.6 +Libs: -L${libdir} -ldrm_omap +Cflags: -I${includedir} -I${includedir}/libdrm -I${includedir}/omap +Requires.private: libdrm diff --git a/omap/omap_drm.c b/omap/omap_drm.c new file mode 100644 index 0000000..336da11 --- /dev/null +++ b/omap/omap_drm.c @@ -0,0 +1,331 @@ +/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */ + +/* + * Copyright (C) 2011 Texas Instruments, Inc + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Rob Clark + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include +#include + +#include + +#include "omap_drm.h" +#include "omap_drmif.h" + +#define __round_mask(x, y) ((__typeof__(x))((y)-1)) +#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1) +#define PAGE_SIZE 4096 + +struct omap_device { + int fd; +}; + +/* a GEM buffer object allocated from the DRM device */ +struct omap_bo { + struct omap_device *dev; + void *map; /* userspace mmap'ing (if there is one) */ + uint32_t size; + uint32_t handle; + uint32_t name; /* flink global handle (DRI2 name) */ + uint64_t offset; /* offset to mmap() */ + int fd; /* dmabuf handle */ +}; + +struct omap_device * omap_device_new(int fd) +{ + struct omap_device *dev = calloc(sizeof(*dev), 1); + if (!dev) + return NULL; + dev->fd = fd; + return dev; +} + +void omap_device_del(struct omap_device *dev) +{ + free(dev); +} + +int omap_get_param(struct omap_device *dev, uint64_t param, uint64_t *value) +{ + struct drm_omap_param req = { + .param = param, + }; + int ret; + + ret = drmCommandWriteRead(dev->fd, DRM_OMAP_GET_PARAM, &req, sizeof(req)); + if (ret) { + return ret; + } + + *value = req.value; + + return 0; +} + +int omap_set_param(struct omap_device *dev, uint64_t param, uint64_t value) +{ + struct drm_omap_param req = { + .param = param, + .value = value, + }; + return drmCommandWrite(dev->fd, DRM_OMAP_SET_PARAM, &req, sizeof(req)); +} + +/* allocate a new buffer object */ +static struct omap_bo * omap_bo_new_impl(struct omap_device *dev, + union omap_gem_size size, uint32_t flags) +{ + struct omap_bo *bo = NULL; + struct drm_omap_gem_new req = { + .size = size, + .flags = flags, + }; + + if (size.bytes == 0) { + goto fail; + } + + bo = calloc(sizeof(*bo), 1); + if (!bo) { + goto fail; + } + + bo->dev = dev; + + if (flags & OMAP_BO_TILED) { + bo->size = round_up(size.tiled.width, PAGE_SIZE) * size.tiled.height; + } else { + bo->size = size.bytes; + } + + if (drmCommandWriteRead(dev->fd, DRM_OMAP_GEM_NEW, &req, sizeof(req))) { + goto fail; + } + + bo->handle = req.handle; + + return bo; + +fail: + free(bo); + return NULL; +} + + +/* allocate a new (un-tiled) buffer object */ +struct omap_bo * omap_bo_new(struct omap_device *dev, + uint32_t size, uint32_t flags) +{ + union omap_gem_size gsize = { + .bytes = size, + }; + if (flags & OMAP_BO_TILED) { + return NULL; + } + return omap_bo_new_impl(dev, gsize, flags); +} + +/* allocate a new buffer object */ +struct omap_bo * omap_bo_new_tiled(struct omap_device *dev, + uint32_t width, uint32_t height, uint32_t flags) +{ + union omap_gem_size gsize = { + .tiled = { + .width = width, + .height = height, + }, + }; + if (!(flags & OMAP_BO_TILED)) { + return NULL; + } + return omap_bo_new_impl(dev, gsize, flags); +} + +/* get buffer info */ +static int get_buffer_info(struct omap_bo *bo) +{ + struct drm_omap_gem_info req = { + .handle = bo->handle, + }; + int ret = drmCommandWriteRead(bo->dev->fd, DRM_OMAP_GEM_INFO, + &req, sizeof(req)); + if (ret) { + return ret; + } + + /* really all we need for now is mmap offset */ + bo->offset = req.offset; + bo->size = req.size; + + return 0; +} + +/* import a buffer object from DRI2 name */ +struct omap_bo * omap_bo_from_name(struct omap_device *dev, uint32_t name) +{ + struct omap_bo *bo; + struct drm_gem_open req = { + .name = name, + }; + + bo = calloc(sizeof(*bo), 1); + if (!bo) { + goto fail; + } + + if (drmIoctl(dev->fd, DRM_IOCTL_GEM_OPEN, &req)) { + goto fail; + } + + bo->dev = dev; + bo->name = name; + bo->handle = req.handle; + + return bo; + +fail: + free(bo); + return NULL; +} + +/* destroy a buffer object */ +void omap_bo_del(struct omap_bo *bo) +{ + if (!bo) { + return; + } + + if (bo->map) { + munmap(bo->map, bo->size); + } + + if (bo->handle) { + struct drm_gem_close req = { + .handle = bo->handle, + }; + + drmIoctl(bo->dev->fd, DRM_IOCTL_GEM_CLOSE, &req); + } + + free(bo); +} + +/* get the global flink/DRI2 buffer name */ +int omap_bo_get_name(struct omap_bo *bo, uint32_t *name) +{ + if (!bo->name) { + struct drm_gem_flink req = { + .handle = bo->handle, + }; + int ret; + + ret = drmIoctl(bo->dev->fd, DRM_IOCTL_GEM_FLINK, &req); + if (ret) { + return ret; + } + + bo->name = req.name; + } + + *name = bo->name; + + return 0; +} + +uint32_t omap_bo_handle(struct omap_bo *bo) +{ + return bo->handle; +} + +int omap_bo_dmabuf(struct omap_bo *bo) +{ + if (!bo->fd) { + struct drm_prime_handle req = { + .handle = bo->handle, + .flags = DRM_CLOEXEC, + }; + int ret; + + ret = drmIoctl(bo->dev->fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &req); + if (ret) { + return ret; + } + + bo->fd = req.fd; + } + return bo->fd; +} + +uint32_t omap_bo_size(struct omap_bo *bo) +{ + if (!bo->size) { + get_buffer_info(bo); + } + return bo->size; +} + +void * omap_bo_map(struct omap_bo *bo) +{ + if (!bo->map) { + if (!bo->offset) { + get_buffer_info(bo); + } + + bo->map = mmap(0, bo->size, PROT_READ | PROT_WRITE, + MAP_SHARED, bo->dev->fd, bo->offset); + if (bo->map == MAP_FAILED) { + bo->map = NULL; + } + } + return bo->map; +} + +int omap_bo_cpu_prep(struct omap_bo *bo, enum omap_gem_op op) +{ + struct drm_omap_gem_cpu_prep req = { + .handle = bo->handle, + .op = op, + }; + return drmCommandWrite(bo->dev->fd, + DRM_OMAP_GEM_CPU_PREP, &req, sizeof(req)); +} + +int omap_bo_cpu_fini(struct omap_bo *bo, enum omap_gem_op op) +{ + struct drm_omap_gem_cpu_fini req = { + .handle = bo->handle, + .op = op, + .nregions = 0, + }; + return drmCommandWrite(bo->dev->fd, + DRM_OMAP_GEM_CPU_FINI, &req, sizeof(req)); +} diff --git a/omap/omap_drm.h b/omap/omap_drm.h new file mode 100644 index 0000000..f677cd8 --- /dev/null +++ b/omap/omap_drm.h @@ -0,0 +1,134 @@ +/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */ + +/* + * Copyright (C) 2011 Texas Instruments, Inc + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Rob Clark + */ + +#ifndef __OMAP_DRM_H__ +#define __OMAP_DRM_H__ + +#include "drm.h" + +/* Please note that modifications to all structs defined here are + * subject to backwards-compatibility constraints. + */ + +#define OMAP_PARAM_CHIPSET_ID 1 /* ie. 0x3430, 0x4430, etc */ + +struct drm_omap_param { + uint64_t param; /* in */ + uint64_t value; /* in (set_param), out (get_param) */ +}; + +struct drm_omap_get_base { + char plugin_name[64]; /* in */ + uint32_t ioctl_base; /* out */ + uint32_t __pad; +}; + +#define OMAP_BO_SCANOUT 0x00000001 /* scanout capable (phys contiguous) */ +#define OMAP_BO_CACHE_MASK 0x00000006 /* cache type mask, see cache modes */ +#define OMAP_BO_TILED_MASK 0x00000f00 /* tiled mapping mask, see tiled modes */ + +/* cache modes */ +#define OMAP_BO_CACHED 0x00000000 /* default */ +#define OMAP_BO_WC 0x00000002 /* write-combine */ +#define OMAP_BO_UNCACHED 0x00000004 /* strongly-ordered (uncached) */ + +/* tiled modes */ +#define OMAP_BO_TILED_8 0x00000100 +#define OMAP_BO_TILED_16 0x00000200 +#define OMAP_BO_TILED_32 0x00000300 +#define OMAP_BO_TILED (OMAP_BO_TILED_8 | OMAP_BO_TILED_16 | OMAP_BO_TILED_32) + +union omap_gem_size { + uint32_t bytes; /* (for non-tiled formats) */ + struct { + uint16_t width; + uint16_t height; + } tiled; /* (for tiled formats) */ +}; + +struct drm_omap_gem_new { + union omap_gem_size size; /* in */ + uint32_t flags; /* in */ + uint32_t handle; /* out */ + uint32_t __pad; +}; + +/* mask of operations: */ +enum omap_gem_op { + OMAP_GEM_READ = 0x01, + OMAP_GEM_WRITE = 0x02, +}; + +struct drm_omap_gem_cpu_prep { + uint32_t handle; /* buffer handle (in) */ + uint32_t op; /* mask of omap_gem_op (in) */ +}; + +struct drm_omap_gem_cpu_fini { + uint32_t handle; /* buffer handle (in) */ + uint32_t op; /* mask of omap_gem_op (in) */ + /* TODO maybe here we pass down info about what regions are touched + * by sw so we can be clever about cache ops? For now a placeholder, + * set to zero and we just do full buffer flush.. + */ + uint32_t nregions; + uint32_t __pad; +}; + +struct drm_omap_gem_info { + uint32_t handle; /* buffer handle (in) */ + uint32_t pad; + uint64_t offset; /* mmap offset (out) */ + /* note: in case of tiled buffers, the user virtual size can be + * different from the physical size (ie. how many pages are needed + * to back the object) which is returned in DRM_IOCTL_GEM_OPEN.. + * This size here is the one that should be used if you want to + * mmap() the buffer: + */ + uint32_t size; /* virtual size for mmap'ing (out) */ + uint32_t __pad; +}; + +#define DRM_OMAP_GET_PARAM 0x00 +#define DRM_OMAP_SET_PARAM 0x01 +#define DRM_OMAP_GET_BASE 0x02 +#define DRM_OMAP_GEM_NEW 0x03 +#define DRM_OMAP_GEM_CPU_PREP 0x04 +#define DRM_OMAP_GEM_CPU_FINI 0x05 +#define DRM_OMAP_GEM_INFO 0x06 +#define DRM_OMAP_NUM_IOCTLS 0x07 + +#define DRM_IOCTL_OMAP_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GET_PARAM, struct drm_omap_param) +#define DRM_IOCTL_OMAP_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_SET_PARAM, struct drm_omap_param) +#define DRM_IOCTL_OMAP_GET_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GET_BASE, struct drm_omap_get_base) +#define DRM_IOCTL_OMAP_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_NEW, struct drm_omap_gem_new) +#define DRM_IOCTL_OMAP_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_PREP, struct drm_omap_gem_cpu_prep) +#define DRM_IOCTL_OMAP_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_FINI, struct drm_omap_gem_cpu_fini) +#define DRM_IOCTL_OMAP_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_INFO, struct drm_omap_gem_info) + +#endif /* __OMAP_DRM_H__ */ diff --git a/omap/omap_drmif.h b/omap/omap_drmif.h new file mode 100644 index 0000000..1e03eee --- /dev/null +++ b/omap/omap_drmif.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2011 Texas Instruments, Inc + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Rob Clark + */ + +#ifndef OMAP_DRMIF_H_ +#define OMAP_DRMIF_H_ + +#include +#include +#include + +struct omap_bo; +struct omap_device; + +/* device related functions: + */ + +struct omap_device * omap_device_new(int fd); +void omap_device_del(struct omap_device *dev); +int omap_get_param(struct omap_device *dev, uint64_t param, uint64_t *value); +int omap_set_param(struct omap_device *dev, uint64_t param, uint64_t value); + +/* buffer-object related functions: + */ + +struct omap_bo * omap_bo_new(struct omap_device *dev, + uint32_t size, uint32_t flags); +struct omap_bo * omap_bo_new_tiled(struct omap_device *dev, + uint32_t width, uint32_t height, uint32_t flags); +struct omap_bo * omap_bo_from_name(struct omap_device *dev, uint32_t name); +void omap_bo_del(struct omap_bo *bo); +int omap_bo_get_name(struct omap_bo *bo, uint32_t *name); +uint32_t omap_bo_handle(struct omap_bo *bo); +int omap_bo_dmabuf(struct omap_bo *bo); +uint32_t omap_bo_size(struct omap_bo *bo); +void * omap_bo_map(struct omap_bo *bo); +int omap_bo_cpu_prep(struct omap_bo *bo, enum omap_gem_op op); +int omap_bo_cpu_fini(struct omap_bo *bo, enum omap_gem_op op); + +#endif /* OMAP_DRMIF_H_ */ diff --git a/packaging/libdrm.spec b/packaging/libdrm.spec new file mode 100644 index 0000000..8ad2b0a --- /dev/null +++ b/packaging/libdrm.spec @@ -0,0 +1,93 @@ +#sbs-git:slp/pkgs/xorg/lib/libdrm libdrm 2.4.27 4df9ab272d6eac089f89ecd9302d39263541a794 +Name: libdrm +Version: 2.4.35 +Release: 11 +License: MIT +Summary: Userspace interface to kernel DRM services +Group: System/Libraries +Source0: %{name}-%{version}.tar.gz +BuildRequires: pkgconfig(xorg-macros) +BuildRequires: pkgconfig(pthread-stubs) + +%description +Description: %{summary} + +%package devel +Summary: Userspace interface to kernel DRM services +Group: Development/Libraries +Requires: libdrm2 +Requires: libdrm-slp1 +Requires: libkms1 + +%description devel +Userspace interface to kernel DRM services + +%package -n libdrm2 +Summary: Userspace interface to kernel DRM services +Group: Development/Libraries + +%description -n libdrm2 +Userspace interface to kernel DRM services + +%package slp1 +Summary: Userspace interface to slp-specific kernel DRM services +Group: Development/Libraries + +%description slp1 +Userspace interface to slp-specific kernel DRM services + +%package -n libkms1 +Summary: Userspace interface to kernel DRM buffer management +Group: Development/Libraries + +%description -n libkms1 +Userspace interface to kernel DRM buffer management + +%prep +%setup -q + + +%build +%reconfigure --prefix=%{_prefix} --mandir=%{_prefix}/share/man --infodir=%{_prefix}/share/info \ + --enable-static=yes --enable-udev --enable-libkms --enable-exynos-experimental-api \ + --disable-nouveau --disable-radeon --disable-intel \ + CFLAGS="${CFLAGS}" LDFLAGS="${LDFLAGS} -Wl,--hash-style=both -Wl,--as-needed" + +make %{?_smp_mflags} + +%install +%make_install + + +%post -p /sbin/ldconfig +%postun -p /sbin/ldconfig + +%post -n libdrm2 -p /sbin/ldconfig +%postun -n libdrm2 -p /sbin/ldconfig + +%post slp1 -p /sbin/ldconfig +%postun slp1 -p /sbin/ldconfig + +%post -n libkms1 -p /sbin/ldconfig +%postun -n libkms1 -p /sbin/ldconfig + + +%files devel +%dir %{_includedir}/libdrm +%{_includedir}/* +%{_includedir}/exynos/* +%{_libdir}/libdrm.so +%{_libdir}/libdrm_slp.so +%{_libdir}/libdrm_exynos.so +%{_libdir}/libkms.so +%{_libdir}/pkgconfig/* + +%files -n libdrm2 +%{_libdir}/libdrm.so.* +%{_libdir}/libdrm_exynos.so.* + +%files slp1 +%{_libdir}/libdrm_slp*.so.* + +%files -n libkms1 +%{_libdir}/libkms.so.* diff --git a/radeon/Makefile.am b/radeon/Makefile.am new file mode 100644 index 0000000..37be8cc --- /dev/null +++ b/radeon/Makefile.am @@ -0,0 +1,61 @@ +# Copyright © 2008 Jérôme Glisse +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. +# +# Authors: +# Jérôme Glisse + +AM_CFLAGS = \ + $(WARN_CFLAGS) \ + -I$(top_srcdir) \ + -I$(top_srcdir)/radeon \ + $(PTHREADSTUBS_CFLAGS) \ + -I$(top_srcdir)/include/drm + +libdrm_radeon_la_LTLIBRARIES = libdrm_radeon.la +libdrm_radeon_ladir = $(libdir) +libdrm_radeon_la_LDFLAGS = -version-number 1:0:0 -no-undefined +libdrm_radeon_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@ + +libdrm_radeon_la_SOURCES = \ + radeon_bo_gem.c \ + radeon_cs_gem.c \ + radeon_cs_space.c \ + radeon_bo.c \ + radeon_cs.c \ + radeon_surface.c \ + bof.c \ + bof.h + +libdrm_radeonincludedir = ${includedir}/libdrm +libdrm_radeoninclude_HEADERS = \ + radeon_bo.h \ + radeon_cs.h \ + radeon_surface.h \ + radeon_bo_gem.h \ + radeon_cs_gem.h \ + radeon_bo_int.h \ + radeon_cs_int.h \ + r600_pci_ids.h + +pkgconfigdir = @pkgconfigdir@ +pkgconfig_DATA = libdrm_radeon.pc + +EXTRA_DIST = libdrm_radeon.pc.in diff --git a/radeon/bof.c b/radeon/bof.c new file mode 100644 index 0000000..0598cc6 --- /dev/null +++ b/radeon/bof.c @@ -0,0 +1,477 @@ +/* + * Copyright 2010 Jerome Glisse + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include +#include +#include +#include "bof.h" + +/* + * helpers + */ +static int bof_entry_grow(bof_t *bof) +{ + bof_t **array; + + if (bof->array_size < bof->nentry) + return 0; + array = realloc(bof->array, (bof->nentry + 16) * sizeof(void*)); + if (array == NULL) + return -ENOMEM; + bof->array = array; + bof->nentry += 16; + return 0; +} + +/* + * object + */ +bof_t *bof_object(void) +{ + bof_t *object; + + object = calloc(1, sizeof(bof_t)); + if (object == NULL) + return NULL; + object->refcount = 1; + object->type = BOF_TYPE_OBJECT; + object->size = 12; + return object; +} + +bof_t *bof_object_get(bof_t *object, const char *keyname) +{ + unsigned i; + + for (i = 0; i < object->array_size; i += 2) { + if (!strcmp(object->array[i]->value, keyname)) { + return object->array[i + 1]; + } + } + return NULL; +} + +int bof_object_set(bof_t *object, const char *keyname, bof_t *value) +{ + bof_t *key; + int r; + + if (object->type != BOF_TYPE_OBJECT) + return -EINVAL; + r = bof_entry_grow(object); + if (r) + return r; + key = bof_string(keyname); + if (key == NULL) + return -ENOMEM; + object->array[object->array_size++] = key; + object->array[object->array_size++] = value; + object->size += value->size; + object->size += key->size; + bof_incref(value); + return 0; +} + +/* + * array + */ +bof_t *bof_array(void) +{ + bof_t *array = bof_object(); + + if (array == NULL) + return NULL; + array->type = BOF_TYPE_ARRAY; + array->size = 12; + return array; +} + +int bof_array_append(bof_t *array, bof_t *value) +{ + int r; + if (array->type != BOF_TYPE_ARRAY) + return -EINVAL; + r = bof_entry_grow(array); + if (r) + return r; + array->array[array->array_size++] = value; + array->size += value->size; + bof_incref(value); + return 0; +} + +bof_t *bof_array_get(bof_t *bof, unsigned i) +{ + if (!bof_is_array(bof) || i >= bof->array_size) + return NULL; + return bof->array[i]; +} + +unsigned bof_array_size(bof_t *bof) +{ + if (!bof_is_array(bof)) + return 0; + return bof->array_size; +} + +/* + * blob + */ +bof_t *bof_blob(unsigned size, void *value) +{ + bof_t *blob = bof_object(); + + if (blob == NULL) + return NULL; + blob->type = BOF_TYPE_BLOB; + blob->value = calloc(1, size); + if (blob->value == NULL) { + bof_decref(blob); + return NULL; + } + blob->size = size; + memcpy(blob->value, value, size); + blob->size += 12; + return blob; +} + +unsigned bof_blob_size(bof_t *bof) +{ + if (!bof_is_blob(bof)) + return 0; + return bof->size - 12; +} + +void *bof_blob_value(bof_t *bof) +{ + if (!bof_is_blob(bof)) + return NULL; + return bof->value; +} + +/* + * string + */ +bof_t *bof_string(const char *value) +{ + bof_t *string = bof_object(); + + if (string == NULL) + return NULL; + string->type = BOF_TYPE_STRING; + string->size = strlen(value) + 1; + string->value = calloc(1, string->size); + if (string->value == NULL) { + bof_decref(string); + return NULL; + } + strcpy(string->value, value); + string->size += 12; + return string; +} + +/* + * int32 + */ +bof_t *bof_int32(int32_t value) +{ + bof_t *int32 = bof_object(); + + if (int32 == NULL) + return NULL; + int32->type = BOF_TYPE_INT32; + int32->size = 4; + int32->value = calloc(1, int32->size); + if (int32->value == NULL) { + bof_decref(int32); + return NULL; + } + memcpy(int32->value, &value, 4); + int32->size += 12; + return int32; +} + +int32_t bof_int32_value(bof_t *bof) +{ + return *((uint32_t*)bof->value); +} + +/* + * common + */ +static void bof_indent(int level) +{ + int i; + + for (i = 0; i < level; i++) + fprintf(stderr, " "); +} + +static void bof_print_bof(bof_t *bof, int level, int entry) +{ + bof_indent(level); + if (bof == NULL) { + fprintf(stderr, "--NULL-- for entry %d\n", entry); + return; + } + switch (bof->type) { + case BOF_TYPE_STRING: + fprintf(stderr, "%p string [%s %d]\n", bof, (char*)bof->value, bof->size); + break; + case BOF_TYPE_INT32: + fprintf(stderr, "%p int32 [%d %d]\n", bof, *(int*)bof->value, bof->size); + break; + case BOF_TYPE_BLOB: + fprintf(stderr, "%p blob [%d]\n", bof, bof->size); + break; + case BOF_TYPE_NULL: + fprintf(stderr, "%p null [%d]\n", bof, bof->size); + break; + case BOF_TYPE_OBJECT: + fprintf(stderr, "%p object [%d %d]\n", bof, bof->array_size / 2, bof->size); + break; + case BOF_TYPE_ARRAY: + fprintf(stderr, "%p array [%d %d]\n", bof, bof->array_size, bof->size); + break; + default: + fprintf(stderr, "%p unknown [%d]\n", bof, bof->type); + return; + } +} + +static void bof_print_rec(bof_t *bof, int level, int entry) +{ + unsigned i; + + bof_print_bof(bof, level, entry); + for (i = 0; i < bof->array_size; i++) { + bof_print_rec(bof->array[i], level + 2, i); + } +} + +void bof_print(bof_t *bof) +{ + bof_print_rec(bof, 0, 0); +} + +static int bof_read(bof_t *root, FILE *file, long end, int level) +{ + bof_t *bof = NULL; + int r; + + if (ftell(file) >= end) { + return 0; + } + r = bof_entry_grow(root); + if (r) + return r; + bof = bof_object(); + if (bof == NULL) + return -ENOMEM; + bof->offset = ftell(file); + r = fread(&bof->type, 4, 1, file); + if (r != 1) + goto out_err; + r = fread(&bof->size, 4, 1, file); + if (r != 1) + goto out_err; + r = fread(&bof->array_size, 4, 1, file); + if (r != 1) + goto out_err; + switch (bof->type) { + case BOF_TYPE_STRING: + case BOF_TYPE_INT32: + case BOF_TYPE_BLOB: + bof->value = calloc(1, bof->size - 12); + if (bof->value == NULL) { + goto out_err; + } + r = fread(bof->value, bof->size - 12, 1, file); + if (r != 1) { + fprintf(stderr, "error reading %d\n", bof->size - 12); + goto out_err; + } + break; + case BOF_TYPE_NULL: + return 0; + case BOF_TYPE_OBJECT: + case BOF_TYPE_ARRAY: + r = bof_read(bof, file, bof->offset + bof->size, level + 2); + if (r) + goto out_err; + break; + default: + fprintf(stderr, "invalid type %d\n", bof->type); + goto out_err; + } + root->array[root->centry++] = bof; + return bof_read(root, file, end, level); +out_err: + bof_decref(bof); + return -EINVAL; +} + +bof_t *bof_load_file(const char *filename) +{ + bof_t *root = bof_object(); + int r; + + if (root == NULL) { + fprintf(stderr, "%s failed to create root object\n", __func__); + return NULL; + } + root->file = fopen(filename, "r"); + if (root->file == NULL) + goto out_err; + r = fseek(root->file, 0L, SEEK_SET); + if (r) { + fprintf(stderr, "%s failed to seek into file %s\n", __func__, filename); + goto out_err; + } + root->offset = ftell(root->file); + r = fread(&root->type, 4, 1, root->file); + if (r != 1) + goto out_err; + r = fread(&root->size, 4, 1, root->file); + if (r != 1) + goto out_err; + r = fread(&root->array_size, 4, 1, root->file); + if (r != 1) + goto out_err; + r = bof_read(root, root->file, root->offset + root->size, 2); + if (r) + goto out_err; + return root; +out_err: + bof_decref(root); + return NULL; +} + +void bof_incref(bof_t *bof) +{ + bof->refcount++; +} + +void bof_decref(bof_t *bof) +{ + unsigned i; + + if (bof == NULL) + return; + if (--bof->refcount > 0) + return; + for (i = 0; i < bof->array_size; i++) { + bof_decref(bof->array[i]); + bof->array[i] = NULL; + } + bof->array_size = 0; + if (bof->file) { + fclose(bof->file); + bof->file = NULL; + } + free(bof->array); + free(bof->value); + free(bof); +} + +static int bof_file_write(bof_t *bof, FILE *file) +{ + unsigned i; + int r; + + r = fwrite(&bof->type, 4, 1, file); + if (r != 1) + return -EINVAL; + r = fwrite(&bof->size, 4, 1, file); + if (r != 1) + return -EINVAL; + r = fwrite(&bof->array_size, 4, 1, file); + if (r != 1) + return -EINVAL; + switch (bof->type) { + case BOF_TYPE_NULL: + if (bof->size) + return -EINVAL; + break; + case BOF_TYPE_STRING: + case BOF_TYPE_INT32: + case BOF_TYPE_BLOB: + r = fwrite(bof->value, bof->size - 12, 1, file); + if (r != 1) + return -EINVAL; + break; + case BOF_TYPE_OBJECT: + case BOF_TYPE_ARRAY: + for (i = 0; i < bof->array_size; i++) { + r = bof_file_write(bof->array[i], file); + if (r) + return r; + } + break; + default: + return -EINVAL; + } + return 0; +} + +int bof_dump_file(bof_t *bof, const char *filename) +{ + unsigned i; + int r = 0; + + if (bof->file) { + fclose(bof->file); + bof->file = NULL; + } + bof->file = fopen(filename, "w"); + if (bof->file == NULL) { + fprintf(stderr, "%s failed to open file %s\n", __func__, filename); + r = -EINVAL; + goto out_err; + } + r = fseek(bof->file, 0L, SEEK_SET); + if (r) { + fprintf(stderr, "%s failed to seek into file %s\n", __func__, filename); + goto out_err; + } + r = fwrite(&bof->type, 4, 1, bof->file); + if (r != 1) + goto out_err; + r = fwrite(&bof->size, 4, 1, bof->file); + if (r != 1) + goto out_err; + r = fwrite(&bof->array_size, 4, 1, bof->file); + if (r != 1) + goto out_err; + for (i = 0; i < bof->array_size; i++) { + r = bof_file_write(bof->array[i], bof->file); + if (r) + return r; + } +out_err: + fclose(bof->file); + bof->file = NULL; + return r; +} diff --git a/radeon/bof.h b/radeon/bof.h new file mode 100644 index 0000000..014affb --- /dev/null +++ b/radeon/bof.h @@ -0,0 +1,90 @@ +/* + * Copyright 2010 Jerome Glisse + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef BOF_H +#define BOF_H + +#include +#include + +#define BOF_TYPE_STRING 0 +#define BOF_TYPE_NULL 1 +#define BOF_TYPE_BLOB 2 +#define BOF_TYPE_OBJECT 3 +#define BOF_TYPE_ARRAY 4 +#define BOF_TYPE_INT32 5 + +struct bof; + +typedef struct bof { + struct bof **array; + unsigned centry; + unsigned nentry; + unsigned refcount; + FILE *file; + uint32_t type; + uint32_t size; + uint32_t array_size; + void *value; + long offset; +} bof_t; + +extern int bof_file_flush(bof_t *root); +extern bof_t *bof_file_new(const char *filename); +extern int bof_object_dump(bof_t *object, const char *filename); + +/* object */ +extern bof_t *bof_object(void); +extern bof_t *bof_object_get(bof_t *object, const char *keyname); +extern int bof_object_set(bof_t *object, const char *keyname, bof_t *value); +/* array */ +extern bof_t *bof_array(void); +extern int bof_array_append(bof_t *array, bof_t *value); +extern bof_t *bof_array_get(bof_t *bof, unsigned i); +extern unsigned bof_array_size(bof_t *bof); +/* blob */ +extern bof_t *bof_blob(unsigned size, void *value); +extern unsigned bof_blob_size(bof_t *bof); +extern void *bof_blob_value(bof_t *bof); +/* string */ +extern bof_t *bof_string(const char *value); +/* int32 */ +extern bof_t *bof_int32(int32_t value); +extern int32_t bof_int32_value(bof_t *bof); +/* common functions */ +extern void bof_decref(bof_t *bof); +extern void bof_incref(bof_t *bof); +extern bof_t *bof_load_file(const char *filename); +extern int bof_dump_file(bof_t *bof, const char *filename); +extern void bof_print(bof_t *bof); + +static inline int bof_is_object(bof_t *bof){return (bof->type == BOF_TYPE_OBJECT);} +static inline int bof_is_blob(bof_t *bof){return (bof->type == BOF_TYPE_BLOB);} +static inline int bof_is_null(bof_t *bof){return (bof->type == BOF_TYPE_NULL);} +static inline int bof_is_int32(bof_t *bof){return (bof->type == BOF_TYPE_INT32);} +static inline int bof_is_array(bof_t *bof){return (bof->type == BOF_TYPE_ARRAY);} +static inline int bof_is_string(bof_t *bof){return (bof->type == BOF_TYPE_STRING);} + +#endif diff --git a/radeon/libdrm_radeon.pc.in b/radeon/libdrm_radeon.pc.in new file mode 100644 index 0000000..68ef0ab --- /dev/null +++ b/radeon/libdrm_radeon.pc.in @@ -0,0 +1,10 @@ +prefix=@prefix@ +exec_prefix=@exec_prefix@ +libdir=@libdir@ +includedir=@includedir@ + +Name: libdrm_radeon +Description: Userspace interface to kernel DRM services for radeon +Version: @PACKAGE_VERSION@ +Libs: -L${libdir} -ldrm_radeon +Cflags: -I${includedir} -I${includedir}/libdrm diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h new file mode 100644 index 0000000..989ec00 --- /dev/null +++ b/radeon/r600_pci_ids.h @@ -0,0 +1,353 @@ +CHIPSET(0x9400, R600_9400, R600) +CHIPSET(0x9401, R600_9401, R600) +CHIPSET(0x9402, R600_9402, R600) +CHIPSET(0x9403, R600_9403, R600) +CHIPSET(0x9405, R600_9405, R600) +CHIPSET(0x940A, R600_940A, R600) +CHIPSET(0x940B, R600_940B, R600) +CHIPSET(0x940F, R600_940F, R600) + +CHIPSET(0x94C0, RV610_94C0, RV610) +CHIPSET(0x94C1, RV610_94C1, RV610) +CHIPSET(0x94C3, RV610_94C3, RV610) +CHIPSET(0x94C4, RV610_94C4, RV610) +CHIPSET(0x94C5, RV610_94C5, RV610) +CHIPSET(0x94C6, RV610_94C6, RV610) +CHIPSET(0x94C7, RV610_94C7, RV610) +CHIPSET(0x94C8, RV610_94C8, RV610) +CHIPSET(0x94C9, RV610_94C9, RV610) +CHIPSET(0x94CB, RV610_94CB, RV610) +CHIPSET(0x94CC, RV610_94CC, RV610) +CHIPSET(0x94CD, RV610_94CD, RV610) + +CHIPSET(0x9580, RV630_9580, RV630) +CHIPSET(0x9581, RV630_9581, RV630) +CHIPSET(0x9583, RV630_9583, RV630) +CHIPSET(0x9586, RV630_9586, RV630) +CHIPSET(0x9587, RV630_9587, RV630) +CHIPSET(0x9588, RV630_9588, RV630) +CHIPSET(0x9589, RV630_9589, RV630) +CHIPSET(0x958A, RV630_958A, RV630) +CHIPSET(0x958B, RV630_958B, RV630) +CHIPSET(0x958C, RV630_958C, RV630) +CHIPSET(0x958D, RV630_958D, RV630) +CHIPSET(0x958E, RV630_958E, RV630) +CHIPSET(0x958F, RV630_958F, RV630) + +CHIPSET(0x9500, RV670_9500, RV670) +CHIPSET(0x9501, RV670_9501, RV670) +CHIPSET(0x9504, RV670_9504, RV670) +CHIPSET(0x9505, RV670_9505, RV670) +CHIPSET(0x9506, RV670_9506, RV670) +CHIPSET(0x9507, RV670_9507, RV670) +CHIPSET(0x9508, RV670_9508, RV670) +CHIPSET(0x9509, RV670_9509, RV670) +CHIPSET(0x950F, RV670_950F, RV670) +CHIPSET(0x9511, RV670_9511, RV670) +CHIPSET(0x9515, RV670_9515, RV670) +CHIPSET(0x9517, RV670_9517, RV670) +CHIPSET(0x9519, RV670_9519, RV670) + +CHIPSET(0x95C0, RV620_95C0, RV620) +CHIPSET(0x95C2, RV620_95C2, RV620) +CHIPSET(0x95C4, RV620_95C4, RV620) +CHIPSET(0x95C5, RV620_95C5, RV620) +CHIPSET(0x95C6, RV620_95C6, RV620) +CHIPSET(0x95C7, RV620_95C7, RV620) +CHIPSET(0x95C9, RV620_95C9, RV620) +CHIPSET(0x95CC, RV620_95CC, RV620) +CHIPSET(0x95CD, RV620_95CD, RV620) +CHIPSET(0x95CE, RV620_95CE, RV620) +CHIPSET(0x95CF, RV620_95CF, RV620) + +CHIPSET(0x9590, RV635_9590, RV635) +CHIPSET(0x9591, RV635_9591, RV635) +CHIPSET(0x9593, RV635_9593, RV635) +CHIPSET(0x9595, RV635_9595, RV635) +CHIPSET(0x9596, RV635_9596, RV635) +CHIPSET(0x9597, RV635_9597, RV635) +CHIPSET(0x9598, RV635_9598, RV635) +CHIPSET(0x9599, RV635_9599, RV635) +CHIPSET(0x959B, RV635_959B, RV635) + +CHIPSET(0x9610, RS780_9610, RS780) +CHIPSET(0x9611, RS780_9611, RS780) +CHIPSET(0x9612, RS780_9612, RS780) +CHIPSET(0x9613, RS780_9613, RS780) +CHIPSET(0x9614, RS780_9614, RS780) +CHIPSET(0x9615, RS780_9615, RS780) +CHIPSET(0x9616, RS780_9616, RS780) + +CHIPSET(0x9710, RS880_9710, RS880) +CHIPSET(0x9711, RS880_9711, RS880) +CHIPSET(0x9712, RS880_9712, RS880) +CHIPSET(0x9713, RS880_9713, RS880) +CHIPSET(0x9714, RS880_9714, RS880) +CHIPSET(0x9715, RS880_9715, RS880) + +CHIPSET(0x9440, RV770_9440, RV770) +CHIPSET(0x9441, RV770_9441, RV770) +CHIPSET(0x9442, RV770_9442, RV770) +CHIPSET(0x9443, RV770_9443, RV770) +CHIPSET(0x9444, RV770_9444, RV770) +CHIPSET(0x9446, RV770_9446, RV770) +CHIPSET(0x944A, RV770_944A, RV770) +CHIPSET(0x944B, RV770_944B, RV770) +CHIPSET(0x944C, RV770_944C, RV770) +CHIPSET(0x944E, RV770_944E, RV770) +CHIPSET(0x9450, RV770_9450, RV770) +CHIPSET(0x9452, RV770_9452, RV770) +CHIPSET(0x9456, RV770_9456, RV770) +CHIPSET(0x945A, RV770_945A, RV770) +CHIPSET(0x945B, RV770_945B, RV770) +CHIPSET(0x945E, RV770_945E, RV770) +CHIPSET(0x9460, RV790_9460, RV770) +CHIPSET(0x9462, RV790_9462, RV770) +CHIPSET(0x946A, RV770_946A, RV770) +CHIPSET(0x946B, RV770_946B, RV770) +CHIPSET(0x947A, RV770_947A, RV770) +CHIPSET(0x947B, RV770_947B, RV770) + +CHIPSET(0x9480, RV730_9480, RV730) +CHIPSET(0x9487, RV730_9487, RV730) +CHIPSET(0x9488, RV730_9488, RV730) +CHIPSET(0x9489, RV730_9489, RV730) +CHIPSET(0x948A, RV730_948A, RV730) +CHIPSET(0x948F, RV730_948F, RV730) +CHIPSET(0x9490, RV730_9490, RV730) +CHIPSET(0x9491, RV730_9491, RV730) +CHIPSET(0x9495, RV730_9495, RV730) +CHIPSET(0x9498, RV730_9498, RV730) +CHIPSET(0x949C, RV730_949C, RV730) +CHIPSET(0x949E, RV730_949E, RV730) +CHIPSET(0x949F, RV730_949F, RV730) + +CHIPSET(0x9540, RV710_9540, RV710) +CHIPSET(0x9541, RV710_9541, RV710) +CHIPSET(0x9542, RV710_9542, RV710) +CHIPSET(0x954E, RV710_954E, RV710) +CHIPSET(0x954F, RV710_954F, RV710) +CHIPSET(0x9552, RV710_9552, RV710) +CHIPSET(0x9553, RV710_9553, RV710) +CHIPSET(0x9555, RV710_9555, RV710) +CHIPSET(0x9557, RV710_9557, RV710) +CHIPSET(0x955F, RV710_955F, RV710) + +CHIPSET(0x94A0, RV740_94A0, RV740) +CHIPSET(0x94A1, RV740_94A1, RV740) +CHIPSET(0x94A3, RV740_94A3, RV740) +CHIPSET(0x94B1, RV740_94B1, RV740) +CHIPSET(0x94B3, RV740_94B3, RV740) +CHIPSET(0x94B4, RV740_94B4, RV740) +CHIPSET(0x94B5, RV740_94B5, RV740) +CHIPSET(0x94B9, RV740_94B9, RV740) + +CHIPSET(0x68E0, CEDAR_68E0, CEDAR) +CHIPSET(0x68E1, CEDAR_68E1, CEDAR) +CHIPSET(0x68E4, CEDAR_68E4, CEDAR) +CHIPSET(0x68E5, CEDAR_68E5, CEDAR) +CHIPSET(0x68E8, CEDAR_68E8, CEDAR) +CHIPSET(0x68E9, CEDAR_68E9, CEDAR) +CHIPSET(0x68F1, CEDAR_68F1, CEDAR) +CHIPSET(0x68F2, CEDAR_68F2, CEDAR) +CHIPSET(0x68F8, CEDAR_68F8, CEDAR) +CHIPSET(0x68F9, CEDAR_68F9, CEDAR) +CHIPSET(0x68FA, CEDAR_68FA, CEDAR) +CHIPSET(0x68FE, CEDAR_68FE, CEDAR) + +CHIPSET(0x68C0, REDWOOD_68C0, REDWOOD) +CHIPSET(0x68C1, REDWOOD_68C1, REDWOOD) +CHIPSET(0x68C8, REDWOOD_68C8, REDWOOD) +CHIPSET(0x68C9, REDWOOD_68C9, REDWOOD) +CHIPSET(0x68D8, REDWOOD_68D8, REDWOOD) +CHIPSET(0x68D9, REDWOOD_68D9, REDWOOD) +CHIPSET(0x68DA, REDWOOD_68DA, REDWOOD) +CHIPSET(0x68DE, REDWOOD_68DE, REDWOOD) + +CHIPSET(0x68A0, JUNIPER_68A0, JUNIPER) +CHIPSET(0x68A1, JUNIPER_68A1, JUNIPER) +CHIPSET(0x68A8, JUNIPER_68A8, JUNIPER) +CHIPSET(0x68A9, JUNIPER_68A9, JUNIPER) +CHIPSET(0x68B0, JUNIPER_68B0, JUNIPER) +CHIPSET(0x68B8, JUNIPER_68B8, JUNIPER) +CHIPSET(0x68B9, JUNIPER_68B9, JUNIPER) +CHIPSET(0x68BA, JUNIPER_68BA, JUNIPER) +CHIPSET(0x68BE, JUNIPER_68BE, JUNIPER) +CHIPSET(0x68BF, JUNIPER_68BF, JUNIPER) + +CHIPSET(0x6880, CYPRESS_6880, CYPRESS) +CHIPSET(0x6888, CYPRESS_6888, CYPRESS) +CHIPSET(0x6889, CYPRESS_6889, CYPRESS) +CHIPSET(0x688A, CYPRESS_688A, CYPRESS) +CHIPSET(0x6898, CYPRESS_6898, CYPRESS) +CHIPSET(0x6899, CYPRESS_6899, CYPRESS) +CHIPSET(0x689B, CYPRESS_689B, CYPRESS) +CHIPSET(0x689E, CYPRESS_689E, CYPRESS) + +CHIPSET(0x689C, HEMLOCK_689C, HEMLOCK) +CHIPSET(0x689D, HEMLOCK_689D, HEMLOCK) + +CHIPSET(0x9802, PALM_9802, PALM) +CHIPSET(0x9803, PALM_9803, PALM) +CHIPSET(0x9804, PALM_9804, PALM) +CHIPSET(0x9805, PALM_9805, PALM) +CHIPSET(0x9806, PALM_9806, PALM) +CHIPSET(0x9807, PALM_9807, PALM) +CHIPSET(0x9808, PALM_9808, PALM) +CHIPSET(0x9809, PALM_9809, PALM) +CHIPSET(0x980A, PALM_980A, PALM) + +CHIPSET(0x9640, SUMO_9640, SUMO) +CHIPSET(0x9641, SUMO_9641, SUMO) +CHIPSET(0x9642, SUMO2_9642, SUMO2) +CHIPSET(0x9643, SUMO2_9643, SUMO2) +CHIPSET(0x9644, SUMO2_9644, SUMO2) +CHIPSET(0x9645, SUMO2_9645, SUMO2) +CHIPSET(0x9647, SUMO_9647, SUMO) +CHIPSET(0x9648, SUMO_9648, SUMO) +CHIPSET(0x9649, SUMO_9649, SUMO) +CHIPSET(0x964a, SUMO_964A, SUMO) +CHIPSET(0x964b, SUMO_964B, SUMO) +CHIPSET(0x964c, SUMO_964C, SUMO) +CHIPSET(0x964e, SUMO_964E, SUMO) +CHIPSET(0x964f, SUMO_964F, SUMO) + +CHIPSET(0x6700, CAYMAN_6700, CAYMAN) +CHIPSET(0x6701, CAYMAN_6701, CAYMAN) +CHIPSET(0x6702, CAYMAN_6702, CAYMAN) +CHIPSET(0x6703, CAYMAN_6703, CAYMAN) +CHIPSET(0x6704, CAYMAN_6704, CAYMAN) +CHIPSET(0x6705, CAYMAN_6705, CAYMAN) +CHIPSET(0x6706, CAYMAN_6706, CAYMAN) +CHIPSET(0x6707, CAYMAN_6707, CAYMAN) +CHIPSET(0x6708, CAYMAN_6708, CAYMAN) +CHIPSET(0x6709, CAYMAN_6709, CAYMAN) +CHIPSET(0x6718, CAYMAN_6718, CAYMAN) +CHIPSET(0x6719, CAYMAN_6719, CAYMAN) +CHIPSET(0x671C, CAYMAN_671C, CAYMAN) +CHIPSET(0x671D, CAYMAN_671D, CAYMAN) +CHIPSET(0x671F, CAYMAN_671F, CAYMAN) + +CHIPSET(0x6720, BARTS_6720, BARTS) +CHIPSET(0x6721, BARTS_6721, BARTS) +CHIPSET(0x6722, BARTS_6722, BARTS) +CHIPSET(0x6723, BARTS_6723, BARTS) +CHIPSET(0x6724, BARTS_6724, BARTS) +CHIPSET(0x6725, BARTS_6725, BARTS) +CHIPSET(0x6726, BARTS_6726, BARTS) +CHIPSET(0x6727, BARTS_6727, BARTS) +CHIPSET(0x6728, BARTS_6728, BARTS) +CHIPSET(0x6729, BARTS_6729, BARTS) +CHIPSET(0x6738, BARTS_6738, BARTS) +CHIPSET(0x6739, BARTS_6739, BARTS) +CHIPSET(0x673E, BARTS_673E, BARTS) + +CHIPSET(0x6740, TURKS_6740, TURKS) +CHIPSET(0x6741, TURKS_6741, TURKS) +CHIPSET(0x6742, TURKS_6742, TURKS) +CHIPSET(0x6743, TURKS_6743, TURKS) +CHIPSET(0x6744, TURKS_6744, TURKS) +CHIPSET(0x6745, TURKS_6745, TURKS) +CHIPSET(0x6746, TURKS_6746, TURKS) +CHIPSET(0x6747, TURKS_6747, TURKS) +CHIPSET(0x6748, TURKS_6748, TURKS) +CHIPSET(0x6749, TURKS_6749, TURKS) +CHIPSET(0x674A, TURKS_674A, TURKS) +CHIPSET(0x6750, TURKS_6750, TURKS) +CHIPSET(0x6751, TURKS_6751, TURKS) +CHIPSET(0x6758, TURKS_6758, TURKS) +CHIPSET(0x6759, TURKS_6759, TURKS) +CHIPSET(0x675B, TURKS_675B, TURKS) +CHIPSET(0x675D, TURKS_675D, TURKS) +CHIPSET(0x675F, TURKS_675F, TURKS) +CHIPSET(0x6840, TURKS_6840, TURKS) +CHIPSET(0x6841, TURKS_6841, TURKS) +CHIPSET(0x6842, TURKS_6842, TURKS) +CHIPSET(0x6843, TURKS_6843, TURKS) +CHIPSET(0x6849, TURKS_6849, TURKS) +CHIPSET(0x6850, TURKS_6850, TURKS) +CHIPSET(0x6858, TURKS_6858, TURKS) +CHIPSET(0x6859, TURKS_6859, TURKS) + +CHIPSET(0x6760, CAICOS_6760, CAICOS) +CHIPSET(0x6761, CAICOS_6761, CAICOS) +CHIPSET(0x6762, CAICOS_6762, CAICOS) +CHIPSET(0x6763, CAICOS_6763, CAICOS) +CHIPSET(0x6764, CAICOS_6764, CAICOS) +CHIPSET(0x6765, CAICOS_6765, CAICOS) +CHIPSET(0x6766, CAICOS_6766, CAICOS) +CHIPSET(0x6767, CAICOS_6767, CAICOS) +CHIPSET(0x6768, CAICOS_6768, CAICOS) +CHIPSET(0x6770, CAICOS_6770, CAICOS) +CHIPSET(0x6771, CAICOS_6771, CAICOS) +CHIPSET(0x6772, CAICOS_6772, CAICOS) +CHIPSET(0x6778, CAICOS_6778, CAICOS) +CHIPSET(0x6779, CAICOS_6779, CAICOS) +CHIPSET(0x677B, CAICOS_677B, CAICOS) + +CHIPSET(0x9900, ARUBA_9900, ARUBA) +CHIPSET(0x9901, ARUBA_9901, ARUBA) +CHIPSET(0x9903, ARUBA_9903, ARUBA) +CHIPSET(0x9904, ARUBA_9904, ARUBA) +CHIPSET(0x9905, ARUBA_9905, ARUBA) +CHIPSET(0x9906, ARUBA_9906, ARUBA) +CHIPSET(0x9907, ARUBA_9907, ARUBA) +CHIPSET(0x9908, ARUBA_9908, ARUBA) +CHIPSET(0x9909, ARUBA_9909, ARUBA) +CHIPSET(0x990A, ARUBA_990A, ARUBA) +CHIPSET(0x990F, ARUBA_990F, ARUBA) +CHIPSET(0x9910, ARUBA_9910, ARUBA) +CHIPSET(0x9913, ARUBA_9913, ARUBA) +CHIPSET(0x9917, ARUBA_9917, ARUBA) +CHIPSET(0x9918, ARUBA_9918, ARUBA) +CHIPSET(0x9919, ARUBA_9919, ARUBA) +CHIPSET(0x9990, ARUBA_9990, ARUBA) +CHIPSET(0x9991, ARUBA_9991, ARUBA) +CHIPSET(0x9992, ARUBA_9992, ARUBA) +CHIPSET(0x9993, ARUBA_9993, ARUBA) +CHIPSET(0x9994, ARUBA_9994, ARUBA) +CHIPSET(0x99A0, ARUBA_99A0, ARUBA) +CHIPSET(0x99A2, ARUBA_99A2, ARUBA) +CHIPSET(0x99A4, ARUBA_99A4, ARUBA) + +CHIPSET(0x6780, TAHITI_6780, TAHITI) +CHIPSET(0x6784, TAHITI_6784, TAHITI) +CHIPSET(0x6788, TAHITI_6788, TAHITI) +CHIPSET(0x678A, TAHITI_678A, TAHITI) +CHIPSET(0x6790, TAHITI_6790, TAHITI) +CHIPSET(0x6798, TAHITI_6798, TAHITI) +CHIPSET(0x6799, TAHITI_6799, TAHITI) +CHIPSET(0x679A, TAHITI_679A, TAHITI) +CHIPSET(0x679E, TAHITI_679E, TAHITI) +CHIPSET(0x679F, TAHITI_679F, TAHITI) + +CHIPSET(0x6800, PITCAIRN_6800, PITCAIRN) +CHIPSET(0x6801, PITCAIRN_6801, PITCAIRN) +CHIPSET(0x6802, PITCAIRN_6802, PITCAIRN) +CHIPSET(0x6808, PITCAIRN_6808, PITCAIRN) +CHIPSET(0x6809, PITCAIRN_6809, PITCAIRN) +CHIPSET(0x6810, PITCAIRN_6810, PITCAIRN) +CHIPSET(0x6818, PITCAIRN_6818, PITCAIRN) +CHIPSET(0x6819, PITCAIRN_6819, PITCAIRN) +CHIPSET(0x684C, PITCAIRN_684C, PITCAIRN) + +CHIPSET(0x6820, VERDE_6820, VERDE) +CHIPSET(0x6821, VERDE_6821, VERDE) +CHIPSET(0x6823, VERDE_6823, VERDE) +CHIPSET(0x6824, VERDE_6824, VERDE) +CHIPSET(0x6825, VERDE_6825, VERDE) +CHIPSET(0x6826, VERDE_6826, VERDE) +CHIPSET(0x6827, VERDE_6827, VERDE) +CHIPSET(0x6828, VERDE_6828, VERDE) +CHIPSET(0x6829, VERDE_6829, VERDE) +CHIPSET(0x682B, VERDE_682B, VERDE) +CHIPSET(0x682D, VERDE_682D, VERDE) +CHIPSET(0x682F, VERDE_682F, VERDE) +CHIPSET(0x6830, VERDE_6830, VERDE) +CHIPSET(0x6831, VERDE_6831, VERDE) +CHIPSET(0x6837, VERDE_6837, VERDE) +CHIPSET(0x6838, VERDE_6838, VERDE) +CHIPSET(0x6839, VERDE_6839, VERDE) +CHIPSET(0x683B, VERDE_683B, VERDE) +CHIPSET(0x683D, VERDE_683D, VERDE) +CHIPSET(0x683F, VERDE_683F, VERDE) diff --git a/radeon/radeon_bo.c b/radeon/radeon_bo.c new file mode 100644 index 0000000..6a0f8e7 --- /dev/null +++ b/radeon/radeon_bo.c @@ -0,0 +1,141 @@ +/* + * Copyright © 2008 Dave Airlie + * Copyright © 2008 Jérôme Glisse + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS + * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Dave Airlie + * Jérôme Glisse + */ +#include +#include + +void radeon_bo_debug(struct radeon_bo *bo, const char *op) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + + fprintf(stderr, "%s %p 0x%08X 0x%08X 0x%08X\n", + op, bo, bo->handle, boi->size, boi->cref); +} + +struct radeon_bo *radeon_bo_open(struct radeon_bo_manager *bom, + uint32_t handle, + uint32_t size, + uint32_t alignment, + uint32_t domains, + uint32_t flags) +{ + struct radeon_bo *bo; + bo = bom->funcs->bo_open(bom, handle, size, alignment, domains, flags); + return bo; +} + +void radeon_bo_ref(struct radeon_bo *bo) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + boi->cref++; + boi->bom->funcs->bo_ref(boi); +} + +struct radeon_bo *radeon_bo_unref(struct radeon_bo *bo) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + if (bo == NULL) + return NULL; + + boi->cref--; + return boi->bom->funcs->bo_unref(boi); +} + +int radeon_bo_map(struct radeon_bo *bo, int write) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + return boi->bom->funcs->bo_map(boi, write); +} + +int radeon_bo_unmap(struct radeon_bo *bo) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + return boi->bom->funcs->bo_unmap(boi); +} + +int radeon_bo_wait(struct radeon_bo *bo) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + if (!boi->bom->funcs->bo_wait) + return 0; + return boi->bom->funcs->bo_wait(boi); +} + +int radeon_bo_is_busy(struct radeon_bo *bo, uint32_t *domain) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + return boi->bom->funcs->bo_is_busy(boi, domain); +} + +int radeon_bo_set_tiling(struct radeon_bo *bo, + uint32_t tiling_flags, uint32_t pitch) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + return boi->bom->funcs->bo_set_tiling(boi, tiling_flags, pitch); +} + +int radeon_bo_get_tiling(struct radeon_bo *bo, + uint32_t *tiling_flags, uint32_t *pitch) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + return boi->bom->funcs->bo_get_tiling(boi, tiling_flags, pitch); +} + +int radeon_bo_is_static(struct radeon_bo *bo) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + if (boi->bom->funcs->bo_is_static) + return boi->bom->funcs->bo_is_static(boi); + return 0; +} + +int radeon_bo_is_referenced_by_cs(struct radeon_bo *bo, struct radeon_cs *cs) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + return boi->cref > 1; +} + +uint32_t radeon_bo_get_handle(struct radeon_bo *bo) +{ + return bo->handle; +} + +uint32_t radeon_bo_get_src_domain(struct radeon_bo *bo) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + uint32_t src_domain; + + src_domain = boi->space_accounted & 0xffff; + if (!src_domain) + src_domain = boi->space_accounted >> 16; + + return src_domain; +} diff --git a/radeon/radeon_bo.h b/radeon/radeon_bo.h new file mode 100644 index 0000000..37478a0 --- /dev/null +++ b/radeon/radeon_bo.h @@ -0,0 +1,74 @@ +/* + * Copyright © 2008 Jérôme Glisse + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS + * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Jérôme Glisse + */ +#ifndef RADEON_BO_H +#define RADEON_BO_H + +#include +#include + +/* bo object */ +#define RADEON_BO_FLAGS_MACRO_TILE 1 +#define RADEON_BO_FLAGS_MICRO_TILE 2 +#define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20 + +struct radeon_bo_manager; +struct radeon_cs; + +struct radeon_bo { + void *ptr; + uint32_t flags; + uint32_t handle; + uint32_t size; +}; + +struct radeon_bo_manager; + +void radeon_bo_debug(struct radeon_bo *bo, const char *op); + +struct radeon_bo *radeon_bo_open(struct radeon_bo_manager *bom, + uint32_t handle, + uint32_t size, + uint32_t alignment, + uint32_t domains, + uint32_t flags); + +void radeon_bo_ref(struct radeon_bo *bo); +struct radeon_bo *radeon_bo_unref(struct radeon_bo *bo); +int radeon_bo_map(struct radeon_bo *bo, int write); +int radeon_bo_unmap(struct radeon_bo *bo); +int radeon_bo_wait(struct radeon_bo *bo); +int radeon_bo_is_busy(struct radeon_bo *bo, uint32_t *domain); +int radeon_bo_set_tiling(struct radeon_bo *bo, uint32_t tiling_flags, uint32_t pitch); +int radeon_bo_get_tiling(struct radeon_bo *bo, uint32_t *tiling_flags, uint32_t *pitch); +int radeon_bo_is_static(struct radeon_bo *bo); +int radeon_bo_is_referenced_by_cs(struct radeon_bo *bo, struct radeon_cs *cs); +uint32_t radeon_bo_get_handle(struct radeon_bo *bo); +uint32_t radeon_bo_get_src_domain(struct radeon_bo *bo); +#endif diff --git a/radeon/radeon_bo_gem.c b/radeon/radeon_bo_gem.c new file mode 100644 index 0000000..719fba7 --- /dev/null +++ b/radeon/radeon_bo_gem.c @@ -0,0 +1,351 @@ +/* + * Copyright © 2008 Dave Airlie + * Copyright © 2008 Jérôme Glisse + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS + * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Dave Airlie + * Jérôme Glisse + */ +#ifdef HAVE_CONFIG_H +#include +#endif +#include +#include +#include +#include +#include +#include +#include "xf86drm.h" +#include "xf86atomic.h" +#include "drm.h" +#include "radeon_drm.h" +#include "radeon_bo.h" +#include "radeon_bo_int.h" +#include "radeon_bo_gem.h" + +struct radeon_bo_gem { + struct radeon_bo_int base; + uint32_t name; + int map_count; + atomic_t reloc_in_cs; + void *priv_ptr; +}; + +struct bo_manager_gem { + struct radeon_bo_manager base; +}; + +static int bo_wait(struct radeon_bo_int *boi); + +static struct radeon_bo *bo_open(struct radeon_bo_manager *bom, + uint32_t handle, + uint32_t size, + uint32_t alignment, + uint32_t domains, + uint32_t flags) +{ + struct radeon_bo_gem *bo; + int r; + + bo = (struct radeon_bo_gem*)calloc(1, sizeof(struct radeon_bo_gem)); + if (bo == NULL) { + return NULL; + } + + bo->base.bom = bom; + bo->base.handle = 0; + bo->base.size = size; + bo->base.alignment = alignment; + bo->base.domains = domains; + bo->base.flags = flags; + bo->base.ptr = NULL; + atomic_set(&bo->reloc_in_cs, 0); + bo->map_count = 0; + if (handle) { + struct drm_gem_open open_arg; + + memset(&open_arg, 0, sizeof(open_arg)); + open_arg.name = handle; + r = drmIoctl(bom->fd, DRM_IOCTL_GEM_OPEN, &open_arg); + if (r != 0) { + free(bo); + return NULL; + } + bo->base.handle = open_arg.handle; + bo->base.size = open_arg.size; + bo->name = handle; + } else { + struct drm_radeon_gem_create args; + + args.size = size; + args.alignment = alignment; + args.initial_domain = bo->base.domains; + args.flags = 0; + args.handle = 0; + r = drmCommandWriteRead(bom->fd, DRM_RADEON_GEM_CREATE, + &args, sizeof(args)); + bo->base.handle = args.handle; + if (r) { + fprintf(stderr, "Failed to allocate :\n"); + fprintf(stderr, " size : %d bytes\n", size); + fprintf(stderr, " alignment : %d bytes\n", alignment); + fprintf(stderr, " domains : %d\n", bo->base.domains); + free(bo); + return NULL; + } + } + radeon_bo_ref((struct radeon_bo*)bo); + return (struct radeon_bo*)bo; +} + +static void bo_ref(struct radeon_bo_int *boi) +{ +} + +static struct radeon_bo *bo_unref(struct radeon_bo_int *boi) +{ + struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)boi; + struct drm_gem_close args; + + if (boi->cref) { + return (struct radeon_bo *)boi; + } + if (bo_gem->priv_ptr) { + munmap(bo_gem->priv_ptr, boi->size); + } + + /* Zero out args to make valgrind happy */ + memset(&args, 0, sizeof(args)); + + /* close object */ + args.handle = boi->handle; + drmIoctl(boi->bom->fd, DRM_IOCTL_GEM_CLOSE, &args); + memset(bo_gem, 0, sizeof(struct radeon_bo_gem)); + free(bo_gem); + return NULL; +} + +static int bo_map(struct radeon_bo_int *boi, int write) +{ + struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)boi; + struct drm_radeon_gem_mmap args; + int r; + void *ptr; + + if (bo_gem->map_count++ != 0) { + return 0; + } + if (bo_gem->priv_ptr) { + goto wait; + } + + boi->ptr = NULL; + + /* Zero out args to make valgrind happy */ + memset(&args, 0, sizeof(args)); + args.handle = boi->handle; + args.offset = 0; + args.size = (uint64_t)boi->size; + r = drmCommandWriteRead(boi->bom->fd, + DRM_RADEON_GEM_MMAP, + &args, + sizeof(args)); + if (r) { + fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n", + boi, boi->handle, r); + return r; + } + ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, boi->bom->fd, args.addr_ptr); + if (ptr == MAP_FAILED) + return -errno; + bo_gem->priv_ptr = ptr; +wait: + boi->ptr = bo_gem->priv_ptr; + r = bo_wait(boi); + if (r) + return r; + return 0; +} + +static int bo_unmap(struct radeon_bo_int *boi) +{ + struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)boi; + + if (--bo_gem->map_count > 0) { + return 0; + } + //munmap(bo->ptr, bo->size); + boi->ptr = NULL; + return 0; +} + +static int bo_wait(struct radeon_bo_int *boi) +{ + struct drm_radeon_gem_wait_idle args; + int ret; + + /* Zero out args to make valgrind happy */ + memset(&args, 0, sizeof(args)); + args.handle = boi->handle; + do { + ret = drmCommandWriteRead(boi->bom->fd, DRM_RADEON_GEM_WAIT_IDLE, + &args, sizeof(args)); + } while (ret == -EBUSY); + return ret; +} + +static int bo_is_busy(struct radeon_bo_int *boi, uint32_t *domain) +{ + struct drm_radeon_gem_busy args; + int ret; + + args.handle = boi->handle; + args.domain = 0; + + ret = drmCommandWriteRead(boi->bom->fd, DRM_RADEON_GEM_BUSY, + &args, sizeof(args)); + + *domain = args.domain; + return ret; +} + +static int bo_set_tiling(struct radeon_bo_int *boi, uint32_t tiling_flags, + uint32_t pitch) +{ + struct drm_radeon_gem_set_tiling args; + int r; + + args.handle = boi->handle; + args.tiling_flags = tiling_flags; + args.pitch = pitch; + + r = drmCommandWriteRead(boi->bom->fd, + DRM_RADEON_GEM_SET_TILING, + &args, + sizeof(args)); + return r; +} + +static int bo_get_tiling(struct radeon_bo_int *boi, uint32_t *tiling_flags, + uint32_t *pitch) +{ + struct drm_radeon_gem_set_tiling args = {}; + int r; + + args.handle = boi->handle; + + r = drmCommandWriteRead(boi->bom->fd, + DRM_RADEON_GEM_GET_TILING, + &args, + sizeof(args)); + + if (r) + return r; + + *tiling_flags = args.tiling_flags; + *pitch = args.pitch; + return r; +} + +static struct radeon_bo_funcs bo_gem_funcs = { + bo_open, + bo_ref, + bo_unref, + bo_map, + bo_unmap, + bo_wait, + NULL, + bo_set_tiling, + bo_get_tiling, + bo_is_busy, +}; + +struct radeon_bo_manager *radeon_bo_manager_gem_ctor(int fd) +{ + struct bo_manager_gem *bomg; + + bomg = (struct bo_manager_gem*)calloc(1, sizeof(struct bo_manager_gem)); + if (bomg == NULL) { + return NULL; + } + bomg->base.funcs = &bo_gem_funcs; + bomg->base.fd = fd; + return (struct radeon_bo_manager*)bomg; +} + +void radeon_bo_manager_gem_dtor(struct radeon_bo_manager *bom) +{ + struct bo_manager_gem *bomg = (struct bo_manager_gem*)bom; + + if (bom == NULL) { + return; + } + free(bomg); +} + +uint32_t radeon_gem_name_bo(struct radeon_bo *bo) +{ + struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo; + return bo_gem->name; +} + +void *radeon_gem_get_reloc_in_cs(struct radeon_bo *bo) +{ + struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo; + return &bo_gem->reloc_in_cs; +} + +int radeon_gem_get_kernel_name(struct radeon_bo *bo, uint32_t *name) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + struct drm_gem_flink flink; + int r; + + flink.handle = bo->handle; + r = drmIoctl(boi->bom->fd, DRM_IOCTL_GEM_FLINK, &flink); + if (r) { + return r; + } + *name = flink.name; + return 0; +} + +int radeon_gem_set_domain(struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + struct drm_radeon_gem_set_domain args; + int r; + + args.handle = bo->handle; + args.read_domains = read_domains; + args.write_domain = write_domain; + + r = drmCommandWriteRead(boi->bom->fd, + DRM_RADEON_GEM_SET_DOMAIN, + &args, + sizeof(args)); + return r; +} diff --git a/radeon/radeon_bo_gem.h b/radeon/radeon_bo_gem.h new file mode 100644 index 0000000..0af8610 --- /dev/null +++ b/radeon/radeon_bo_gem.h @@ -0,0 +1,44 @@ +/* + * Copyright © 2008 Dave Airlie + * Copyright © 2008 Jérôme Glisse + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS + * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Dave Airlie + * Jérôme Glisse + */ +#ifndef RADEON_BO_GEM_H +#define RADEON_BO_GEM_H + +#include "radeon_bo.h" + +struct radeon_bo_manager *radeon_bo_manager_gem_ctor(int fd); +void radeon_bo_manager_gem_dtor(struct radeon_bo_manager *bom); + +uint32_t radeon_gem_name_bo(struct radeon_bo *bo); +void *radeon_gem_get_reloc_in_cs(struct radeon_bo *bo); +int radeon_gem_set_domain(struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain); +int radeon_gem_get_kernel_name(struct radeon_bo *bo, uint32_t *name); +#endif diff --git a/radeon/radeon_bo_int.h b/radeon/radeon_bo_int.h new file mode 100644 index 0000000..9589ead --- /dev/null +++ b/radeon/radeon_bo_int.h @@ -0,0 +1,45 @@ +#ifndef RADEON_BO_INT +#define RADEON_BO_INT + +struct radeon_bo_manager { + struct radeon_bo_funcs *funcs; + int fd; +}; + +struct radeon_bo_int { + void *ptr; + uint32_t flags; + uint32_t handle; + uint32_t size; + /* private members */ + uint32_t alignment; + uint32_t domains; + unsigned cref; + struct radeon_bo_manager *bom; + uint32_t space_accounted; + uint32_t referenced_in_cs; +}; + +/* bo functions */ +struct radeon_bo_funcs { + struct radeon_bo *(*bo_open)(struct radeon_bo_manager *bom, + uint32_t handle, + uint32_t size, + uint32_t alignment, + uint32_t domains, + uint32_t flags); + void (*bo_ref)(struct radeon_bo_int *bo); + struct radeon_bo *(*bo_unref)(struct radeon_bo_int *bo); + int (*bo_map)(struct radeon_bo_int *bo, int write); + int (*bo_unmap)(struct radeon_bo_int *bo); + int (*bo_wait)(struct radeon_bo_int *bo); + int (*bo_is_static)(struct radeon_bo_int *bo); + int (*bo_set_tiling)(struct radeon_bo_int *bo, uint32_t tiling_flags, + uint32_t pitch); + int (*bo_get_tiling)(struct radeon_bo_int *bo, uint32_t *tiling_flags, + uint32_t *pitch); + int (*bo_is_busy)(struct radeon_bo_int *bo, uint32_t *domain); + int (*bo_is_referenced_by_cs)(struct radeon_bo_int *bo, struct radeon_cs *cs); +}; + +#endif diff --git a/radeon/radeon_cs.c b/radeon/radeon_cs.c new file mode 100644 index 0000000..d0e922b --- /dev/null +++ b/radeon/radeon_cs.c @@ -0,0 +1,96 @@ + +#include +#include "radeon_cs.h" +#include "radeon_cs_int.h" + +struct radeon_cs *radeon_cs_create(struct radeon_cs_manager *csm, uint32_t ndw) +{ + struct radeon_cs_int *csi = csm->funcs->cs_create(csm, ndw); + return (struct radeon_cs *)csi; +} + +int radeon_cs_write_reloc(struct radeon_cs *cs, + struct radeon_bo *bo, + uint32_t read_domain, + uint32_t write_domain, + uint32_t flags) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + + return csi->csm->funcs->cs_write_reloc(csi, + bo, + read_domain, + write_domain, + flags); +} + +int radeon_cs_begin(struct radeon_cs *cs, + uint32_t ndw, + const char *file, + const char *func, + int line) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + return csi->csm->funcs->cs_begin(csi, ndw, file, func, line); +} + +int radeon_cs_end(struct radeon_cs *cs, + const char *file, + const char *func, + int line) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + return csi->csm->funcs->cs_end(csi, file, func, line); +} + +int radeon_cs_emit(struct radeon_cs *cs) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + return csi->csm->funcs->cs_emit(csi); +} + +int radeon_cs_destroy(struct radeon_cs *cs) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + return csi->csm->funcs->cs_destroy(csi); +} + +int radeon_cs_erase(struct radeon_cs *cs) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + return csi->csm->funcs->cs_erase(csi); +} + +int radeon_cs_need_flush(struct radeon_cs *cs) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + return csi->csm->funcs->cs_need_flush(csi); +} + +void radeon_cs_print(struct radeon_cs *cs, FILE *file) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + csi->csm->funcs->cs_print(csi, file); +} + +void radeon_cs_set_limit(struct radeon_cs *cs, uint32_t domain, uint32_t limit) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + if (domain == RADEON_GEM_DOMAIN_VRAM) + csi->csm->vram_limit = limit; + else + csi->csm->gart_limit = limit; +} + +void radeon_cs_space_set_flush(struct radeon_cs *cs, void (*fn)(void *), void *data) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + csi->space_flush_fn = fn; + csi->space_flush_data = data; +} + +uint32_t radeon_cs_get_id(struct radeon_cs *cs) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + return csi->id; +} diff --git a/radeon/radeon_cs.h b/radeon/radeon_cs.h new file mode 100644 index 0000000..f68a624 --- /dev/null +++ b/radeon/radeon_cs.h @@ -0,0 +1,141 @@ +/* + * Copyright © 2008 Nicolai Haehnle + * Copyright © 2008 Jérôme Glisse + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Aapo Tahkola + * Nicolai Haehnle + * Jérôme Glisse + */ +#ifndef RADEON_CS_H +#define RADEON_CS_H + +#include +#include +#include "drm.h" +#include "radeon_drm.h" +#include "radeon_bo.h" + +struct radeon_cs_reloc { + struct radeon_bo *bo; + uint32_t read_domain; + uint32_t write_domain; + uint32_t flags; +}; + + +#define RADEON_CS_SPACE_OK 0 +#define RADEON_CS_SPACE_OP_TO_BIG 1 +#define RADEON_CS_SPACE_FLUSH 2 + +struct radeon_cs { + uint32_t *packets; + unsigned cdw; + unsigned ndw; + unsigned section_ndw; + unsigned section_cdw; +}; + +#define MAX_SPACE_BOS (32) + +struct radeon_cs_manager; + +extern struct radeon_cs *radeon_cs_create(struct radeon_cs_manager *csm, + uint32_t ndw); + +extern int radeon_cs_begin(struct radeon_cs *cs, + uint32_t ndw, + const char *file, + const char *func, int line); +extern int radeon_cs_end(struct radeon_cs *cs, + const char *file, + const char *func, + int line); +extern int radeon_cs_emit(struct radeon_cs *cs); +extern int radeon_cs_destroy(struct radeon_cs *cs); +extern int radeon_cs_erase(struct radeon_cs *cs); +extern int radeon_cs_need_flush(struct radeon_cs *cs); +extern void radeon_cs_print(struct radeon_cs *cs, FILE *file); +extern void radeon_cs_set_limit(struct radeon_cs *cs, uint32_t domain, uint32_t limit); +extern void radeon_cs_space_set_flush(struct radeon_cs *cs, void (*fn)(void *), void *data); +extern int radeon_cs_write_reloc(struct radeon_cs *cs, + struct radeon_bo *bo, + uint32_t read_domain, + uint32_t write_domain, + uint32_t flags); +extern uint32_t radeon_cs_get_id(struct radeon_cs *cs); +/* + * add a persistent BO to the list + * a persistent BO is one that will be referenced across flushes, + * i.e. colorbuffer, textures etc. + * They get reset when a new "operation" happens, where an operation + * is a state emission with a color/textures etc followed by a bunch of vertices. + */ +void radeon_cs_space_add_persistent_bo(struct radeon_cs *cs, + struct radeon_bo *bo, + uint32_t read_domains, + uint32_t write_domain); + +/* reset the persistent BO list */ +void radeon_cs_space_reset_bos(struct radeon_cs *cs); + +/* do a space check with the current persistent BO list */ +int radeon_cs_space_check(struct radeon_cs *cs); + +/* do a space check with the current persistent BO list and a temporary BO + * a temporary BO is like a DMA buffer, which gets flushed with the + * command buffer */ +int radeon_cs_space_check_with_bo(struct radeon_cs *cs, + struct radeon_bo *bo, + uint32_t read_domains, + uint32_t write_domain); + +static inline void radeon_cs_write_dword(struct radeon_cs *cs, uint32_t dword) +{ + cs->packets[cs->cdw++] = dword; + if (cs->section_ndw) { + cs->section_cdw++; + } +} + +static inline void radeon_cs_write_qword(struct radeon_cs *cs, uint64_t qword) +{ + memcpy(cs->packets + cs->cdw, &qword, sizeof(uint64_t)); + cs->cdw += 2; + if (cs->section_ndw) { + cs->section_cdw += 2; + } +} + +static inline void radeon_cs_write_table(struct radeon_cs *cs, + const void *data, uint32_t size) +{ + memcpy(cs->packets + cs->cdw, data, size * 4); + cs->cdw += size; + if (cs->section_ndw) { + cs->section_cdw += size; + } +} +#endif diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c new file mode 100644 index 0000000..9834bcf --- /dev/null +++ b/radeon/radeon_cs_gem.c @@ -0,0 +1,548 @@ +/* + * Copyright © 2008 Jérôme Glisse + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS + * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Aapo Tahkola + * Nicolai Haehnle + * Jérôme Glisse + */ +#include +#include +#include +#include +#include +#include +#include +#include "radeon_cs.h" +#include "radeon_cs_int.h" +#include "radeon_bo_int.h" +#include "radeon_cs_gem.h" +#include "radeon_bo_gem.h" +#include "drm.h" +#include "xf86drm.h" +#include "xf86atomic.h" +#include "radeon_drm.h" +#include "bof.h" + +#define CS_BOF_DUMP 0 + +struct radeon_cs_manager_gem { + struct radeon_cs_manager base; + uint32_t device_id; + unsigned nbof; +}; + +#pragma pack(1) +struct cs_reloc_gem { + uint32_t handle; + uint32_t read_domain; + uint32_t write_domain; + uint32_t flags; +}; + +#pragma pack() +#define RELOC_SIZE (sizeof(struct cs_reloc_gem) / sizeof(uint32_t)) + +struct cs_gem { + struct radeon_cs_int base; + struct drm_radeon_cs cs; + struct drm_radeon_cs_chunk chunks[2]; + unsigned nrelocs; + uint32_t *relocs; + struct radeon_bo_int **relocs_bo; +}; + +static pthread_mutex_t id_mutex = PTHREAD_MUTEX_INITIALIZER; +static uint32_t cs_id_source = 0; + +/** + * result is undefined if called with ~0 + */ +static uint32_t get_first_zero(const uint32_t n) +{ + /* __builtin_ctz returns number of trailing zeros. */ + return 1 << __builtin_ctz(~n); +} + +/** + * Returns a free id for cs. + * If there is no free id we return zero + **/ +static uint32_t generate_id(void) +{ + uint32_t r = 0; + pthread_mutex_lock( &id_mutex ); + /* check for free ids */ + if (cs_id_source != ~r) { + /* find first zero bit */ + r = get_first_zero(cs_id_source); + + /* set id as reserved */ + cs_id_source |= r; + } + pthread_mutex_unlock( &id_mutex ); + return r; +} + +/** + * Free the id for later reuse + **/ +static void free_id(uint32_t id) +{ + pthread_mutex_lock( &id_mutex ); + + cs_id_source &= ~id; + + pthread_mutex_unlock( &id_mutex ); +} + +static struct radeon_cs_int *cs_gem_create(struct radeon_cs_manager *csm, + uint32_t ndw) +{ + struct cs_gem *csg; + + /* max cmd buffer size is 64Kb */ + if (ndw > (64 * 1024 / 4)) { + return NULL; + } + csg = (struct cs_gem*)calloc(1, sizeof(struct cs_gem)); + if (csg == NULL) { + return NULL; + } + csg->base.csm = csm; + csg->base.ndw = 64 * 1024 / 4; + csg->base.packets = (uint32_t*)calloc(1, 64 * 1024); + if (csg->base.packets == NULL) { + free(csg); + return NULL; + } + csg->base.relocs_total_size = 0; + csg->base.crelocs = 0; + csg->base.id = generate_id(); + csg->nrelocs = 4096 / (4 * 4) ; + csg->relocs_bo = (struct radeon_bo_int**)calloc(1, + csg->nrelocs*sizeof(void*)); + if (csg->relocs_bo == NULL) { + free(csg->base.packets); + free(csg); + return NULL; + } + csg->base.relocs = csg->relocs = (uint32_t*)calloc(1, 4096); + if (csg->relocs == NULL) { + free(csg->relocs_bo); + free(csg->base.packets); + free(csg); + return NULL; + } + csg->chunks[0].chunk_id = RADEON_CHUNK_ID_IB; + csg->chunks[0].length_dw = 0; + csg->chunks[0].chunk_data = (uint64_t)(uintptr_t)csg->base.packets; + csg->chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS; + csg->chunks[1].length_dw = 0; + csg->chunks[1].chunk_data = (uint64_t)(uintptr_t)csg->relocs; + return (struct radeon_cs_int*)csg; +} + +static int cs_gem_write_reloc(struct radeon_cs_int *cs, + struct radeon_bo *bo, + uint32_t read_domain, + uint32_t write_domain, + uint32_t flags) +{ + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + struct cs_gem *csg = (struct cs_gem*)cs; + struct cs_reloc_gem *reloc; + uint32_t idx; + unsigned i; + + assert(boi->space_accounted); + + /* check domains */ + if ((read_domain && write_domain) || (!read_domain && !write_domain)) { + /* in one CS a bo can only be in read or write domain but not + * in read & write domain at the same sime + */ + return -EINVAL; + } + if (read_domain == RADEON_GEM_DOMAIN_CPU) { + return -EINVAL; + } + if (write_domain == RADEON_GEM_DOMAIN_CPU) { + return -EINVAL; + } + /* use bit field hash function to determine + if this bo is for sure not in this cs.*/ + if ((atomic_read((atomic_t *)radeon_gem_get_reloc_in_cs(bo)) & cs->id)) { + /* check if bo is already referenced. + * Scanning from end to begin reduces cycles with mesa because + * it often relocates same shared dma bo again. */ + for(i = cs->crelocs; i != 0;) { + --i; + idx = i * RELOC_SIZE; + reloc = (struct cs_reloc_gem*)&csg->relocs[idx]; + if (reloc->handle == bo->handle) { + /* Check domains must be in read or write. As we check already + * checked that in argument one of the read or write domain was + * set we only need to check that if previous reloc as the read + * domain set then the read_domain should also be set for this + * new relocation. + */ + /* the DDX expects to read and write from same pixmap */ + if (write_domain && (reloc->read_domain & write_domain)) { + reloc->read_domain = 0; + reloc->write_domain = write_domain; + } else if (read_domain & reloc->write_domain) { + reloc->read_domain = 0; + } else { + if (write_domain != reloc->write_domain) + return -EINVAL; + if (read_domain != reloc->read_domain) + return -EINVAL; + } + + reloc->read_domain |= read_domain; + reloc->write_domain |= write_domain; + /* update flags */ + reloc->flags |= (flags & reloc->flags); + /* write relocation packet */ + radeon_cs_write_dword((struct radeon_cs *)cs, 0xc0001000); + radeon_cs_write_dword((struct radeon_cs *)cs, idx); + return 0; + } + } + } + /* new relocation */ + if (csg->base.crelocs >= csg->nrelocs) { + /* allocate more memory (TODO: should use a slab allocatore maybe) */ + uint32_t *tmp, size; + size = ((csg->nrelocs + 1) * sizeof(struct radeon_bo*)); + tmp = (uint32_t*)realloc(csg->relocs_bo, size); + if (tmp == NULL) { + return -ENOMEM; + } + csg->relocs_bo = (struct radeon_bo_int **)tmp; + size = ((csg->nrelocs + 1) * RELOC_SIZE * 4); + tmp = (uint32_t*)realloc(csg->relocs, size); + if (tmp == NULL) { + return -ENOMEM; + } + cs->relocs = csg->relocs = tmp; + csg->nrelocs += 1; + csg->chunks[1].chunk_data = (uint64_t)(uintptr_t)csg->relocs; + } + csg->relocs_bo[csg->base.crelocs] = boi; + idx = (csg->base.crelocs++) * RELOC_SIZE; + reloc = (struct cs_reloc_gem*)&csg->relocs[idx]; + reloc->handle = bo->handle; + reloc->read_domain = read_domain; + reloc->write_domain = write_domain; + reloc->flags = flags; + csg->chunks[1].length_dw += RELOC_SIZE; + radeon_bo_ref(bo); + /* bo might be referenced from another context so have to use atomic opertions */ + atomic_add((atomic_t *)radeon_gem_get_reloc_in_cs(bo), cs->id); + cs->relocs_total_size += boi->size; + radeon_cs_write_dword((struct radeon_cs *)cs, 0xc0001000); + radeon_cs_write_dword((struct radeon_cs *)cs, idx); + return 0; +} + +static int cs_gem_begin(struct radeon_cs_int *cs, + uint32_t ndw, + const char *file, + const char *func, + int line) +{ + + if (cs->section_ndw) { + fprintf(stderr, "CS already in a section(%s,%s,%d)\n", + cs->section_file, cs->section_func, cs->section_line); + fprintf(stderr, "CS can't start section(%s,%s,%d)\n", + file, func, line); + return -EPIPE; + } + cs->section_ndw = ndw; + cs->section_cdw = 0; + cs->section_file = file; + cs->section_func = func; + cs->section_line = line; + + if (cs->cdw + ndw > cs->ndw) { + uint32_t tmp, *ptr; + + /* round up the required size to a multiple of 1024 */ + tmp = (cs->cdw + ndw + 0x3FF) & (~0x3FF); + ptr = (uint32_t*)realloc(cs->packets, 4 * tmp); + if (ptr == NULL) { + return -ENOMEM; + } + cs->packets = ptr; + cs->ndw = tmp; + } + return 0; +} + +static int cs_gem_end(struct radeon_cs_int *cs, + const char *file, + const char *func, + int line) + +{ + if (!cs->section_ndw) { + fprintf(stderr, "CS no section to end at (%s,%s,%d)\n", + file, func, line); + return -EPIPE; + } + if (cs->section_ndw != cs->section_cdw) { + fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n", + cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw); + fprintf(stderr, "CS section end at (%s,%s,%d)\n", + file, func, line); + + /* We must reset the section even when there is error. */ + cs->section_ndw = 0; + return -EPIPE; + } + cs->section_ndw = 0; + return 0; +} + +static void cs_gem_dump_bof(struct radeon_cs_int *cs) +{ + struct cs_gem *csg = (struct cs_gem*)cs; + struct radeon_cs_manager_gem *csm; + bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root; + char tmp[256]; + unsigned i; + + csm = (struct radeon_cs_manager_gem *)cs->csm; + root = device_id = bcs = blob = array = bo = size = handle = NULL; + root = bof_object(); + if (root == NULL) + goto out_err; + device_id = bof_int32(csm->device_id); + if (device_id == NULL) + return; + if (bof_object_set(root, "device_id", device_id)) + goto out_err; + bof_decref(device_id); + device_id = NULL; + /* dump relocs */ + blob = bof_blob(csg->nrelocs * 16, csg->relocs); + if (blob == NULL) + goto out_err; + if (bof_object_set(root, "reloc", blob)) + goto out_err; + bof_decref(blob); + blob = NULL; + /* dump cs */ + blob = bof_blob(cs->cdw * 4, cs->packets); + if (blob == NULL) + goto out_err; + if (bof_object_set(root, "pm4", blob)) + goto out_err; + bof_decref(blob); + blob = NULL; + /* dump bo */ + array = bof_array(); + if (array == NULL) + goto out_err; + for (i = 0; i < csg->base.crelocs; i++) { + bo = bof_object(); + if (bo == NULL) + goto out_err; + size = bof_int32(csg->relocs_bo[i]->size); + if (size == NULL) + goto out_err; + if (bof_object_set(bo, "size", size)) + goto out_err; + bof_decref(size); + size = NULL; + handle = bof_int32(csg->relocs_bo[i]->handle); + if (handle == NULL) + goto out_err; + if (bof_object_set(bo, "handle", handle)) + goto out_err; + bof_decref(handle); + handle = NULL; + radeon_bo_map((struct radeon_bo*)csg->relocs_bo[i], 0); + blob = bof_blob(csg->relocs_bo[i]->size, csg->relocs_bo[i]->ptr); + radeon_bo_unmap((struct radeon_bo*)csg->relocs_bo[i]); + if (blob == NULL) + goto out_err; + if (bof_object_set(bo, "data", blob)) + goto out_err; + bof_decref(blob); + blob = NULL; + if (bof_array_append(array, bo)) + goto out_err; + bof_decref(bo); + bo = NULL; + } + if (bof_object_set(root, "bo", array)) + goto out_err; + sprintf(tmp, "d-0x%04X-%08d.bof", csm->device_id, csm->nbof++); + bof_dump_file(root, tmp); +out_err: + bof_decref(blob); + bof_decref(array); + bof_decref(bo); + bof_decref(size); + bof_decref(handle); + bof_decref(device_id); + bof_decref(root); +} + +static int cs_gem_emit(struct radeon_cs_int *cs) +{ + struct cs_gem *csg = (struct cs_gem*)cs; + uint64_t chunk_array[2]; + unsigned i; + int r; + +#if CS_BOF_DUMP + cs_gem_dump_bof(cs); +#endif + csg->chunks[0].length_dw = cs->cdw; + + chunk_array[0] = (uint64_t)(uintptr_t)&csg->chunks[0]; + chunk_array[1] = (uint64_t)(uintptr_t)&csg->chunks[1]; + + csg->cs.num_chunks = 2; + csg->cs.chunks = (uint64_t)(uintptr_t)chunk_array; + + r = drmCommandWriteRead(cs->csm->fd, DRM_RADEON_CS, + &csg->cs, sizeof(struct drm_radeon_cs)); + for (i = 0; i < csg->base.crelocs; i++) { + csg->relocs_bo[i]->space_accounted = 0; + /* bo might be referenced from another context so have to use atomic opertions */ + atomic_dec((atomic_t *)radeon_gem_get_reloc_in_cs((struct radeon_bo*)csg->relocs_bo[i]), cs->id); + radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]); + csg->relocs_bo[i] = NULL; + } + + cs->csm->read_used = 0; + cs->csm->vram_write_used = 0; + cs->csm->gart_write_used = 0; + return r; +} + +static int cs_gem_destroy(struct radeon_cs_int *cs) +{ + struct cs_gem *csg = (struct cs_gem*)cs; + + free_id(cs->id); + free(csg->relocs_bo); + free(cs->relocs); + free(cs->packets); + free(cs); + return 0; +} + +static int cs_gem_erase(struct radeon_cs_int *cs) +{ + struct cs_gem *csg = (struct cs_gem*)cs; + unsigned i; + + if (csg->relocs_bo) { + for (i = 0; i < csg->base.crelocs; i++) { + if (csg->relocs_bo[i]) { + /* bo might be referenced from another context so have to use atomic opertions */ + atomic_dec((atomic_t *)radeon_gem_get_reloc_in_cs((struct radeon_bo*)csg->relocs_bo[i]), cs->id); + radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]); + csg->relocs_bo[i] = NULL; + } + } + } + cs->relocs_total_size = 0; + cs->cdw = 0; + cs->section_ndw = 0; + cs->crelocs = 0; + csg->chunks[0].length_dw = 0; + csg->chunks[1].length_dw = 0; + return 0; +} + +static int cs_gem_need_flush(struct radeon_cs_int *cs) +{ + return 0; //(cs->relocs_total_size > (32*1024*1024)); +} + +static void cs_gem_print(struct radeon_cs_int *cs, FILE *file) +{ + struct radeon_cs_manager_gem *csm; + unsigned int i; + + csm = (struct radeon_cs_manager_gem *)cs->csm; + fprintf(file, "VENDORID:DEVICEID 0x%04X:0x%04X\n", 0x1002, csm->device_id); + for (i = 0; i < cs->cdw; i++) { + fprintf(file, "0x%08X\n", cs->packets[i]); + } +} + +static struct radeon_cs_funcs radeon_cs_gem_funcs = { + cs_gem_create, + cs_gem_write_reloc, + cs_gem_begin, + cs_gem_end, + cs_gem_emit, + cs_gem_destroy, + cs_gem_erase, + cs_gem_need_flush, + cs_gem_print, +}; + +static int radeon_get_device_id(int fd, uint32_t *device_id) +{ + struct drm_radeon_info info = {}; + int r; + + *device_id = 0; + info.request = RADEON_INFO_DEVICE_ID; + info.value = (uintptr_t)device_id; + r = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, + sizeof(struct drm_radeon_info)); + return r; +} + +struct radeon_cs_manager *radeon_cs_manager_gem_ctor(int fd) +{ + struct radeon_cs_manager_gem *csm; + + csm = calloc(1, sizeof(struct radeon_cs_manager_gem)); + if (csm == NULL) { + return NULL; + } + csm->base.funcs = &radeon_cs_gem_funcs; + csm->base.fd = fd; + radeon_get_device_id(fd, &csm->device_id); + return &csm->base; +} + +void radeon_cs_manager_gem_dtor(struct radeon_cs_manager *csm) +{ + free(csm); +} diff --git a/radeon/radeon_cs_gem.h b/radeon/radeon_cs_gem.h new file mode 100644 index 0000000..5dea38a --- /dev/null +++ b/radeon/radeon_cs_gem.h @@ -0,0 +1,41 @@ +/* + * Copyright © 2008 Nicolai Haehnle + * Copyright © 2008 Jérôme Glisse + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS + * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Aapo Tahkola + * Nicolai Haehnle + * Jérôme Glisse + */ +#ifndef RADEON_CS_GEM_H +#define RADEON_CS_GEM_H + +#include "radeon_cs.h" + +struct radeon_cs_manager *radeon_cs_manager_gem_ctor(int fd); +void radeon_cs_manager_gem_dtor(struct radeon_cs_manager *csm); + +#endif diff --git a/radeon/radeon_cs_int.h b/radeon/radeon_cs_int.h new file mode 100644 index 0000000..6cee574 --- /dev/null +++ b/radeon/radeon_cs_int.h @@ -0,0 +1,67 @@ + +#ifndef _RADEON_CS_INT_H_ +#define _RADEON_CS_INT_H_ + +struct radeon_cs_space_check { + struct radeon_bo_int *bo; + uint32_t read_domains; + uint32_t write_domain; + uint32_t new_accounted; +}; + +struct radeon_cs_int { + /* keep first two in same place */ + uint32_t *packets; + unsigned cdw; + unsigned ndw; + unsigned section_ndw; + unsigned section_cdw; + /* private members */ + struct radeon_cs_manager *csm; + void *relocs; + unsigned crelocs; + unsigned relocs_total_size; + const char *section_file; + const char *section_func; + int section_line; + struct radeon_cs_space_check bos[MAX_SPACE_BOS]; + int bo_count; + void (*space_flush_fn)(void *); + void *space_flush_data; + uint32_t id; +}; + +/* cs functions */ +struct radeon_cs_funcs { + struct radeon_cs_int *(*cs_create)(struct radeon_cs_manager *csm, + uint32_t ndw); + int (*cs_write_reloc)(struct radeon_cs_int *cs, + struct radeon_bo *bo, + uint32_t read_domain, + uint32_t write_domain, + uint32_t flags); + int (*cs_begin)(struct radeon_cs_int *cs, + uint32_t ndw, + const char *file, + const char *func, + int line); + int (*cs_end)(struct radeon_cs_int *cs, + const char *file, const char *func, + int line); + + + int (*cs_emit)(struct radeon_cs_int *cs); + int (*cs_destroy)(struct radeon_cs_int *cs); + int (*cs_erase)(struct radeon_cs_int *cs); + int (*cs_need_flush)(struct radeon_cs_int *cs); + void (*cs_print)(struct radeon_cs_int *cs, FILE *file); +}; + +struct radeon_cs_manager { + struct radeon_cs_funcs *funcs; + int fd; + int32_t vram_limit, gart_limit; + int32_t vram_write_used, gart_write_used; + int32_t read_used; +}; +#endif diff --git a/radeon/radeon_cs_space.c b/radeon/radeon_cs_space.c new file mode 100644 index 0000000..be047a7 --- /dev/null +++ b/radeon/radeon_cs_space.c @@ -0,0 +1,245 @@ +/* + * Copyright © 2009 Red Hat Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS + * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + */ +#include +#include +#include +#include "radeon_cs.h" +#include "radeon_bo_int.h" +#include "radeon_cs_int.h" + +struct rad_sizes { + int32_t op_read; + int32_t op_gart_write; + int32_t op_vram_write; +}; + +static inline int radeon_cs_setup_bo(struct radeon_cs_space_check *sc, struct rad_sizes *sizes) +{ + uint32_t read_domains, write_domain; + struct radeon_bo_int *bo; + + bo = sc->bo; + sc->new_accounted = 0; + read_domains = sc->read_domains; + write_domain = sc->write_domain; + + /* legacy needs a static check */ + if (radeon_bo_is_static((struct radeon_bo *)sc->bo)) { + bo->space_accounted = sc->new_accounted = (read_domains << 16) | write_domain; + return 0; + } + + /* already accounted this bo */ + if (write_domain && (write_domain == bo->space_accounted)) { + sc->new_accounted = bo->space_accounted; + return 0; + } + if (read_domains && ((read_domains << 16) == bo->space_accounted)) { + sc->new_accounted = bo->space_accounted; + return 0; + } + + if (bo->space_accounted == 0) { + if (write_domain) { + if (write_domain == RADEON_GEM_DOMAIN_VRAM) + sizes->op_vram_write += bo->size; + else if (write_domain == RADEON_GEM_DOMAIN_GTT) + sizes->op_gart_write += bo->size; + sc->new_accounted = write_domain; + } else { + sizes->op_read += bo->size; + sc->new_accounted = read_domains << 16; + } + } else { + uint16_t old_read, old_write; + + old_read = bo->space_accounted >> 16; + old_write = bo->space_accounted & 0xffff; + + if (write_domain && (old_read & write_domain)) { + sc->new_accounted = write_domain; + /* moving from read to a write domain */ + if (write_domain == RADEON_GEM_DOMAIN_VRAM) { + sizes->op_read -= bo->size; + sizes->op_vram_write += bo->size; + } else if (write_domain == RADEON_GEM_DOMAIN_GTT) { + sizes->op_read -= bo->size; + sizes->op_gart_write += bo->size; + } + } else if (read_domains & old_write) { + sc->new_accounted = bo->space_accounted & 0xffff; + } else { + /* rewrite the domains */ + if (write_domain != old_write) + fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write); + if (read_domains != old_read) + fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read); + return RADEON_CS_SPACE_FLUSH; + } + } + return 0; +} + +static int radeon_cs_do_space_check(struct radeon_cs_int *cs, struct radeon_cs_space_check *new_tmp) +{ + struct radeon_cs_manager *csm = cs->csm; + int i; + struct radeon_bo_int *bo; + struct rad_sizes sizes; + int ret; + + /* check the totals for this operation */ + + if (cs->bo_count == 0 && !new_tmp) + return 0; + + memset(&sizes, 0, sizeof(struct rad_sizes)); + + /* prepare */ + for (i = 0; i < cs->bo_count; i++) { + ret = radeon_cs_setup_bo(&cs->bos[i], &sizes); + if (ret) + return ret; + } + + if (new_tmp) { + ret = radeon_cs_setup_bo(new_tmp, &sizes); + if (ret) + return ret; + } + + if (sizes.op_read < 0) + sizes.op_read = 0; + + /* check sizes - operation first */ + if ((sizes.op_read + sizes.op_gart_write > csm->gart_limit) || + (sizes.op_vram_write > csm->vram_limit)) { + return RADEON_CS_SPACE_OP_TO_BIG; + } + + if (((csm->vram_write_used + sizes.op_vram_write) > csm->vram_limit) || + ((csm->read_used + csm->gart_write_used + sizes.op_gart_write + sizes.op_read) > csm->gart_limit)) { + return RADEON_CS_SPACE_FLUSH; + } + + csm->gart_write_used += sizes.op_gart_write; + csm->vram_write_used += sizes.op_vram_write; + csm->read_used += sizes.op_read; + /* commit */ + for (i = 0; i < cs->bo_count; i++) { + bo = cs->bos[i].bo; + bo->space_accounted = cs->bos[i].new_accounted; + } + if (new_tmp) + new_tmp->bo->space_accounted = new_tmp->new_accounted; + + return RADEON_CS_SPACE_OK; +} + +void radeon_cs_space_add_persistent_bo(struct radeon_cs *cs, struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + int i; + for (i = 0; i < csi->bo_count; i++) { + if (csi->bos[i].bo == boi && + csi->bos[i].read_domains == read_domains && + csi->bos[i].write_domain == write_domain) + return; + } + radeon_bo_ref(bo); + i = csi->bo_count; + csi->bos[i].bo = boi; + csi->bos[i].read_domains = read_domains; + csi->bos[i].write_domain = write_domain; + csi->bos[i].new_accounted = 0; + csi->bo_count++; + + assert(csi->bo_count < MAX_SPACE_BOS); +} + +static int radeon_cs_check_space_internal(struct radeon_cs_int *cs, + struct radeon_cs_space_check *tmp_bo) +{ + int ret; + int flushed = 0; + +again: + ret = radeon_cs_do_space_check(cs, tmp_bo); + if (ret == RADEON_CS_SPACE_OP_TO_BIG) + return -1; + if (ret == RADEON_CS_SPACE_FLUSH) { + (*cs->space_flush_fn)(cs->space_flush_data); + if (flushed) + return -1; + flushed = 1; + goto again; + } + return 0; +} + +int radeon_cs_space_check_with_bo(struct radeon_cs *cs, + struct radeon_bo *bo, + uint32_t read_domains, uint32_t write_domain) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + struct radeon_bo_int *boi = (struct radeon_bo_int *)bo; + struct radeon_cs_space_check temp_bo; + + int ret = 0; + + if (bo) { + temp_bo.bo = boi; + temp_bo.read_domains = read_domains; + temp_bo.write_domain = write_domain; + temp_bo.new_accounted = 0; + } + + ret = radeon_cs_check_space_internal(csi, bo ? &temp_bo : NULL); + return ret; +} + +int radeon_cs_space_check(struct radeon_cs *cs) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + return radeon_cs_check_space_internal(csi, NULL); +} + +void radeon_cs_space_reset_bos(struct radeon_cs *cs) +{ + struct radeon_cs_int *csi = (struct radeon_cs_int *)cs; + int i; + for (i = 0; i < csi->bo_count; i++) { + radeon_bo_unref((struct radeon_bo *)csi->bos[i].bo); + csi->bos[i].bo = NULL; + csi->bos[i].read_domains = 0; + csi->bos[i].write_domain = 0; + csi->bos[i].new_accounted = 0; + } + csi->bo_count = 0; +} diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c new file mode 100644 index 0000000..adf209d --- /dev/null +++ b/radeon/radeon_surface.c @@ -0,0 +1,1025 @@ +/* + * Copyright © 2011 Red Hat All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS + * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Jérôme Glisse + */ +#include +#include +#include +#include +#include +#include +#include "drm.h" +#include "xf86drm.h" +#include "radeon_drm.h" +#include "radeon_surface.h" + +#define ALIGN(value, alignment) (((value) + alignment - 1) & ~(alignment - 1)) +#define MAX2(A, B) ((A) > (B) ? (A) : (B)) +#define MIN2(A, B) ((A) < (B) ? (A) : (B)) + +/* keep this private */ +enum radeon_family { + CHIP_UNKNOWN, + CHIP_R600, + CHIP_RV610, + CHIP_RV630, + CHIP_RV670, + CHIP_RV620, + CHIP_RV635, + CHIP_RS780, + CHIP_RS880, + CHIP_RV770, + CHIP_RV730, + CHIP_RV710, + CHIP_RV740, + CHIP_CEDAR, + CHIP_REDWOOD, + CHIP_JUNIPER, + CHIP_CYPRESS, + CHIP_HEMLOCK, + CHIP_PALM, + CHIP_SUMO, + CHIP_SUMO2, + CHIP_BARTS, + CHIP_TURKS, + CHIP_CAICOS, + CHIP_CAYMAN, + CHIP_ARUBA, + CHIP_TAHITI, + CHIP_PITCAIRN, + CHIP_VERDE, + CHIP_LAST, +}; + +typedef int (*hw_init_surface_t)(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf); +typedef int (*hw_best_surface_t)(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf); + +struct radeon_hw_info { + /* apply to r6, eg */ + uint32_t group_bytes; + uint32_t num_banks; + uint32_t num_pipes; + /* apply to eg */ + uint32_t row_size; + unsigned allow_2d; +}; + +struct radeon_surface_manager { + int fd; + uint32_t device_id; + struct radeon_hw_info hw_info; + unsigned family; + hw_init_surface_t surface_init; + hw_best_surface_t surface_best; +}; + +/* helper */ +static int radeon_get_value(int fd, unsigned req, uint32_t *value) +{ + struct drm_radeon_info info = {}; + int r; + + *value = 0; + info.request = req; + info.value = (uintptr_t)value; + r = drmCommandWriteRead(fd, DRM_RADEON_INFO, &info, + sizeof(struct drm_radeon_info)); + return r; +} + +static int radeon_get_family(struct radeon_surface_manager *surf_man) +{ + switch (surf_man->device_id) { +#define CHIPSET(pci_id, name, fam) case pci_id: surf_man->family = CHIP_##fam; break; +#include "r600_pci_ids.h" +#undef CHIPSET + default: + return -EINVAL; + } + return 0; +} + +static unsigned next_power_of_two(unsigned x) +{ + if (x <= 1) + return 1; + + return (1 << ((sizeof(unsigned) * 8) - __builtin_clz(x - 1))); +} + +static unsigned mip_minify(unsigned size, unsigned level) +{ + unsigned val; + + val = MAX2(1, size >> level); + if (level > 0) + val = next_power_of_two(val); + return val; +} + +static void surf_minify(struct radeon_surface *surf, + unsigned level, + uint32_t xalign, uint32_t yalign, uint32_t zalign, + unsigned offset) +{ + surf->level[level].npix_x = mip_minify(surf->npix_x, level); + surf->level[level].npix_y = mip_minify(surf->npix_y, level); + surf->level[level].npix_z = mip_minify(surf->npix_z, level); + surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; + surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; + surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; + if (surf->level[level].mode == RADEON_SURF_MODE_2D) { + if (surf->level[level].nblk_x < xalign || surf->level[level].nblk_y < yalign) { + surf->level[level].mode = RADEON_SURF_MODE_1D; + return; + } + } + surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, xalign); + surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, yalign); + surf->level[level].nblk_z = ALIGN(surf->level[level].nblk_z, zalign); + + surf->level[level].offset = offset; + surf->level[level].pitch_bytes = surf->level[level].nblk_x * surf->bpe; + surf->level[level].slice_size = surf->level[level].pitch_bytes * surf->level[level].nblk_y; + + surf->bo_size = offset + surf->level[level].slice_size * surf->level[level].nblk_z * surf->array_size; +} + +/* =========================================================================== + * r600/r700 family + */ +static int r6_init_hw_info(struct radeon_surface_manager *surf_man) +{ + uint32_t tiling_config; + drmVersionPtr version; + int r; + + r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, + &tiling_config); + if (r) { + return r; + } + + surf_man->hw_info.allow_2d = 0; + version = drmGetVersion(surf_man->fd); + if (version && version->version_minor >= 14) { + surf_man->hw_info.allow_2d = 1; + } + + switch ((tiling_config & 0xe) >> 1) { + case 0: + surf_man->hw_info.num_pipes = 1; + break; + case 1: + surf_man->hw_info.num_pipes = 2; + break; + case 2: + surf_man->hw_info.num_pipes = 4; + break; + case 3: + surf_man->hw_info.num_pipes = 8; + break; + default: + surf_man->hw_info.num_pipes = 8; + surf_man->hw_info.allow_2d = 0; + break; + } + + switch ((tiling_config & 0x30) >> 4) { + case 0: + surf_man->hw_info.num_banks = 4; + break; + case 1: + surf_man->hw_info.num_banks = 8; + break; + default: + surf_man->hw_info.num_banks = 8; + surf_man->hw_info.allow_2d = 0; + break; + } + + switch ((tiling_config & 0xc0) >> 6) { + case 0: + surf_man->hw_info.group_bytes = 256; + break; + case 1: + surf_man->hw_info.group_bytes = 512; + break; + default: + surf_man->hw_info.group_bytes = 256; + surf_man->hw_info.allow_2d = 0; + break; + } + return 0; +} + +static int r6_surface_init_linear(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf, + uint64_t offset, unsigned start_level) +{ + uint32_t xalign, yalign, zalign; + unsigned i; + + /* compute alignment */ + if (!start_level) { + surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); + } + /* the 32 alignment is for scanout, cb or db but to allow texture to be + * easily bound as such we force this alignment to all surface + */ + xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe); + yalign = 1; + zalign = 1; + if (surf->flags & RADEON_SURF_SCANOUT) { + xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); + } + + /* build mipmap tree */ + for (i = start_level; i <= surf->last_level; i++) { + surf->level[i].mode = RADEON_SURF_MODE_LINEAR; + surf_minify(surf, i, xalign, yalign, zalign, offset); + /* level0 and first mipmap need to have alignment */ + offset = surf->bo_size; + if ((i == 0)) { + offset = ALIGN(offset, surf->bo_alignment); + } + } + return 0; +} + +static int r6_surface_init_linear_aligned(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf, + uint64_t offset, unsigned start_level) +{ + uint32_t xalign, yalign, zalign; + unsigned i; + + /* compute alignment */ + if (!start_level) { + surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); + } + xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe); + yalign = 1; + zalign = 1; + + /* build mipmap tree */ + for (i = start_level; i <= surf->last_level; i++) { + surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED; + surf_minify(surf, i, xalign, yalign, zalign, offset); + /* level0 and first mipmap need to have alignment */ + offset = surf->bo_size; + if ((i == 0)) { + offset = ALIGN(offset, surf->bo_alignment); + } + } + return 0; +} + +static int r6_surface_init_1d(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf, + uint64_t offset, unsigned start_level) +{ + uint32_t xalign, yalign, zalign, tilew; + unsigned i; + + /* compute alignment */ + tilew = 8; + xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); + xalign = MAX2(tilew, xalign); + yalign = tilew; + zalign = 1; + if (surf->flags & RADEON_SURF_SCANOUT) { + xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); + } + if (!start_level) { + surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); + } + + /* build mipmap tree */ + for (i = start_level; i <= surf->last_level; i++) { + surf->level[i].mode = RADEON_SURF_MODE_1D; + surf_minify(surf, i, xalign, yalign, zalign, offset); + /* level0 and first mipmap need to have alignment */ + offset = surf->bo_size; + if ((i == 0)) { + offset = ALIGN(offset, surf->bo_alignment); + } + } + return 0; +} + +static int r6_surface_init_2d(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf, + uint64_t offset, unsigned start_level) +{ + uint32_t xalign, yalign, zalign, tilew; + unsigned i; + + /* compute alignment */ + tilew = 8; + zalign = 1; + xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) / + (tilew * surf->bpe * surf->nsamples); + xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign); + yalign = tilew * surf_man->hw_info.num_pipes; + if (surf->flags & RADEON_SURF_SCANOUT) { + xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); + } + if (!start_level) { + surf->bo_alignment = + MAX2(surf_man->hw_info.num_pipes * + surf_man->hw_info.num_banks * + surf->bpe * 64, + xalign * yalign * surf->nsamples * surf->bpe); + } + + /* build mipmap tree */ + for (i = start_level; i <= surf->last_level; i++) { + surf->level[i].mode = RADEON_SURF_MODE_2D; + surf_minify(surf, i, xalign, yalign, zalign, offset); + if (surf->level[i].mode == RADEON_SURF_MODE_1D) { + return r6_surface_init_1d(surf_man, surf, offset, i); + } + /* level0 and first mipmap need to have alignment */ + offset = surf->bo_size; + if ((i == 0)) { + offset = ALIGN(offset, surf->bo_alignment); + } + } + return 0; +} + +static int r6_surface_init(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf) +{ + unsigned mode; + int r; + + /* tiling mode */ + mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; + + /* force 1d on kernel that can't do 2d */ + if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { + mode = RADEON_SURF_MODE_1D; + surf->flags = RADEON_SURF_CLR(surf->flags, MODE); + surf->flags |= RADEON_SURF_SET(mode, MODE); + } + + /* check surface dimension */ + if (surf->npix_x > 8192 || surf->npix_y > 8192 || surf->npix_z > 8192) { + return -EINVAL; + } + + /* check mipmap last_level */ + if (surf->last_level > 14) { + return -EINVAL; + } + + /* check tiling mode */ + switch (mode) { + case RADEON_SURF_MODE_LINEAR: + r = r6_surface_init_linear(surf_man, surf, 0, 0); + break; + case RADEON_SURF_MODE_LINEAR_ALIGNED: + r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0); + break; + case RADEON_SURF_MODE_1D: + r = r6_surface_init_1d(surf_man, surf, 0, 0); + break; + case RADEON_SURF_MODE_2D: + r = r6_surface_init_2d(surf_man, surf, 0, 0); + break; + default: + return -EINVAL; + } + return r; +} + +static int r6_surface_best(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf) +{ + /* no value to optimize for r6xx/r7xx */ + return 0; +} + + +/* =========================================================================== + * evergreen family + */ +static int eg_init_hw_info(struct radeon_surface_manager *surf_man) +{ + uint32_t tiling_config; + drmVersionPtr version; + int r; + + r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, + &tiling_config); + if (r) { + return r; + } + + surf_man->hw_info.allow_2d = 0; + version = drmGetVersion(surf_man->fd); + if (version && version->version_minor >= 14) { + surf_man->hw_info.allow_2d = 1; + } + + switch (tiling_config & 0xf) { + case 0: + surf_man->hw_info.num_pipes = 1; + break; + case 1: + surf_man->hw_info.num_pipes = 2; + break; + case 2: + surf_man->hw_info.num_pipes = 4; + break; + case 3: + surf_man->hw_info.num_pipes = 8; + break; + default: + surf_man->hw_info.num_pipes = 8; + surf_man->hw_info.allow_2d = 0; + break; + } + + switch ((tiling_config & 0xf0) >> 4) { + case 0: + surf_man->hw_info.num_banks = 4; + break; + case 1: + surf_man->hw_info.num_banks = 8; + break; + case 2: + surf_man->hw_info.num_banks = 16; + break; + default: + surf_man->hw_info.num_banks = 8; + surf_man->hw_info.allow_2d = 0; + break; + } + + switch ((tiling_config & 0xf00) >> 8) { + case 0: + surf_man->hw_info.group_bytes = 256; + break; + case 1: + surf_man->hw_info.group_bytes = 512; + break; + default: + surf_man->hw_info.group_bytes = 256; + surf_man->hw_info.allow_2d = 0; + break; + } + + switch ((tiling_config & 0xf000) >> 12) { + case 0: + surf_man->hw_info.row_size = 1024; + break; + case 1: + surf_man->hw_info.row_size = 2048; + break; + case 2: + surf_man->hw_info.row_size = 4096; + break; + default: + surf_man->hw_info.row_size = 4096; + surf_man->hw_info.allow_2d = 0; + break; + } + return 0; +} + +static void eg_surf_minify(struct radeon_surface *surf, + unsigned level, + unsigned slice_pt, + unsigned mtilew, + unsigned mtileh, + unsigned mtileb, + unsigned offset) +{ + unsigned mtile_pr, mtile_ps; + + surf->level[level].npix_x = mip_minify(surf->npix_x, level); + surf->level[level].npix_y = mip_minify(surf->npix_y, level); + surf->level[level].npix_z = mip_minify(surf->npix_z, level); + surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; + surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; + surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; + if (surf->level[level].mode == RADEON_SURF_MODE_2D) { + if (surf->level[level].nblk_x < mtilew || surf->level[level].nblk_y < mtileh) { + surf->level[level].mode = RADEON_SURF_MODE_1D; + return; + } + } + surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, mtilew); + surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, mtileh); + surf->level[level].nblk_z = ALIGN(surf->level[level].nblk_z, 1); + + /* macro tile per row */ + mtile_pr = surf->level[level].nblk_x / mtilew; + /* macro tile per slice */ + mtile_ps = (mtile_pr * surf->level[level].nblk_y) / mtileh; + + surf->level[level].offset = offset; + surf->level[level].pitch_bytes = surf->level[level].nblk_x * surf->bpe * slice_pt; + surf->level[level].slice_size = mtile_ps * mtileb * slice_pt; + + surf->bo_size = offset + surf->level[level].slice_size * surf->level[level].nblk_z * surf->array_size; +} + +static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf, + uint64_t offset, unsigned start_level) +{ + uint32_t xalign, yalign, zalign, tilew; + unsigned i; + + /* compute alignment */ + tilew = 8; + xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); + if (surf->flags & RADEON_SURF_SBUFFER) { + surf->stencil_offset = 0; + surf->stencil_tile_split = 0; + xalign = surf_man->hw_info.group_bytes / (tilew * surf->nsamples); + } + xalign = MAX2(tilew, xalign); + yalign = tilew; + zalign = 1; + if (surf->flags & RADEON_SURF_SCANOUT) { + xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); + } + if (!start_level) { + surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); + } + + /* build mipmap tree */ + for (i = start_level; i <= surf->last_level; i++) { + surf->level[i].mode = RADEON_SURF_MODE_1D; + surf_minify(surf, i, xalign, yalign, zalign, offset); + /* level0 and first mipmap need to have alignment */ + offset = surf->bo_size; + if ((i == 0)) { + offset = ALIGN(offset, surf->bo_alignment); + } + } + + if (surf->flags & RADEON_SURF_SBUFFER) { + surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); + surf->bo_size = surf->stencil_offset + surf->bo_size / 4; + } + + return 0; +} + +static int eg_surface_init_2d(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf, + uint64_t offset, unsigned start_level) +{ + unsigned tilew, tileh, tileb; + unsigned mtilew, mtileh, mtileb; + unsigned slice_pt; + unsigned i; + + surf->stencil_offset = 0; + /* compute tile values */ + tilew = 8; + tileh = 8; + tileb = tilew * tileh * surf->bpe * surf->nsamples; + /* slices per tile */ + slice_pt = 1; + if (tileb > surf->tile_split) { + slice_pt = tileb / surf->tile_split; + } + tileb = tileb / slice_pt; + + /* macro tile width & height */ + mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea; + mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea; + /* macro tile bytes */ + mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb; + + if (!start_level) { + surf->bo_alignment = MAX2(256, mtileb); + } + + /* build mipmap tree */ + for (i = start_level; i <= surf->last_level; i++) { + surf->level[i].mode = RADEON_SURF_MODE_2D; + eg_surf_minify(surf, i, slice_pt, mtilew, mtileh, mtileb, offset); + if (surf->level[i].mode == RADEON_SURF_MODE_1D) { + return eg_surface_init_1d(surf_man, surf, offset, i); + } + /* level0 and first mipmap need to have alignment */ + offset = surf->bo_size; + if ((i == 0)) { + offset = ALIGN(offset, surf->bo_alignment); + } + } + + if (surf->flags & RADEON_SURF_SBUFFER) { + surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment); + surf->bo_size = surf->stencil_offset + surf->bo_size / 4; + } + + return 0; +} + +static int eg_surface_sanity(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf, + unsigned mode) +{ + unsigned tileb; + + /* check surface dimension */ + if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) { + return -EINVAL; + } + + /* check mipmap last_level */ + if (surf->last_level > 15) { + return -EINVAL; + } + + /* force 1d on kernel that can't do 2d */ + if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { + mode = RADEON_SURF_MODE_1D; + surf->flags = RADEON_SURF_CLR(surf->flags, MODE); + surf->flags |= RADEON_SURF_SET(mode, MODE); + } + + /* check tile split */ + if (mode == RADEON_SURF_MODE_2D) { + switch (surf->tile_split) { + case 64: + case 128: + case 256: + case 512: + case 1024: + case 2048: + case 4096: + break; + default: + return -EINVAL; + } + switch (surf->mtilea) { + case 1: + case 2: + case 4: + case 8: + break; + default: + return -EINVAL; + } + /* check aspect ratio */ + if (surf_man->hw_info.num_banks < surf->mtilea) { + return -EINVAL; + } + /* check bank width */ + switch (surf->bankw) { + case 1: + case 2: + case 4: + case 8: + break; + default: + return -EINVAL; + } + /* check bank height */ + switch (surf->bankh) { + case 1: + case 2: + case 4: + case 8: + break; + default: + return -EINVAL; + } + tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples); + if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) { + return -EINVAL; + } + } + + return 0; +} + +static int eg_surface_init(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf) +{ + unsigned mode; + int r; + + /* tiling mode */ + mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; + + /* for some reason eg need to have room for stencil right after depth */ + if (surf->flags & RADEON_SURF_ZBUFFER) { + surf->flags |= RADEON_SURF_SBUFFER; + } + + r = eg_surface_sanity(surf_man, surf, mode); + if (r) { + return r; + } + + /* check tiling mode */ + switch (mode) { + case RADEON_SURF_MODE_LINEAR: + r = r6_surface_init_linear(surf_man, surf, 0, 0); + break; + case RADEON_SURF_MODE_LINEAR_ALIGNED: + r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0); + break; + case RADEON_SURF_MODE_1D: + r = eg_surface_init_1d(surf_man, surf, 0, 0); + break; + case RADEON_SURF_MODE_2D: + r = eg_surface_init_2d(surf_man, surf, 0, 0); + break; + default: + return -EINVAL; + } + return r; +} + +static unsigned log2_int(unsigned x) +{ + unsigned l; + + if (x < 2) { + return 0; + } + for (l = 2; ; l++) { + if ((unsigned)(1 << l) > x) { + return l - 1; + } + } + return 0; +} + +/* compute best tile_split, bankw, bankh, mtilea + * depending on surface + */ +static int eg_surface_best(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf) +{ + unsigned mode, tileb, h_over_w; + int r; + + /* tiling mode */ + mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; + + /* for some reason eg need to have room for stencil right after depth */ + if (surf->flags & RADEON_SURF_ZBUFFER) { + surf->flags |= RADEON_SURF_SBUFFER; + } + + /* set some default value to avoid sanity check choking on them */ + surf->tile_split = 1024; + surf->bankw = 1; + surf->bankh = 1; + surf->mtilea = surf_man->hw_info.num_banks; + tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples); + for (; surf->bankh <= 8; surf->bankh *= 2) { + if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { + break; + } + } + if (surf->mtilea > 8) { + surf->mtilea = 8; + } + + r = eg_surface_sanity(surf_man, surf, mode); + if (r) { + return r; + } + + if (mode != RADEON_SURF_MODE_2D) { + /* nothing to do for non 2D tiled surface */ + return 0; + } + + /* set tile split to row size, optimize latter for multi-sample surface + * tile split >= 256 for render buffer surface. Also depth surface want + * smaller value for optimal performances. + */ + surf->tile_split = surf_man->hw_info.row_size; + surf->stencil_tile_split = surf_man->hw_info.row_size / 2; + + /* bankw or bankh greater than 1 increase alignment requirement, not + * sure if it's worth using smaller bankw & bankh to stick with 2D + * tiling on small surface rather than falling back to 1D tiling. + * Use recommanded value based on tile size for now. + * + * fmask buffer has different optimal value figure them out once we + * use it. + */ + if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { + /* assume 1 bytes for stencil, we optimize for stencil as stencil + * and depth shares surface values + */ + tileb = MIN2(surf->tile_split, 64 * surf->nsamples); + } else { + tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples); + } + + /* use bankw of 1 to minimize width alignment, might be interesting to + * increase it for large surface + */ + surf->bankw = 1; + switch (tileb) { + case 64: + surf->bankh = 4; + break; + case 128: + case 256: + surf->bankh = 2; + break; + default: + surf->bankh = 1; + break; + } + /* double check the constraint */ + for (; surf->bankh <= 8; surf->bankh *= 2) { + if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { + break; + } + } + + h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) / + (surf->bankw * surf_man->hw_info.num_pipes)) >> 16; + surf->mtilea = 1 << (log2_int(h_over_w) >> 1); + + return 0; +} + + +/* =========================================================================== + * public API + */ +struct radeon_surface_manager *radeon_surface_manager_new(int fd) +{ + struct radeon_surface_manager *surf_man; + + surf_man = calloc(1, sizeof(struct radeon_surface_manager)); + if (surf_man == NULL) { + return NULL; + } + surf_man->fd = fd; + if (radeon_get_value(fd, RADEON_INFO_DEVICE_ID, &surf_man->device_id)) { + goto out_err; + } + if (radeon_get_family(surf_man)) { + goto out_err; + } + + if (surf_man->family <= CHIP_RV740) { + if (r6_init_hw_info(surf_man)) { + goto out_err; + } + surf_man->surface_init = &r6_surface_init; + surf_man->surface_best = &r6_surface_best; + } else { + if (eg_init_hw_info(surf_man)) { + goto out_err; + } + surf_man->surface_init = &eg_surface_init; + surf_man->surface_best = &eg_surface_best; + } + + return surf_man; +out_err: + free(surf_man); + return NULL; +} + +void radeon_surface_manager_free(struct radeon_surface_manager *surf_man) +{ + free(surf_man); +} + +static int radeon_surface_sanity(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf, + unsigned type, + unsigned mode) +{ + if (surf_man == NULL || surf_man->surface_init == NULL || surf == NULL) { + return -EINVAL; + } + + /* all dimension must be at least 1 ! */ + if (!surf->npix_x || !surf->npix_y || !surf->npix_z) { + return -EINVAL; + } + if (!surf->blk_w || !surf->blk_h || !surf->blk_d) { + return -EINVAL; + } + if (!surf->array_size) { + return -EINVAL; + } + /* array size must be a power of 2 */ + surf->array_size = next_power_of_two(surf->array_size); + + switch (surf->nsamples) { + case 1: + case 2: + case 4: + case 8: + break; + default: + return -EINVAL; + } + /* check type */ + switch (type) { + case RADEON_SURF_TYPE_1D: + if (surf->npix_y > 1) { + return -EINVAL; + } + case RADEON_SURF_TYPE_2D: + if (surf->npix_z > 1) { + return -EINVAL; + } + break; + case RADEON_SURF_TYPE_CUBEMAP: + if (surf->npix_z > 1) { + return -EINVAL; + } + /* deal with cubemap as they were texture array */ + if (surf_man->family >= CHIP_RV770) { + surf->array_size = 8; + } else { + surf->array_size = 6; + } + break; + case RADEON_SURF_TYPE_3D: + break; + case RADEON_SURF_TYPE_1D_ARRAY: + if (surf->npix_y > 1) { + return -EINVAL; + } + case RADEON_SURF_TYPE_2D_ARRAY: + break; + default: + return -EINVAL; + } + return 0; +} + +int radeon_surface_init(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf) +{ + unsigned mode, type; + int r; + + type = RADEON_SURF_GET(surf->flags, TYPE); + mode = RADEON_SURF_GET(surf->flags, MODE); + + r = radeon_surface_sanity(surf_man, surf, type, mode); + if (r) { + return r; + } + return surf_man->surface_init(surf_man, surf); +} + +int radeon_surface_best(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf) +{ + unsigned mode, type; + int r; + + type = RADEON_SURF_GET(surf->flags, TYPE); + mode = RADEON_SURF_GET(surf->flags, MODE); + + r = radeon_surface_sanity(surf_man, surf, type, mode); + if (r) { + return r; + } + return surf_man->surface_best(surf_man, surf); +} diff --git a/radeon/radeon_surface.h b/radeon/radeon_surface.h new file mode 100644 index 0000000..bfee8ab --- /dev/null +++ b/radeon/radeon_surface.h @@ -0,0 +1,114 @@ +/* + * Copyright © 2011 Red Hat All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS + * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + */ +/* + * Authors: + * Jérôme Glisse + */ +#ifndef RADEON_SURFACE_H +#define RADEON_SURFACE_H + +/* Note : + * + * For texture array, the n layer are stored one after the other within each + * mipmap level. 0 value for field than can be hint is always valid. + */ + +#define RADEON_SURF_MAX_LEVEL 32 + +#define RADEON_SURF_TYPE_MASK 0xFF +#define RADEON_SURF_TYPE_SHIFT 0 +#define RADEON_SURF_TYPE_1D 0 +#define RADEON_SURF_TYPE_2D 1 +#define RADEON_SURF_TYPE_3D 2 +#define RADEON_SURF_TYPE_CUBEMAP 3 +#define RADEON_SURF_TYPE_1D_ARRAY 4 +#define RADEON_SURF_TYPE_2D_ARRAY 5 +#define RADEON_SURF_MODE_MASK 0xFF +#define RADEON_SURF_MODE_SHIFT 8 +#define RADEON_SURF_MODE_LINEAR 0 +#define RADEON_SURF_MODE_LINEAR_ALIGNED 1 +#define RADEON_SURF_MODE_1D 2 +#define RADEON_SURF_MODE_2D 3 +#define RADEON_SURF_SCANOUT (1 << 16) +#define RADEON_SURF_ZBUFFER (1 << 17) +#define RADEON_SURF_SBUFFER (1 << 18) + +#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK) +#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) +#define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT)) + +/* first field up to mode need to match r6 struct so that we can reuse + * same function for linear & linear aligned + */ +struct radeon_surface_level { + uint64_t offset; + uint64_t slice_size; + uint32_t npix_x; + uint32_t npix_y; + uint32_t npix_z; + uint32_t nblk_x; + uint32_t nblk_y; + uint32_t nblk_z; + uint32_t pitch_bytes; + uint32_t mode; +}; + +struct radeon_surface { + uint32_t npix_x; + uint32_t npix_y; + uint32_t npix_z; + uint32_t blk_w; + uint32_t blk_h; + uint32_t blk_d; + uint32_t array_size; + uint32_t last_level; + uint32_t bpe; + uint32_t nsamples; + uint32_t flags; + /* Following is updated/fill by the allocator. It's allowed to + * set some of the value but they are use as hint and can be + * overridden (things lile bankw/bankh on evergreen for + * instance). + */ + uint64_t bo_size; + uint64_t bo_alignment; + /* apply to eg */ + uint32_t bankw; + uint32_t bankh; + uint32_t mtilea; + uint32_t tile_split; + uint32_t stencil_tile_split; + uint64_t stencil_offset; + struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL]; +}; + +struct radeon_surface_manager *radeon_surface_manager_new(int fd); +void radeon_surface_manager_free(struct radeon_surface_manager *surf_man); +int radeon_surface_init(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf); +int radeon_surface_best(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf); + +#endif diff --git a/slp/Makefile.am b/slp/Makefile.am new file mode 100644 index 0000000..132662b --- /dev/null +++ b/slp/Makefile.am @@ -0,0 +1,22 @@ +SUBDIRS = . + +AM_CFLAGS = \ + $(WARN_CFLAGS) \ + -I$(top_srcdir) \ + -I$(top_srcdir)/slp \ + $(PTHREADSTUBS_CFLAGS) \ + -I$(top_srcdir)/include/drm + +libdrm_slp_la_LTLIBRARIES = libdrm_slp.la +libdrm_slp_ladir = $(libdir) +libdrm_slp_la_LDFLAGS = -version-number 1:0:0 -no-undefined +libdrm_slp_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@ @CLOCK_LIB@ -ldl + +libdrm_slp_la_SOURCES = \ + drm_slp_bufmgr.c \ + drm_slp_bufmgr.h + +libdrm_slpincludedir = ${includedir}/libdrm +libdrm_slpinclude_HEADERS = drm_slp_bufmgr.h + +pkgconfig_DATA = libdrm_slp.pc diff --git a/slp/drm_slp_bufmgr.c b/slp/drm_slp_bufmgr.c new file mode 100644 index 0000000..a4e17a4 --- /dev/null +++ b/slp/drm_slp_bufmgr.c @@ -0,0 +1,850 @@ +/************************************************************************** + +xserver-xorg-video-sec + +Copyright 2011 Samsung Electronics co., Ltd. All Rights Reserved. + +Contact: SooChan Lim , Sangjin Lee + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +#include "config.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "drm_slp_bufmgr.h" +#include "list.h" + +#define PREFIX_LIB "libdrm_slp_" +#define SUFFIX_LIB ".so" +#define DEFAULT_LIB PREFIX_LIB"default"SUFFIX_LIB + +#define NUM_TRY_LOCK 10 +#define SEM_NAME "pixmap_1" +#define SEM_DEBUG 0 + +#define DRM_RETURN_IF_FAIL(cond) {if (!(cond)) { fprintf (stderr, "[%s] : '%s' failed.\n", __FUNCTION__, #cond); return; }} +#define DRM_RETURN_VAL_IF_FAIL(cond, val) {if (!(cond)) { fprintf (stderr, "[%s] : '%s' failed.\n", __FUNCTION__, #cond); return val; }} + +#define MGR_IS_VALID(mgr) (mgr && \ + mgr->link.next && \ + mgr->link.next->prev == &mgr->link) +#define BO_IS_VALID(bo) (bo && \ + MGR_IS_VALID(bo->bufmgr) && \ + bo->list.next && \ + bo->list.next->prev == &bo->list) + +typedef struct{ + void* data; + + int is_valid; + drm_data_free free_func ; +}drm_slp_user_data; + +static struct list_head *gBufMgrs = NULL; + +static int +_sem_wait_wrapper(sem_t* sem) +{ + int res = 0; + int num_try = NUM_TRY_LOCK; + + do + { + res = sem_wait(sem); + num_try--; + } while((res == -1) && (errno == EINTR) && (num_try >= 0)); + + if(res == -1) + { + fprintf(stderr, + "[libdrm] error %s:%d(sem:%p, num_try:%d) PID:%04d\n", + __FUNCTION__, + __LINE__, + sem, + num_try, + getpid()); + return 0; + } +#if SEM_DEBUG + else + { + fprintf(stderr, + "[libdrm] LOCK >> %s:%d(sem:%p, num_try:%d) PID:%04d\n", + __FUNCTION__, + __LINE__, + sem, + num_try, + getpid()); + } +#endif + + return 1; +} + +static int +_sem_post_wrapper(sem_t* sem) +{ + int res = 0; + int num_try = NUM_TRY_LOCK; + + do + { + res = sem_post(sem); + num_try--; + + } while((res == -1) && (errno == EINTR) && (num_try >= 0)); + + if(res == -1) + { + fprintf(stderr, + "[libdrm] error %s:%d(sem:%p, num_try:%d) PID:%04d\n", + __FUNCTION__, + __LINE__, + sem, + num_try, + getpid()); + return 0; + } +#if SEM_DEBUG + else + { + fprintf(stderr, + "[libdrm] UNLOCK << %s:%d(sem:%p, num_try:%d) PID:%04d\n", + __FUNCTION__, + __LINE__, + sem, + num_try, + getpid()); + } +#endif + + return 1; +} + +static int +_sem_open(drm_slp_bufmgr bufmgr) +{ + bufmgr->semObj.handle = sem_open(SEM_NAME, O_CREAT, 0777, 1); + if(bufmgr->semObj.handle == SEM_FAILED) + { + fprintf(stderr, + "[libdrm] error %s:%d(name:%s) PID:%04d\n", + __FUNCTION__, + __LINE__, + SEM_NAME, + getpid()); + bufmgr->semObj.handle = NULL; + return 0; + } +#if SEM_DEBUG + else + { + fprintf(stderr, + "[libdrm] OPEN %s:%d(sem:%p) PID:%04d\n", + __FUNCTION__, + __LINE__, + bufmgr->semObj.handle, + getpid()); + } +#endif + + bufmgr->semObj.status = STATUS_UNLOCK; + + return 1; +} + +static int +_sem_close(drm_slp_bufmgr bufmgr) +{ + _sem_wait_wrapper(bufmgr->semObj.handle); + sem_unlink(SEM_NAME); + return 1; +} + +static int +_sem_lock(drm_slp_bufmgr bufmgr) +{ + if(bufmgr->semObj.status != STATUS_UNLOCK) return 0; + + if(!_sem_wait_wrapper(bufmgr->semObj.handle)) return 0; + bufmgr->semObj.status = STATUS_LOCK; + return 1; +} + +static int +_sem_unlock(drm_slp_bufmgr bufmgr) +{ + if(bufmgr->semObj.status != STATUS_LOCK) return 0; + + _sem_post_wrapper(bufmgr->semObj.handle); + bufmgr->semObj.status = STATUS_UNLOCK; + return 1; +} + +static drm_slp_bufmgr +_load_bufmgr(int fd, const char *file, void *arg) +{ + char path[PATH_MAX] = {0,}; + drm_slp_bufmgr bufmgr = NULL; + int (*bufmgr_init)(drm_slp_bufmgr bufmgr, int fd, void *arg); + void *module; + + snprintf(path, sizeof(path), BUFMGR_DIR "/%s", file); + + module = dlopen(path, RTLD_LAZY); + if (!module) { + fprintf(stderr, + "[libdrm] failed to load module: %s(%s)\n", + dlerror(), file); + return NULL; + } + + bufmgr_init = dlsym(module, "init_slp_bufmgr"); + if (!bufmgr_init) { + fprintf(stderr, + "[libdrm] failed to lookup init function: %s(%s)\n", + dlerror(), file); + return NULL; + } + + bufmgr = calloc(sizeof(struct _drm_slp_bufmgr), 1); + if(!bufmgr) + { + return NULL; + } + + if(!bufmgr_init(bufmgr, fd, arg)) + { + fprintf(stderr,"[libdrm] Fail to init module(%s)\n", file); + free(bufmgr); + bufmgr = NULL; + return NULL; + } + + fprintf(stderr,"[libdrm] Success to load module(%s)\n", file); + + return bufmgr; +} + +drm_slp_bufmgr +drm_slp_bufmgr_init(int fd, void *arg) +{ + drm_slp_bufmgr bufmgr = NULL; + const char *p = NULL; + + if (fd < 0) + return NULL; + + if(gBufMgrs == NULL) + { + gBufMgrs = malloc(sizeof(struct list_head)); + LIST_INITHEAD(gBufMgrs); + } + else + { + LIST_FOR_EACH_ENTRY(bufmgr, gBufMgrs, link) + { + if(bufmgr->drm_fd == fd) + { + bufmgr->ref_count++; + fprintf(stderr, "[libdrm] bufmgr ref: fd=%d, ref_count:%d\n", fd, bufmgr->ref_count); + return bufmgr; + } + } + bufmgr = NULL; + } + fprintf(stderr, "[libdrm] bufmgr init: fd=%d\n", fd); + + p = getenv ("SLP_BUFMGR_MODULE"); + if (p) + { + char file[PATH_MAX] = {0,}; + snprintf(file, sizeof(file), PREFIX_LIB"%s"SUFFIX_LIB, p); + bufmgr = _load_bufmgr (fd, file, arg); + } + + if (!bufmgr) + bufmgr = _load_bufmgr (fd, DEFAULT_LIB, arg); + + if (!bufmgr) + { + struct dirent **namelist; + int found = 0; + int n; + + n = scandir(BUFMGR_DIR, &namelist, 0, alphasort); + if (n < 0) + fprintf(stderr,"[libdrm] no files : %s\n", BUFMGR_DIR); + else + { + while(n--) + { + if (!found && strstr (namelist[n]->d_name, PREFIX_LIB)) + { + char *p = strstr (namelist[n]->d_name, SUFFIX_LIB); + if (!strcmp (p, SUFFIX_LIB)) + { + bufmgr = _load_bufmgr (fd, namelist[n]->d_name, arg); + if (bufmgr) + found = 1; + } + } + free(namelist[n]); + } + free(namelist); + } + } + + if (!bufmgr) + { + fprintf(stderr,"[libdrm] backend is NULL.\n"); + return NULL; + } + + if (pthread_mutex_init(&bufmgr->lock, NULL) != 0) + { + bufmgr->bufmgr_destroy(bufmgr); + free(bufmgr); + return NULL; + } + + bufmgr->ref_count = 1; + bufmgr->drm_fd = fd; + + LIST_INITHEAD(&bufmgr->bos); + LIST_ADD(&bufmgr->link, gBufMgrs); + + return bufmgr; +} + +void +drm_slp_bufmgr_destroy(drm_slp_bufmgr bufmgr) +{ + DRM_RETURN_IF_FAIL(MGR_IS_VALID(bufmgr)); + + fprintf(stderr, "[DRM] bufmgr destroy: bufmgr:%p, drm_fd:%d\n", + bufmgr, bufmgr->drm_fd); + + /*Check and Free bos*/ + if(!LIST_IS_EMPTY(&bufmgr->bos)) + { + drm_slp_bo bo, tmp; + + LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &bufmgr->bos, list) + { + fprintf(stderr, "[libdrm] Un-freed bo(%p, ref:%d) \n", bo, bo->ref_cnt); + bo->ref_cnt = 1; + drm_slp_bo_unref(bo); + } + } + + LIST_DEL(&bufmgr->link); + bufmgr->bufmgr_destroy(bufmgr); + + if(bufmgr->semObj.isOpened) + { + _sem_close(bufmgr); + } + + pthread_mutex_destroy(&bufmgr->lock); + free(bufmgr); +} + +int +drm_slp_bufmgr_lock(drm_slp_bufmgr bufmgr) +{ + DRM_RETURN_VAL_IF_FAIL(MGR_IS_VALID(bufmgr), 0); + + pthread_mutex_lock(&bufmgr->lock); + + if(bufmgr->bufmgr_lock) + { + int ret; + ret = bufmgr->bufmgr_lock(bufmgr); + pthread_mutex_unlock(&bufmgr->lock); + return ret; + } + + if(!bufmgr->semObj.isOpened) + { + if(_sem_open(bufmgr) != 1) + { + pthread_mutex_unlock(&bufmgr->lock); + return 0; + } + bufmgr->semObj.isOpened = 1; + } + + if(_sem_lock(bufmgr) != 1) + { + pthread_mutex_unlock(&bufmgr->lock); + return 0; + } + + pthread_mutex_unlock(&bufmgr->lock); + + return 1; +} + +int +drm_slp_bufmgr_unlock(drm_slp_bufmgr bufmgr) +{ + DRM_RETURN_VAL_IF_FAIL(MGR_IS_VALID(bufmgr), 0); + + pthread_mutex_lock(&bufmgr->lock); + + if(bufmgr->bufmgr_unlock) + { + int ret; + ret = bufmgr->bufmgr_unlock(bufmgr); + pthread_mutex_unlock(&bufmgr->lock); + return ret; + } + + if(_sem_unlock(bufmgr) != 1) + { + pthread_mutex_unlock(&bufmgr->lock); + return 0; + } + + pthread_mutex_unlock(&bufmgr->lock); + + return 1; +} + +int +drm_slp_bufmgr_cache_flush(drm_slp_bufmgr bufmgr, drm_slp_bo bo, int flags) +{ + int ret; + + DRM_RETURN_VAL_IF_FAIL(MGR_IS_VALID(bufmgr) || BO_IS_VALID(bo), 0); + + if (!bo) + flags |= DRM_SLP_CACHE_ALL; + + if (bo) + { + DRM_RETURN_VAL_IF_FAIL(BO_IS_VALID(bo), 0); + + if(!bo->bufmgr) + return 0; + + pthread_mutex_lock(&bo->bufmgr->lock); + ret = bo->bufmgr->bufmgr_cache_flush(bufmgr, bo, flags); + pthread_mutex_unlock(&bo->bufmgr->lock); + } + else + { + pthread_mutex_lock(&bufmgr->lock); + ret = bufmgr->bufmgr_cache_flush(bufmgr, NULL, flags); + pthread_mutex_unlock(&bufmgr->lock); + } + + return ret; +} + +int +drm_slp_bo_size(drm_slp_bo bo) +{ + int size; + drm_slp_bufmgr bufmgr; + + DRM_RETURN_VAL_IF_FAIL(BO_IS_VALID(bo), 0); + + bufmgr = bo->bufmgr; + + pthread_mutex_lock(&bufmgr->lock); + size = bo->bufmgr->bo_size(bo); + pthread_mutex_unlock(&bufmgr->lock); + + return size; +} + +drm_slp_bo +drm_slp_bo_ref(drm_slp_bo bo) +{ + drm_slp_bufmgr bufmgr; + + DRM_RETURN_VAL_IF_FAIL(BO_IS_VALID(bo), NULL); + + bufmgr = bo->bufmgr; + + pthread_mutex_lock(&bufmgr->lock); + + bo->ref_cnt++; + + pthread_mutex_unlock(&bufmgr->lock); + + return bo; +} + +void +drm_slp_bo_unref(drm_slp_bo bo) +{ + drm_slp_bufmgr bufmgr; + + DRM_RETURN_IF_FAIL(BO_IS_VALID(bo)); + + bufmgr = bo->bufmgr; + + if(0 >= bo->ref_cnt) + return; + + pthread_mutex_lock(&bufmgr->lock); + + bo->ref_cnt--; + if(bo->ref_cnt == 0) + { + if(bo->user_data) + { + void* rd; + drm_slp_user_data* old_data; + unsigned long key; + + while(1==drmSLFirst(bo->user_data, &key, &rd)) + { + old_data = (drm_slp_user_data*)rd; + + if(old_data->is_valid && old_data->free_func) + { + if(old_data->data) + old_data->free_func(old_data->data); + old_data->data = NULL; + free(old_data); + } + drmSLDelete(bo->user_data, key); + } + + drmSLDestroy(bo->user_data); + bo->user_data = (void*)0; + } + + LIST_DEL(&bo->list); + bufmgr->bo_free(bo); + + free(bo); + } + + pthread_mutex_unlock(&bufmgr->lock); +} + +drm_slp_bo +drm_slp_bo_alloc(drm_slp_bufmgr bufmgr, const char * name, int size, int flags) +{ + drm_slp_bo bo=NULL; + + DRM_RETURN_VAL_IF_FAIL( MGR_IS_VALID(bufmgr) && (size > 0), NULL); + + bo = calloc(sizeof(struct _drm_slp_bo), 1); + if(!bo) + return NULL; + + bo->bufmgr = bufmgr; + + pthread_mutex_lock(&bufmgr->lock); + if(!bufmgr->bo_alloc(bo, name, size, flags)) + { + free(bo); + pthread_mutex_unlock(&bufmgr->lock); + return NULL; + } + bo->ref_cnt = 1; + LIST_ADD(&bo->list, &bufmgr->bos); + pthread_mutex_unlock(&bufmgr->lock); + + return bo; +} + +drm_slp_bo +drm_slp_bo_attach(drm_slp_bufmgr bufmgr, + const char* name, + int type, + int size, + unsigned int handle) +{ + drm_slp_bo bo; + + DRM_RETURN_VAL_IF_FAIL(MGR_IS_VALID(bufmgr), NULL); + + bo = calloc(sizeof(struct _drm_slp_bo), 1); + if(!bo) + return NULL; + + bo->bufmgr = bufmgr; + + pthread_mutex_lock(&bufmgr->lock); + if(!bufmgr->bo_attach(bo, name, type, size, handle)) + { + free(bo); + pthread_mutex_unlock(&bufmgr->lock); + return NULL; + } + bo->ref_cnt = 1; + LIST_ADD(&bo->list, &bufmgr->bos); + pthread_mutex_unlock(&bufmgr->lock); + + return bo; +} + +drm_slp_bo +drm_slp_bo_import(drm_slp_bufmgr bufmgr, unsigned int key) +{ + drm_slp_bo bo; + + DRM_RETURN_VAL_IF_FAIL(MGR_IS_VALID(bufmgr), NULL); + + bo = calloc(sizeof(struct _drm_slp_bo), 1); + if(!bo) + return NULL; + + bo->bufmgr = bufmgr; + + pthread_mutex_lock(&bufmgr->lock); + if(!bufmgr->bo_import(bo, key)) + { + free(bo); + pthread_mutex_unlock(&bufmgr->lock); + return NULL; + } + bo->ref_cnt = 1; + LIST_ADD(&bo->list, &bufmgr->bos); + pthread_mutex_unlock(&bufmgr->lock); + + return bo; +} + +unsigned int +drm_slp_bo_export(drm_slp_bo bo) +{ + int ret; + + DRM_RETURN_VAL_IF_FAIL(BO_IS_VALID(bo), 0); + + pthread_mutex_lock(&bo->bufmgr->lock); + ret = bo->bufmgr->bo_export(bo); + pthread_mutex_unlock(&bo->bufmgr->lock); + + return ret; +} + +unsigned int +drm_slp_bo_get_handle(drm_slp_bo bo, int device) +{ + unsigned int ret; + + DRM_RETURN_VAL_IF_FAIL(BO_IS_VALID(bo), 0); + + pthread_mutex_lock(&bo->bufmgr->lock); + ret = bo->bufmgr->bo_get_handle(bo, device); + pthread_mutex_unlock(&bo->bufmgr->lock); + + return ret; +} + +unsigned int +drm_slp_bo_map(drm_slp_bo bo, int device, int opt) +{ + unsigned int ret; + + DRM_RETURN_VAL_IF_FAIL(BO_IS_VALID(bo), 0); + + pthread_mutex_lock(&bo->bufmgr->lock); + if(bo->bufmgr->bo_lock) + { + bo->bufmgr->bo_lock(bo, 0, (void*)0); + } + + ret = bo->bufmgr->bo_map(bo, device, opt); + pthread_mutex_unlock(&bo->bufmgr->lock); + + return ret; +} + +int +drm_slp_bo_unmap(drm_slp_bo bo, int device) +{ + int ret; + + DRM_RETURN_VAL_IF_FAIL(BO_IS_VALID(bo), 0); + + pthread_mutex_lock(&bo->bufmgr->lock); + ret = bo->bufmgr->bo_unmap(bo, device); + + if(bo->bufmgr->bo_unlock) + { + bo->bufmgr->bo_unlock(bo); + } + pthread_mutex_unlock(&bo->bufmgr->lock); + + return 0; +} + +int +drm_slp_bo_swap(drm_slp_bo bo1, drm_slp_bo bo2) +{ + void* temp; + + DRM_RETURN_VAL_IF_FAIL(BO_IS_VALID(bo1), 0); + DRM_RETURN_VAL_IF_FAIL(BO_IS_VALID(bo2), 0); + + if(bo1->bufmgr->bo_size(bo1) != bo2->bufmgr->bo_size(bo2)) + return 0; + + pthread_mutex_lock(&bo1->bufmgr->lock); + temp = bo1->priv; + bo1->priv = bo2->priv; + bo2->priv = temp; + pthread_mutex_unlock(&bo1->bufmgr->lock); + + return 1; +} + +int +drm_slp_bo_add_user_data(drm_slp_bo bo, unsigned long key, drm_data_free data_free_func) +{ + int ret; + drm_slp_user_data* data; + + DRM_RETURN_VAL_IF_FAIL(BO_IS_VALID(bo), 0); + + if(!bo->user_data) + bo->user_data = drmSLCreate(); + + data = calloc(1, sizeof(drm_slp_user_data)); + if(!data) + return 0; + + data->free_func = data_free_func; + data->data = (void*)0; + data->is_valid = 0; + + ret = drmSLInsert(bo->user_data, key, data); + if(ret == 1) /* Already in list */ + { + free(data); + return 0; + } + + return 1; +} + +int +drm_slp_bo_set_user_data(drm_slp_bo bo, unsigned long key, void* data) +{ + void *rd; + drm_slp_user_data* old_data; + + DRM_RETURN_VAL_IF_FAIL(BO_IS_VALID(bo), 0); + + if(!bo->user_data) + return 0; + + if(drmSLLookup(bo->user_data, key, &rd)) + return 0; + + old_data = (drm_slp_user_data*)rd; + if (!old_data) + return 0; + + if(old_data->is_valid) + { + if(old_data->free_func) + { + if(old_data->data) + old_data->free_func(old_data->data); + old_data->data = NULL; + } + } + else + old_data->is_valid = 1; + + old_data->data = data; + + return 1; +} + +int +drm_slp_bo_get_user_data(drm_slp_bo bo, unsigned long key, void** data) +{ + void *rd; + drm_slp_user_data* old_data; + + DRM_RETURN_VAL_IF_FAIL(BO_IS_VALID(bo), 0); + + if (!data || !bo->user_data) + return 0; + + if(drmSLLookup(bo->user_data, key, &rd)) + { + *data = NULL; + return 0; + } + + old_data = (drm_slp_user_data*)rd; + if (!old_data) + { + *data = NULL; + return 0; + } + + *data = old_data->data; + + return 1; +} + +int +drm_slp_bo_delete_user_data(drm_slp_bo bo, unsigned long key) +{ + void *rd; + drm_slp_user_data* old_data=(void*)0; + + DRM_RETURN_VAL_IF_FAIL(BO_IS_VALID(bo) && bo->user_data, 0); + + if(drmSLLookup(bo->user_data, key, &rd)) + return 0; + + old_data = (drm_slp_user_data*)rd; + if (!old_data) + return 0; + + if(old_data->is_valid && old_data->free_func) + { + if(old_data->data) + old_data->free_func(old_data->data); + free(old_data); + } + drmSLDelete(bo->user_data, key); + + return 1; +} diff --git a/slp/drm_slp_bufmgr.h b/slp/drm_slp_bufmgr.h new file mode 100644 index 0000000..a4adef5 --- /dev/null +++ b/slp/drm_slp_bufmgr.h @@ -0,0 +1,201 @@ +/************************************************************************** + +xserver-xorg-video-sec + +Copyright 2011 Samsung Electronics co., Ltd. All Rights Reserved. + +Contact: SooChan Lim , Sangjin Lee + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +#ifndef _DRM_SLP_BUFMGR_H_ +#define _DRM_SLP_BUFMGR_H_ + +#include +#include +#include + +typedef struct _drm_slp_bo * drm_slp_bo; +typedef struct _drm_slp_bufmgr * drm_slp_bufmgr; + +struct list_head +{ + struct list_head *prev; + struct list_head *next; +}; + +struct _drm_slp_bo +{ + struct list_head list; + drm_slp_bufmgr bufmgr; + int ref_cnt; /*atomic count*/ + void *user_data; + + /* private data */ + void *priv; +}; + +typedef enum +{ + STATUS_UNLOCK, + STATUS_READY_TO_LOCK, + STATUS_LOCK, +} lock_status; + +struct _drm_slp_bufmgr +{ + struct list_head bos; /*list head of bo*/ + + pthread_mutex_t lock; + struct { + int isOpened; + lock_status status; + sem_t* handle; + } semObj; + + void (*bufmgr_destroy)(drm_slp_bufmgr bufmgr); + int (*bufmgr_cache_flush)(drm_slp_bufmgr bufmgr, drm_slp_bo bo, int flags); + + int (*bo_size)(drm_slp_bo bo); + + void (*bo_free)(drm_slp_bo bo); + int (*bo_alloc)(drm_slp_bo bo, + const char* name, + int size, + int flags); + int (*bo_attach)(drm_slp_bo bo, + const char* name, + int type, + int size, + unsigned int handle); + int (*bo_import)(drm_slp_bo bo, unsigned int key); + unsigned int (*bo_export)(drm_slp_bo bo); + + unsigned int (*bo_get_handle)(drm_slp_bo bo, int device); + unsigned int (*bo_map)(drm_slp_bo bo, int device, int opt); + int (*bo_unmap)(drm_slp_bo bo, int device); + + + /* Padding for future extension */ + int (*bufmgr_lock) (drm_slp_bufmgr bufmgr); + int (*bufmgr_unlock) (drm_slp_bufmgr bufmgr); + int (*bo_lock) (drm_slp_bo bo, unsigned int checkOnly, unsigned int* isLocked); + int (*bo_unlock) (drm_slp_bo bo); + void (*reserved5) (void); + void (*reserved6) (void); + + /* private data */ + void *priv; + + struct list_head link; /*link of bufmgr*/ + + int drm_fd; + int ref_count; +}; + +/* DRM_SLP_MEM_TYPE */ +#define DRM_SLP_MEM_GEM 0 +#define DRM_SLP_MEM_USERPTR 1 +#define DRM_SLP_MEM_DMABUF 2 +#define DRM_SLP_MEM_GPU 3 + +/* DRM_SLP_DEVICE_TYPE */ +#define DRM_SLP_DEVICE_DEFAULT 0 //Default handle +#define DRM_SLP_DEVICE_CPU 1 +#define DRM_SLP_DEVICE_2D 2 +#define DRM_SLP_DEVICE_3D 3 +#define DRM_SLP_DEVICE_MM 4 + +/* DRM_SLP_OPTION */ +#define DRM_SLP_OPTION_READ (1 << 0) +#define DRM_SLP_OPTION_WRITE (1 << 1) + +/* DRM_SLP_CACHE */ +#define DRM_SLP_CACHE_INV 0x01 +#define DRM_SLP_CACHE_CLN 0x02 +#define DRM_SLP_CACHE_ALL 0x10 +#define DRM_SLP_CACHE_FLUSH (DRM_SLP_CACHE_INV|DRM_SLP_CACHE_CLN) +#define DRM_SLP_CACHE_FLUSH_ALL (DRM_SLP_CACHE_FLUSH|DRM_SLP_CACHE_ALL) + +enum DRM_SLP_BO_FLAGS{ + DRM_SLP_BO_DEFAULT = 0, + DRM_SLP_BO_SCANOUT = (1<<0), + DRM_SLP_BO_NONCACHABLE = (1<<1), + DRM_SLP_BO_WC = (1<<2), +}; + +/* Functions for buffer mnager */ +drm_slp_bufmgr +drm_slp_bufmgr_init(int fd, void * arg); +void +drm_slp_bufmgr_destroy(drm_slp_bufmgr bufmgr); +int +drm_slp_bufmgr_lock(drm_slp_bufmgr bufmgr); +int +drm_slp_bufmgr_unlock(drm_slp_bufmgr bufmgr); +int +drm_slp_bufmgr_cache_flush(drm_slp_bufmgr bufmgr, drm_slp_bo bo, int flags); + + +/*Functions for bo*/ +int +drm_slp_bo_size (drm_slp_bo bo); +drm_slp_bo +drm_slp_bo_ref(drm_slp_bo bo); +void +drm_slp_bo_unref(drm_slp_bo bo); +drm_slp_bo +drm_slp_bo_alloc(drm_slp_bufmgr bufmgr, + const char* name, + int size, + int flags); +drm_slp_bo +drm_slp_bo_attach(drm_slp_bufmgr bufmgr, + const char* name, + int type, + int size, + unsigned int handle); +drm_slp_bo +drm_slp_bo_import(drm_slp_bufmgr bufmgr, unsigned int key); +unsigned int +drm_slp_bo_export(drm_slp_bo bo); +unsigned int +drm_slp_bo_get_handle(drm_slp_bo, int device); +unsigned int +drm_slp_bo_map(drm_slp_bo bo, int device, int opt); +int +drm_slp_bo_unmap(drm_slp_bo bo, int device); +int +drm_slp_bo_swap(drm_slp_bo bo1, drm_slp_bo bo2); + +/*Functions for userdata of bo*/ +typedef void (*drm_data_free)(void *); +int +drm_slp_bo_add_user_data(drm_slp_bo bo, unsigned long key, drm_data_free data_free_func); +int +drm_slp_bo_delete_user_data(drm_slp_bo bo, unsigned long key); +int +drm_slp_bo_set_user_data(drm_slp_bo bo, unsigned long key, void* data); +int +drm_slp_bo_get_user_data(drm_slp_bo bo, unsigned long key, void** data); +#endif /* _DRM_SLP_BUFMGR_H_ */ diff --git a/slp/libdrm_slp.pc.in b/slp/libdrm_slp.pc.in new file mode 100644 index 0000000..220d38b --- /dev/null +++ b/slp/libdrm_slp.pc.in @@ -0,0 +1,11 @@ +prefix=@prefix@ +exec_prefix=@exec_prefix@ +libdir=@libdir@ +includedir=@includedir@ + +Name: libdrm +Description: Userspace interface to kernel DRM services +Version: @PACKAGE_VERSION@ +Requires: libdrm +Libs: -L${libdir} -ldrm_slp +Cflags: -I${includedir} -I${includedir}/libdrm diff --git a/slp/list.h b/slp/list.h new file mode 100644 index 0000000..e967b93 --- /dev/null +++ b/slp/list.h @@ -0,0 +1,131 @@ +/* + * + * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND. USA. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ + +/** + * \file + * List macros heavily inspired by the Linux kernel + * list handling. No list looping yet. + * + * Is not threadsafe, so common operations need to + * be protected using an external mutex. + */ +#ifndef _U_DOUBLE_LIST_H_ +#define _U_DOUBLE_LIST_H_ + +#include + +static void list_inithead(struct list_head *item) +{ + item->prev = item; + item->next = item; +} + +static inline void list_add(struct list_head *item, struct list_head *list) +{ + item->prev = list; + item->next = list->next; + list->next->prev = item; + list->next = item; +} + +static inline void list_addtail(struct list_head *item, struct list_head *list) +{ + item->next = list; + item->prev = list->prev; + list->prev->next = item; + list->prev = item; +} + +static inline void list_replace(struct list_head *from, struct list_head *to) +{ + to->prev = from->prev; + to->next = from->next; + from->next->prev = to; + from->prev->next = to; +} + +static inline void list_del(struct list_head *item) +{ + item->prev->next = item->next; + item->next->prev = item->prev; +} + +static inline void list_delinit(struct list_head *item) +{ + item->prev->next = item->next; + item->next->prev = item->prev; + item->next = item; + item->prev = item; +} + +#define LIST_INITHEAD(__item) list_inithead(__item) +#define LIST_ADD(__item, __list) list_add(__item, __list) +#define LIST_ADDTAIL(__item, __list) list_addtail(__item, __list) +#define LIST_REPLACE(__from, __to) list_replace(__from, __to) +#define LIST_DEL(__item) list_del(__item) +#define LIST_DELINIT(__item) list_delinit(__item) + +#define LIST_ENTRY(__type, __item, __field) \ + ((__type *)(((char *)(__item)) - offsetof(__type, __field))) + +#define LIST_IS_EMPTY(__list) \ + ((__list)->next == (__list)) + +#ifndef container_of +#define container_of(ptr, sample, member) \ + (void *)((char *)(ptr) \ + - ((char *)&(sample)->member - (char *)(sample))) +#endif + +#define LIST_FOR_EACH_ENTRY(pos, head, member) \ + for (pos = container_of((head)->next, pos, member); \ + &pos->member != (head); \ + pos = container_of(pos->member.next, pos, member)) + +#define LIST_FOR_EACH_ENTRY_SAFE(pos, storage, head, member) \ + for (pos = container_of((head)->next, pos, member), \ + storage = container_of(pos->member.next, pos, member); \ + &pos->member != (head); \ + pos = storage, storage = container_of(storage->member.next, storage, member)) + +#define LIST_FOR_EACH_ENTRY_SAFE_REV(pos, storage, head, member) \ + for (pos = container_of((head)->prev, pos, member), \ + storage = container_of(pos->member.prev, pos, member); \ + &pos->member != (head); \ + pos = storage, storage = container_of(storage->member.prev, storage, member)) + +#define LIST_FOR_EACH_ENTRY_FROM(pos, start, head, member) \ + for (pos = container_of((start), pos, member); \ + &pos->member != (head); \ + pos = container_of(pos->member.next, pos, member)) + +#define LIST_FOR_EACH_ENTRY_FROM_REV(pos, start, head, member) \ + for (pos = container_of((start), pos, member); \ + &pos->member != (head); \ + pos = container_of(pos->member.prev, pos, member)) + +#endif /*_U_DOUBLE_LIST_H_*/ diff --git a/tests/Makefile.am b/tests/Makefile.am new file mode 100644 index 0000000..1442854 --- /dev/null +++ b/tests/Makefile.am @@ -0,0 +1,64 @@ +NULL:=# + +AM_CPPFLAGS = \ + -I $(top_srcdir)/include/drm \ + -I $(top_srcdir) + +LDADD = $(top_builddir)/libdrm.la + +check_PROGRAMS = \ + dristat \ + drmstat + +SUBDIRS = modeprint proptest + +if HAVE_LIBKMS +SUBDIRS += kmstest modetest +endif + +if HAVE_RADEON +SUBDIRS += radeon +endif + +if HAVE_LIBUDEV + +check_LTLIBRARIES = libdrmtest.la + +libdrmtest_la_SOURCES = \ + drmtest.c \ + drmtest.h + +libdrmtest_la_LIBADD = \ + $(top_builddir)/libdrm.la \ + $(LIBUDEV_LIBS) + +LDADD += libdrmtest.la + +XFAIL_TESTS = \ + auth \ + lock + +TESTS = \ + openclose \ + getversion \ + getclient \ + getstats \ + setversion \ + updatedraw \ + name_from_fd \ + $(NULL) + +SUBDIRS += vbltest $(NULL) + +if HAVE_INTEL +TESTS += \ + gem_basic \ + gem_flink \ + gem_readwrite \ + gem_mmap \ + $(NULL) +endif + +check_PROGRAMS += $(TESTS) + +endif diff --git a/tests/auth.c b/tests/auth.c new file mode 100644 index 0000000..9b6fca9 --- /dev/null +++ b/tests/auth.c @@ -0,0 +1,137 @@ +/* + * Copyright © 2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include "drmtest.h" + +enum auth_event { + SERVER_READY, + CLIENT_MAGIC, + CLIENT_DONE, +}; + +int commfd[2]; + +static void wait_event(int pipe, enum auth_event expected_event) +{ + int ret; + enum auth_event event; + unsigned char in; + + ret = read(commfd[pipe], &in, 1); + if (ret == -1) + err(1, "read error"); + event = in; + + if (event != expected_event) + errx(1, "unexpected event: %d\n", event); +} + +static void +send_event(int pipe, enum auth_event send_event) +{ + int ret; + unsigned char event; + + event = send_event; + ret = write(commfd[pipe], &event, 1); + if (ret == -1) + err(1, "failed to send event %d", event); +} + +static void client() +{ + struct drm_auth auth; + int drmfd, ret; + + /* XXX: Should make sure we open the same DRM as the master */ + wait_event(0, SERVER_READY); + + drmfd = drm_open_any(); + + /* Get a client magic number and pass it to the master for auth. */ + auth.magic = 0; /* Quiet valgrind */ + ret = ioctl(drmfd, DRM_IOCTL_GET_MAGIC, &auth); + if (ret == -1) + err(1, "Couldn't get client magic"); + send_event(0, CLIENT_MAGIC); + ret = write(commfd[0], &auth.magic, sizeof(auth.magic)); + if (ret == -1) + err(1, "Couldn't write auth data"); + + /* Signal that the client is completely done. */ + send_event(0, CLIENT_DONE); +} + +static void server() +{ + int drmfd, ret; + struct drm_auth auth; + + drmfd = drm_open_any_master(); + + auth.magic = 0xd0d0d0d0; + ret = ioctl(drmfd, DRM_IOCTL_AUTH_MAGIC, &auth); + if (ret != -1 || errno != EINVAL) + errx(1, "Authenticating bad magic succeeded\n"); + + send_event(1, SERVER_READY); + + wait_event(1, CLIENT_MAGIC); + ret = read(commfd[1], &auth.magic, sizeof(auth.magic)); + if (ret == -1) + err(1, "Failure to read client magic"); + + ret = ioctl(drmfd, DRM_IOCTL_AUTH_MAGIC, &auth); + if (ret == -1) + err(1, "Failure to authenticate client magic\n"); + + wait_event(1, CLIENT_DONE); +} + +/** + * Checks DRM authentication mechanisms. + */ +int main(int argc, char **argv) +{ + int ret; + + ret = pipe(commfd); + if (ret == -1) + err(1, "Couldn't create pipe"); + + ret = fork(); + if (ret == -1) + err(1, "failure to fork client"); + if (ret == 0) + client(); + else + server(); + + return 0; +} + diff --git a/tests/dristat.c b/tests/dristat.c new file mode 100644 index 0000000..900a3e6 --- /dev/null +++ b/tests/dristat.c @@ -0,0 +1,280 @@ +/* dristat.c -- + * Created: Mon Jan 15 05:05:07 2001 by faith@acm.org + * + * Copyright 2000 VA Linux Systems, Inc., Fremont, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * + */ + +#include +#include +#include +#include "xf86drm.h" +#include "xf86drmRandom.c" +#include "xf86drmHash.c" +#include "xf86drm.c" + +#define DRM_VERSION 0x00000001 +#define DRM_MEMORY 0x00000002 +#define DRM_CLIENTS 0x00000004 +#define DRM_STATS 0x00000008 +#define DRM_BUSID 0x00000010 + +static void getversion(int fd) +{ + drmVersionPtr version; + + version = drmGetVersion(fd); + if (version) { + printf(" Version information:\n"); + printf(" Name: %s\n", version->name ? version->name : "?"); + printf(" Version: %d.%d.%d\n", + version->version_major, + version->version_minor, + version->version_patchlevel); + printf(" Date: %s\n", version->date ? version->date : "?"); + printf(" Desc: %s\n", version->desc ? version->desc : "?"); + drmFreeVersion(version); + } else { + printf(" No version information available\n"); + } +} + +static void getbusid(int fd) +{ + const char *busid = drmGetBusid(fd); + + printf(" Busid: %s\n", *busid ? busid : "(not set)"); + drmFreeBusid(busid); +} + + +static void getvm(int fd) +{ + int i; + const char *typename; + char flagname[33]; + drm_handle_t offset; + drmSize size; + drmMapType type; + drmMapFlags flags; + drm_handle_t handle; + int mtrr; + + printf(" VM map information:\n"); + printf(" flags: (R)estricted (r)ead/(w)rite (l)ocked (k)ernel (W)rite-combine (L)ock:\n"); + printf(" slot offset size type flags address mtrr\n"); + + for (i = 0; + !drmGetMap(fd, i, &offset, &size, &type, &flags, &handle, &mtrr); + i++) { + + switch (type) { + case DRM_FRAME_BUFFER: typename = "FB"; break; + case DRM_REGISTERS: typename = "REG"; break; + case DRM_SHM: typename = "SHM"; break; + case DRM_AGP: typename = "AGP"; break; + case DRM_SCATTER_GATHER: typename = "SG"; break; + default: typename = "???"; break; + } + + flagname[0] = (flags & DRM_RESTRICTED) ? 'R' : ' '; + flagname[1] = (flags & DRM_READ_ONLY) ? 'r' : 'w'; + flagname[2] = (flags & DRM_LOCKED) ? 'l' : ' '; + flagname[3] = (flags & DRM_KERNEL) ? 'k' : ' '; + flagname[4] = (flags & DRM_WRITE_COMBINING) ? 'W' : ' '; + flagname[5] = (flags & DRM_CONTAINS_LOCK) ? 'L' : ' '; + flagname[6] = '\0'; + + printf(" %4d 0x%08lx 0x%08lx %3.3s %6.6s 0x%08lx ", + i, (unsigned long)offset, (unsigned long)size, + typename, flagname, (unsigned long)handle); + if (mtrr < 0) printf("none\n"); + else printf("%4d\n", mtrr); + } +} + +static void getclients(int fd) +{ + int i; + int auth; + int pid; + int uid; + unsigned long magic; + unsigned long iocs; + char buf[64]; + char cmd[40]; + int procfd; + + printf(" DRI client information:\n"); + printf(" a pid uid magic ioctls prog\n"); + + for (i = 0; !drmGetClient(fd, i, &auth, &pid, &uid, &magic, &iocs); i++) { + sprintf(buf, "/proc/%d/cmdline", pid); + memset(cmd, 0, sizeof(cmd)); + if ((procfd = open(buf, O_RDONLY, 0)) >= 0) { + read(procfd, cmd, sizeof(cmd)-1); + close(procfd); + } + if (*cmd) { + char *pt; + + for (pt = cmd; *pt; pt++) if (!isprint(*pt)) *pt = ' '; + printf(" %c %5d %5d %10lu %10lu %s\n", + auth ? 'y' : 'n', pid, uid, magic, iocs, cmd); + } else { + printf(" %c %5d %5d %10lu %10lu\n", + auth ? 'y' : 'n', pid, uid, magic, iocs); + } + } +} + +static void printhuman(unsigned long value, const char *name, int mult) +{ + const char *p; + double f; + /* Print width 5 number in width 6 space */ + if (value < 100000) { + printf(" %5lu", value); + return; + } + + p = name; + f = (double)value / (double)mult; + if (f < 10.0) { + printf(" %4.2f%c", f, *p); + return; + } + + p++; + f = (double)value / (double)mult; + if (f < 10.0) { + printf(" %4.2f%c", f, *p); + return; + } + + p++; + f = (double)value / (double)mult; + if (f < 10.0) { + printf(" %4.2f%c", f, *p); + return; + } +} + +static void getstats(int fd, int i) +{ + drmStatsT prev, curr; + int j; + double rate; + + printf(" System statistics:\n"); + + if (drmGetStats(fd, &prev)) return; + if (!i) { + for (j = 0; j < prev.count; j++) { + printf(" "); + printf(prev.data[j].long_format, prev.data[j].long_name); + if (prev.data[j].isvalue) printf(" 0x%08lx\n", prev.data[j].value); + else printf(" %10lu\n", prev.data[j].value); + } + return; + } + + printf(" "); + for (j = 0; j < prev.count; j++) + if (!prev.data[j].verbose) { + printf(" "); + printf(prev.data[j].rate_format, prev.data[j].rate_name); + } + printf("\n"); + + for (;;) { + sleep(i); + if (drmGetStats(fd, &curr)) return; + printf(" "); + for (j = 0; j < curr.count; j++) { + if (curr.data[j].verbose) continue; + if (curr.data[j].isvalue) { + printf(" %08lx", curr.data[j].value); + } else { + rate = (curr.data[j].value - prev.data[j].value) / (double)i; + printhuman(rate, curr.data[j].mult_names, curr.data[j].mult); + } + } + printf("\n"); + memcpy(&prev, &curr, sizeof(prev)); + } + +} + +int main(int argc, char **argv) +{ + int c; + int mask = 0; + int minor = 0; + int interval = 0; + int fd; + char buf[64]; + int i; + + while ((c = getopt(argc, argv, "avmcsbM:i:")) != EOF) + switch (c) { + case 'a': mask = ~0; break; + case 'v': mask |= DRM_VERSION; break; + case 'm': mask |= DRM_MEMORY; break; + case 'c': mask |= DRM_CLIENTS; break; + case 's': mask |= DRM_STATS; break; + case 'b': mask |= DRM_BUSID; break; + case 'i': interval = strtol(optarg, NULL, 0); break; + case 'M': minor = strtol(optarg, NULL, 0); break; + default: + fprintf( stderr, "Usage: dristat [options]\n\n" ); + fprintf( stderr, "Displays DRM information. Use with no arguments to display available cards.\n\n" ); + fprintf( stderr, " -a Show all available information\n" ); + fprintf( stderr, " -b Show DRM bus ID's\n" ); + fprintf( stderr, " -c Display information about DRM clients\n" ); + fprintf( stderr, " -i [interval] Continuously display statistics every [interval] seconds\n" ); + fprintf( stderr, " -v Display DRM module and card version information\n" ); + fprintf( stderr, " -m Display memory use information\n" ); + fprintf( stderr, " -s Display DRM statistics\n" ); + fprintf( stderr, " -M [minor] Select card by minor number\n" ); + return 1; + } + + for (i = 0; i < 16; i++) if (!minor || i == minor) { + sprintf(buf, DRM_DEV_NAME, DRM_DIR_NAME, i); + fd = drmOpenMinor(i, 1, DRM_NODE_RENDER); + if (fd >= 0) { + printf("%s\n", buf); + if (mask & DRM_BUSID) getbusid(fd); + if (mask & DRM_VERSION) getversion(fd); + if (mask & DRM_MEMORY) getvm(fd); + if (mask & DRM_CLIENTS) getclients(fd); + if (mask & DRM_STATS) getstats(fd, interval); + close(fd); + } + } + + return 0; +} diff --git a/tests/drmstat.c b/tests/drmstat.c new file mode 100644 index 0000000..345b8d2 --- /dev/null +++ b/tests/drmstat.c @@ -0,0 +1,435 @@ +/* drmstat.c -- DRM device status and testing program + * Created: Tue Jan 5 08:19:24 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * + */ + +#include "config.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef HAVE_ALLOCA_H +# include +#endif +#include "xf86drm.h" + +/* Support gcc's __FUNCTION__ for people using other compilers */ +#if !defined(__GNUC__) && !defined(__FUNCTION__) +# define __FUNCTION__ __func__ /* C99 */ +#endif + +int sigio_fd; + +static double usec(struct timeval *end, struct timeval *start) +{ + double e = end->tv_sec * 1000000 + end->tv_usec; + double s = start->tv_sec * 1000000 + start->tv_usec; + + return e - s; +} + +static void getversion(int fd) +{ + drmVersionPtr version; + + version = drmGetVersion(fd); + if (version) { + printf( "Name: %s\n", version->name ? version->name : "?" ); + printf( " Version: %d.%d.%d\n", + version->version_major, + version->version_minor, + version->version_patchlevel ); + printf( " Date: %s\n", version->date ? version->date : "?" ); + printf( " Desc: %s\n", version->desc ? version->desc : "?" ); + drmFreeVersion(version); + } else { + printf( "No driver available\n" ); + } +} + +void handler(int fd, void *oldctx, void *newctx) +{ + printf("Got fd %d\n", fd); +} + +void process_sigio(char *device) +{ + int fd; + + if ((fd = open(device, 0)) < 0) { + drmError(-errno, __FUNCTION__); + exit(1); + } + + sigio_fd = fd; + /* drmInstallSIGIOHandler(fd, handler); */ + for (;;) sleep(60); +} + +int main(int argc, char **argv) +{ + int c; + int r = 0; + int fd = -1; + drm_handle_t handle; + void *address; + char *pt; + unsigned long count; + unsigned long offset; + unsigned long size; + drm_context_t context; + int loops; + char buf[1024]; + int i; + drmBufInfoPtr info; + drmBufMapPtr bufs; + drmLockPtr lock; + int secs; + + while ((c = getopt(argc, argv, + "lc:vo:O:f:s:w:W:b:r:R:P:L:C:XS:B:F:")) != EOF) + switch (c) { + case 'F': + count = strtoul(optarg, NULL, 0); + if (!fork()) { + dup(fd); + sleep(count); + } + close(fd); + break; + case 'v': getversion(fd); break; + case 'X': + if ((r = drmCreateContext(fd, &context))) { + drmError(r, argv[0]); + return 1; + } + printf( "Got %d\n", context); + break; + case 'S': + process_sigio(optarg); + break; + case 'C': + if ((r = drmSwitchToContext(fd, strtoul(optarg, NULL, 0)))) { + drmError(r, argv[0]); + return 1; + } + break; + case 'c': + if ((r = drmSetBusid(fd,optarg))) { + drmError(r, argv[0]); + return 1; + } + break; + case 'o': + if ((fd = drmOpen(optarg, NULL)) < 0) { + drmError(fd, argv[0]); + return 1; + } + break; + case 'O': + if ((fd = drmOpen(NULL, optarg)) < 0) { + drmError(fd, argv[0]); + return 1; + } + break; + case 'B': /* Test buffer allocation */ + count = strtoul(optarg, &pt, 0); + size = strtoul(pt+1, &pt, 0); + secs = strtoul(pt+1, NULL, 0); + { + drmDMAReq dma; + int *indices, *sizes; + + indices = alloca(sizeof(*indices) * count); + sizes = alloca(sizeof(*sizes) * count); + dma.context = context; + dma.send_count = 0; + dma.request_count = count; + dma.request_size = size; + dma.request_list = indices; + dma.request_sizes = sizes; + dma.flags = DRM_DMA_WAIT; + if ((r = drmDMA(fd, &dma))) { + drmError(r, argv[0]); + return 1; + } + for (i = 0; i < dma.granted_count; i++) { + printf("%5d: index = %d, size = %d\n", + i, dma.request_list[i], dma.request_sizes[i]); + } + sleep(secs); + drmFreeBufs(fd, dma.granted_count, indices); + } + break; + case 'b': + count = strtoul(optarg, &pt, 0); + size = strtoul(pt+1, NULL, 0); + if ((r = drmAddBufs(fd, count, size, 0, 65536)) < 0) { + drmError(r, argv[0]); + return 1; + } + if (!(info = drmGetBufInfo(fd))) { + drmError(0, argv[0]); + return 1; + } + for (i = 0; i < info->count; i++) { + printf("%5d buffers of size %6d (low = %d, high = %d)\n", + info->list[i].count, + info->list[i].size, + info->list[i].low_mark, + info->list[i].high_mark); + } + if ((r = drmMarkBufs(fd, 0.50, 0.80))) { + drmError(r, argv[0]); + return 1; + } + if (!(info = drmGetBufInfo(fd))) { + drmError(0, argv[0]); + return 1; + } + for (i = 0; i < info->count; i++) { + printf("%5d buffers of size %6d (low = %d, high = %d)\n", + info->list[i].count, + info->list[i].size, + info->list[i].low_mark, + info->list[i].high_mark); + } + printf("===== /proc/dri/0/mem =====\n"); + sprintf(buf, "cat /proc/dri/0/mem"); + system(buf); +#if 1 + if (!(bufs = drmMapBufs(fd))) { + drmError(0, argv[0]); + return 1; + } + printf("===============================\n"); + printf( "%d bufs\n", bufs->count); + for (i = 0; i < bufs->count; i++) { + printf( " %4d: %8d bytes at %p\n", + i, + bufs->list[i].total, + bufs->list[i].address); + } + printf("===== /proc/dri/0/vma =====\n"); + sprintf(buf, "cat /proc/dri/0/vma"); + system(buf); +#endif + break; + case 'f': + offset = strtoul(optarg, &pt, 0); + size = strtoul(pt+1, NULL, 0); + handle = 0; + if ((r = drmAddMap(fd, offset, size, + DRM_FRAME_BUFFER, 0, &handle))) { + drmError(r, argv[0]); + return 1; + } + printf("0x%08lx:0x%04lx added\n", offset, size); + printf("===== /proc/dri/0/mem =====\n"); + sprintf(buf, "cat /proc/dri/0/mem"); + system(buf); + break; + case 'r': + case 'R': + offset = strtoul(optarg, &pt, 0); + size = strtoul(pt+1, NULL, 0); + handle = 0; + if ((r = drmAddMap(fd, offset, size, + DRM_REGISTERS, + c == 'R' ? DRM_READ_ONLY : 0, + &handle))) { + drmError(r, argv[0]); + return 1; + } + printf("0x%08lx:0x%04lx added\n", offset, size); + printf("===== /proc/dri/0/mem =====\n"); + sprintf(buf, "cat /proc/dri/0/mem"); + system(buf); + break; + case 's': + size = strtoul(optarg, &pt, 0); + handle = 0; + if ((r = drmAddMap(fd, 0, size, + DRM_SHM, DRM_CONTAINS_LOCK, + &handle))) { + drmError(r, argv[0]); + return 1; + } + printf("0x%04lx byte shm added at 0x%08lx\n", size, handle); + sprintf(buf, "cat /proc/dri/0/vm"); + system(buf); + break; + case 'P': + offset = strtoul(optarg, &pt, 0); + size = strtoul(pt+1, NULL, 0); + address = NULL; + if ((r = drmMap(fd, offset, size, &address))) { + drmError(r, argv[0]); + return 1; + } + printf("0x%08lx:0x%04lx mapped at %p for pid %d\n", + offset, size, address, getpid()); + printf("===== /proc/dri/0/vma =====\n"); + sprintf(buf, "cat /proc/dri/0/vma"); + system(buf); + mprotect((void *)offset, size, PROT_READ); + printf("===== /proc/dri/0/vma =====\n"); + sprintf(buf, "cat /proc/dri/0/vma"); + system(buf); + break; + case 'w': + case 'W': + offset = strtoul(optarg, &pt, 0); + size = strtoul(pt+1, NULL, 0); + address = NULL; + if ((r = drmMap(fd, offset, size, &address))) { + drmError(r, argv[0]); + return 1; + } + printf("0x%08lx:0x%04lx mapped at %p for pid %d\n", + offset, size, address, getpid()); + printf("===== /proc/%d/maps =====\n", getpid()); + sprintf(buf, "cat /proc/%d/maps", getpid()); + system(buf); + printf("===== /proc/dri/0/mem =====\n"); + sprintf(buf, "cat /proc/dri/0/mem"); + system(buf); + printf("===== /proc/dri/0/vma =====\n"); + sprintf(buf, "cat /proc/dri/0/vma"); + system(buf); + printf("===== READING =====\n"); + for (i = 0; i < 0x10; i++) + printf("%02x ", (unsigned int)((unsigned char *)address)[i]); + printf("\n"); + if (c == 'w') { + printf("===== WRITING =====\n"); + for (i = 0; i < size; i+=2) { + ((char *)address)[i] = i & 0xff; + ((char *)address)[i+1] = i & 0xff; + } + } + printf("===== READING =====\n"); + for (i = 0; i < 0x10; i++) + printf("%02x ", (unsigned int)((unsigned char *)address)[i]); + printf("\n"); + printf("===== /proc/dri/0/vma =====\n"); + sprintf(buf, "cat /proc/dri/0/vma"); + system(buf); + break; + case 'L': + context = strtoul(optarg, &pt, 0); + offset = strtoul(pt+1, &pt, 0); + size = strtoul(pt+1, &pt, 0); + loops = strtoul(pt+1, NULL, 0); + address = NULL; + if ((r = drmMap(fd, offset, size, &address))) { + drmError(r, argv[0]); + return 1; + } + lock = address; +#if 1 + { + int counter = 0; + struct timeval loop_start, loop_end; + struct timeval lock_start, lock_end; + double wt; +#define HISTOSIZE 9 + int histo[HISTOSIZE]; + int output = 0; + int fast = 0; + + if (loops < 0) { + loops = -loops; + ++output; + } + + for (i = 0; i < HISTOSIZE; i++) histo[i] = 0; + + gettimeofday(&loop_start, NULL); + for (i = 0; i < loops; i++) { + gettimeofday(&lock_start, NULL); + DRM_LIGHT_LOCK_COUNT(fd,lock,context,fast); + gettimeofday(&lock_end, NULL); + DRM_UNLOCK(fd,lock,context); + ++counter; + wt = usec(&lock_end, &lock_start); + if (wt <= 2.5) ++histo[8]; + if (wt < 5.0) ++histo[0]; + else if (wt < 50.0) ++histo[1]; + else if (wt < 500.0) ++histo[2]; + else if (wt < 5000.0) ++histo[3]; + else if (wt < 50000.0) ++histo[4]; + else if (wt < 500000.0) ++histo[5]; + else if (wt < 5000000.0) ++histo[6]; + else ++histo[7]; + if (output) printf( "%.2f uSec, %d fast\n", wt, fast); + } + gettimeofday(&loop_end, NULL); + printf( "Average wait time = %.2f usec, %d fast\n", + usec(&loop_end, &loop_start) / counter, fast); + printf( "%9d <= 2.5 uS\n", histo[8]); + printf( "%9d < 5 uS\n", histo[0]); + printf( "%9d < 50 uS\n", histo[1]); + printf( "%9d < 500 uS\n", histo[2]); + printf( "%9d < 5000 uS\n", histo[3]); + printf( "%9d < 50000 uS\n", histo[4]); + printf( "%9d < 500000 uS\n", histo[5]); + printf( "%9d < 5000000 uS\n", histo[6]); + printf( "%9d >= 5000000 uS\n", histo[7]); + } +#else + printf( "before lock: 0x%08x\n", lock->lock); + printf( "lock: 0x%08x\n", lock->lock); + sleep(5); + printf( "unlock: 0x%08x\n", lock->lock); +#endif + break; + default: + fprintf( stderr, "Usage: drmstat [options]\n" ); + return 1; + } + + return r; +} + +void +xf86VDrvMsgVerb(int scrnIndex, int type, int verb, const char *format, + va_list args) +{ + vfprintf(stderr, format, args); +} + +int xf86ConfigDRI[10]; diff --git a/tests/drmtest.c b/tests/drmtest.c new file mode 100644 index 0000000..022994a --- /dev/null +++ b/tests/drmtest.c @@ -0,0 +1,135 @@ +/* + * Copyright © 2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include +#include +#include +#include +#include "drmtest.h" + +#define LIBUDEV_I_KNOW_THE_API_IS_SUBJECT_TO_CHANGE +#include + +static int is_master(int fd) +{ + drm_client_t client; + int ret; + + /* Check that we're the only opener and authed. */ + client.idx = 0; + ret = ioctl(fd, DRM_IOCTL_GET_CLIENT, &client); + assert (ret == 0); + if (!client.auth) + return 0; + client.idx = 1; + ret = ioctl(fd, DRM_IOCTL_GET_CLIENT, &client); + if (ret != -1 || errno != EINVAL) + return 0; + + return 1; +} + +/** Open the first DRM device matching the criteria */ +int drm_open_matching(const char *pci_glob, int flags) +{ + struct udev *udev; + struct udev_enumerate *e; + struct udev_device *device, *parent; + struct udev_list_entry *entry; + const char *pci_id, *path; + const char *usub, *dnode; + int fd; + + udev = udev_new(); + if (udev == NULL) { + fprintf(stderr, "failed to initialize udev context\n"); + abort(); + } + + fd = -1; + e = udev_enumerate_new(udev); + udev_enumerate_add_match_subsystem(e, "drm"); + udev_enumerate_scan_devices(e); + udev_list_entry_foreach(entry, udev_enumerate_get_list_entry(e)) { + path = udev_list_entry_get_name(entry); + device = udev_device_new_from_syspath(udev, path); + parent = udev_device_get_parent(device); + usub = udev_device_get_subsystem(parent); + /* Filter out KMS output devices. */ + if (!usub || (strcmp(usub, "pci") != 0)) + continue; + pci_id = udev_device_get_property_value(parent, "PCI_ID"); + if (fnmatch(pci_glob, pci_id, 0) != 0) + continue; + dnode = udev_device_get_devnode(device); + if (strstr(dnode, "control")) + continue; + fd = open(dnode, O_RDWR); + if (fd < 0) + continue; + if ((flags & DRM_TEST_MASTER) && !is_master(fd)) { + close(fd); + fd = -1; + continue; + } + + break; + } + udev_enumerate_unref(e); + udev_unref(udev); + + return fd; +} + +int drm_open_any(void) +{ + int fd = drm_open_matching("*:*", 0); + + if (fd < 0) { + fprintf(stderr, "failed to open any drm device\n"); + exit(0); + } + + return fd; +} + +/** + * Open the first DRM device we can find where we end up being the master. + */ +int drm_open_any_master(void) +{ + int fd = drm_open_matching("*:*", DRM_TEST_MASTER); + + if (fd < 0) { + fprintf(stderr, "failed to open any drm device\n"); + exit(0); + } + + return fd; + +} diff --git a/tests/drmtest.h b/tests/drmtest.h new file mode 100644 index 0000000..55bb446 --- /dev/null +++ b/tests/drmtest.h @@ -0,0 +1,40 @@ +/* + * Copyright © 2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include +#include +#include +#include + +#include "xf86drm.h" + +#define DRM_TEST_MASTER 0x01 + +int drm_open_any(void); +int drm_open_any_master(void); +int drm_open_matching(const char *pci_glob, int flags); diff --git a/tests/gem_basic.c b/tests/gem_basic.c new file mode 100644 index 0000000..4e4b6cb --- /dev/null +++ b/tests/gem_basic.c @@ -0,0 +1,102 @@ +/* + * Copyright © 2008 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "drm.h" +#include "i915_drm.h" + +static void +test_bad_close(int fd) +{ + struct drm_gem_close close; + int ret; + + printf("Testing error return on bad close ioctl.\n"); + + close.handle = 0x10101010; + ret = ioctl(fd, DRM_IOCTL_GEM_CLOSE, &close); + + assert(ret == -1 && errno == EINVAL); +} + +static void +test_create_close(int fd) +{ + struct drm_i915_gem_create create; + struct drm_gem_close close; + int ret; + + printf("Testing creating and closing an object.\n"); + + memset(&create, 0, sizeof(create)); + create.size = 16 * 1024; + ret = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create); + assert(ret == 0); + + close.handle = create.handle; + ret = ioctl(fd, DRM_IOCTL_GEM_CLOSE, &close); +} + +static void +test_create_fd_close(int fd) +{ + struct drm_i915_gem_create create; + int ret; + + printf("Testing closing with an object allocated.\n"); + + memset(&create, 0, sizeof(create)); + create.size = 16 * 1024; + ret = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create); + assert(ret == 0); + + close(fd); +} + +int main(int argc, char **argv) +{ + int fd; + + fd = drm_open_matching("8086:*", 0); + if (fd < 0) { + fprintf(stderr, "failed to open intel drm device\n"); + return 0; + } + + test_bad_close(fd); + test_create_close(fd); + test_create_fd_close(fd); + + return 0; +} diff --git a/tests/gem_flink.c b/tests/gem_flink.c new file mode 100644 index 0000000..ce43e42 --- /dev/null +++ b/tests/gem_flink.c @@ -0,0 +1,137 @@ +/* + * Copyright © 2008 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "drm.h" +#include "i915_drm.h" + +static void +test_flink(int fd) +{ + struct drm_i915_gem_create create; + struct drm_gem_flink flink; + struct drm_gem_open open; + int ret; + + printf("Testing flink and open.\n"); + + memset(&create, 0, sizeof(create)); + create.size = 16 * 1024; + ret = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create); + assert(ret == 0); + + flink.handle = create.handle; + ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, &flink); + assert(ret == 0); + + open.name = flink.name; + ret = ioctl(fd, DRM_IOCTL_GEM_OPEN, &open); + assert(ret == 0); + assert(open.handle != 0); +} + +static void +test_double_flink(int fd) +{ + struct drm_i915_gem_create create; + struct drm_gem_flink flink; + struct drm_gem_flink flink2; + int ret; + + printf("Testing repeated flink.\n"); + + memset(&create, 0, sizeof(create)); + create.size = 16 * 1024; + ret = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create); + assert(ret == 0); + + flink.handle = create.handle; + ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, &flink); + assert(ret == 0); + + flink2.handle = create.handle; + ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, &flink2); + assert(ret == 0); + assert(flink2.name == flink.name); +} + +static void +test_bad_flink(int fd) +{ + struct drm_gem_flink flink; + int ret; + + printf("Testing error return on bad flink ioctl.\n"); + + flink.handle = 0x10101010; + ret = ioctl(fd, DRM_IOCTL_GEM_FLINK, &flink); + assert(ret == -1 && errno == ENOENT); +} + +static void +test_bad_open(int fd) +{ + struct drm_gem_open open; + int ret; + + printf("Testing error return on bad open ioctl.\n"); + + open.name = 0x10101010; + ret = ioctl(fd, DRM_IOCTL_GEM_OPEN, &open); + + assert(ret == -1 && errno == ENOENT); +} + +int main(int argc, char **argv) +{ + int fd; + + if (geteuid()) { + fprintf(stderr, "requires root privileges, skipping\n"); + return 77; + } + + fd = drm_open_matching("8086:*", 0); + if (fd < 0) { + fprintf(stderr, "failed to open intel drm device, skipping\n"); + return 77; + } + + test_flink(fd); + test_double_flink(fd); + test_bad_flink(fd); + test_bad_open(fd); + + return 0; +} diff --git a/tests/gem_mmap.c b/tests/gem_mmap.c new file mode 100644 index 0000000..2239789 --- /dev/null +++ b/tests/gem_mmap.c @@ -0,0 +1,136 @@ +/* + * Copyright © 2008 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "drm.h" +#include "i915_drm.h" + +#define OBJECT_SIZE 16384 + +int do_read(int fd, int handle, void *buf, int offset, int size) +{ + struct drm_i915_gem_pread read; + + /* Ensure that we don't have any convenient data in buf in case + * we fail. + */ + memset(buf, 0xd0, size); + + memset(&read, 0, sizeof(read)); + read.handle = handle; + read.data_ptr = (uintptr_t)buf; + read.size = size; + read.offset = offset; + + return ioctl(fd, DRM_IOCTL_I915_GEM_PREAD, &read); +} + +int do_write(int fd, int handle, void *buf, int offset, int size) +{ + struct drm_i915_gem_pwrite write; + + memset(&write, 0, sizeof(write)); + write.handle = handle; + write.data_ptr = (uintptr_t)buf; + write.size = size; + write.offset = offset; + + return ioctl(fd, DRM_IOCTL_I915_GEM_PWRITE, &write); +} + +int main(int argc, char **argv) +{ + int fd; + struct drm_i915_gem_create create; + struct drm_i915_gem_mmap mmap; + struct drm_gem_close unref; + uint8_t expected[OBJECT_SIZE]; + uint8_t buf[OBJECT_SIZE]; + uint8_t *addr; + int ret; + int handle; + + fd = drm_open_matching("8086:*", 0); + if (fd < 0) { + fprintf(stderr, "failed to open intel drm device, skipping\n"); + return 0; + } + + memset(&mmap, 0, sizeof(mmap)); + mmap.handle = 0x10101010; + mmap.offset = 0; + mmap.size = 4096; + printf("Testing mmaping of bad object.\n"); + ret = ioctl(fd, DRM_IOCTL_I915_GEM_MMAP, &mmap); + assert(ret == -1 && errno == ENOENT); + + memset(&create, 0, sizeof(create)); + create.size = OBJECT_SIZE; + ret = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create); + assert(ret == 0); + handle = create.handle; + + printf("Testing mmaping of newly created object.\n"); + mmap.handle = handle; + mmap.offset = 0; + mmap.size = OBJECT_SIZE; + ret = ioctl(fd, DRM_IOCTL_I915_GEM_MMAP, &mmap); + assert(ret == 0); + addr = (uint8_t *)(uintptr_t)mmap.addr_ptr; + + printf("Testing contents of newly created object.\n"); + memset(expected, 0, sizeof(expected)); + assert(memcmp(addr, expected, sizeof(expected)) == 0); + + printf("Testing coherency of writes and mmap reads.\n"); + memset(buf, 0, sizeof(buf)); + memset(buf + 1024, 0x01, 1024); + memset(expected + 1024, 0x01, 1024); + ret = do_write(fd, handle, buf, 0, OBJECT_SIZE); + assert(ret == 0); + assert(memcmp(buf, addr, sizeof(buf)) == 0); + + printf("Testing that mapping stays after close\n"); + unref.handle = handle; + ret = ioctl(fd, DRM_IOCTL_GEM_CLOSE, &unref); + assert(ret == 0); + assert(memcmp(buf, addr, sizeof(buf)) == 0); + + printf("Testing unmapping\n"); + munmap(addr, OBJECT_SIZE); + + close(fd); + + return 0; +} diff --git a/tests/gem_readwrite.c b/tests/gem_readwrite.c new file mode 100644 index 0000000..07dc853 --- /dev/null +++ b/tests/gem_readwrite.c @@ -0,0 +1,139 @@ +/* + * Copyright © 2008 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "drm.h" +#include "i915_drm.h" + +#define OBJECT_SIZE 16384 + +int do_read(int fd, int handle, void *buf, int offset, int size) +{ + struct drm_i915_gem_pread read; + + /* Ensure that we don't have any convenient data in buf in case + * we fail. + */ + memset(buf, 0xd0, size); + + memset(&read, 0, sizeof(read)); + read.handle = handle; + read.data_ptr = (uintptr_t)buf; + read.size = size; + read.offset = offset; + + return ioctl(fd, DRM_IOCTL_I915_GEM_PREAD, &read); +} + +int do_write(int fd, int handle, void *buf, int offset, int size) +{ + struct drm_i915_gem_pwrite write; + + memset(&write, 0, sizeof(write)); + write.handle = handle; + write.data_ptr = (uintptr_t)buf; + write.size = size; + write.offset = offset; + + return ioctl(fd, DRM_IOCTL_I915_GEM_PWRITE, &write); +} + +int main(int argc, char **argv) +{ + int fd; + struct drm_i915_gem_create create; + uint8_t expected[OBJECT_SIZE]; + uint8_t buf[OBJECT_SIZE]; + int ret; + int handle; + + fd = drm_open_matching("8086:*", 0); + if (fd < 0) { + fprintf(stderr, "failed to open intel drm device, skipping\n"); + return 0; + } + + memset(&create, 0, sizeof(create)); + create.size = OBJECT_SIZE; + ret = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE, &create); + assert(ret == 0); + handle = create.handle; + + printf("Testing contents of newly created object.\n"); + ret = do_read(fd, handle, buf, 0, OBJECT_SIZE); + assert(ret == 0); + memset(&expected, 0, sizeof(expected)); + assert(memcmp(expected, buf, sizeof(expected)) == 0); + + printf("Testing read beyond end of buffer.\n"); + ret = do_read(fd, handle, buf, OBJECT_SIZE / 2, OBJECT_SIZE); + printf("%d %d\n", ret, errno); + assert(ret == -1 && errno == EINVAL); + + printf("Testing full write of buffer\n"); + memset(buf, 0, sizeof(buf)); + memset(buf + 1024, 0x01, 1024); + memset(expected + 1024, 0x01, 1024); + ret = do_write(fd, handle, buf, 0, OBJECT_SIZE); + assert(ret == 0); + ret = do_read(fd, handle, buf, 0, OBJECT_SIZE); + assert(ret == 0); + assert(memcmp(buf, expected, sizeof(buf)) == 0); + + printf("Testing partial write of buffer\n"); + memset(buf + 4096, 0x02, 1024); + memset(expected + 4096, 0x02, 1024); + ret = do_write(fd, handle, buf + 4096, 4096, 1024); + assert(ret == 0); + ret = do_read(fd, handle, buf, 0, OBJECT_SIZE); + assert(ret == 0); + assert(memcmp(buf, expected, sizeof(buf)) == 0); + + printf("Testing partial read of buffer\n"); + ret = do_read(fd, handle, buf, 512, 1024); + assert(ret == 0); + assert(memcmp(buf, expected + 512, 1024) == 0); + + printf("Testing read of bad buffer handle\n"); + ret = do_read(fd, 1234, buf, 0, 1024); + assert(ret == -1 && errno == ENOENT); + + printf("Testing write of bad buffer handle\n"); + ret = do_write(fd, 1234, buf, 0, 1024); + assert(ret == -1 && errno == ENOENT); + + close(fd); + + return 0; +} diff --git a/tests/getclient.c b/tests/getclient.c new file mode 100644 index 0000000..349c16e --- /dev/null +++ b/tests/getclient.c @@ -0,0 +1,60 @@ +/* + * Copyright © 2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include "drmtest.h" + +/** + * Checks DRM_IOCTL_GET_CLIENT. + */ +int main(int argc, char **argv) +{ + int fd, ret; + drm_client_t client; + + fd = drm_open_any(); + + /* Look for client index 0. This should exist whether we're operating + * on an otherwise unused drm device, or the X Server is running on + * the device. + */ + client.idx = 0; + ret = ioctl(fd, DRM_IOCTL_GET_CLIENT, &client); + assert(ret == 0); + + /* Look for some absurd client index and make sure it's invalid. + * The DRM drivers currently always return data, so the user has + * no real way to detect when the list has terminated. That's bad, + * and this test is XFAIL as a result. + */ + client.idx = 0x7fffffff; + ret = ioctl(fd, DRM_IOCTL_GET_CLIENT, &client); + assert(ret == -1 && errno == EINVAL); + + close(fd); + return 0; +} diff --git a/tests/getstats.c b/tests/getstats.c new file mode 100644 index 0000000..bd55b12 --- /dev/null +++ b/tests/getstats.c @@ -0,0 +1,51 @@ +/* + * Copyright © 2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include "drmtest.h" + +/** + * Checks DRM_IOCTL_GET_STATS. + * + * I don't care too much about the actual contents, just that the kernel + * doesn't crash. + */ +int main(int argc, char **argv) +{ + int fd, ret; + drm_stats_t stats; + + fd = drm_open_any(); + + ret = ioctl(fd, DRM_IOCTL_GET_STATS, &stats); + assert(ret == 0); + + assert(stats.count >= 0); + + close(fd); + return 0; +} diff --git a/tests/getversion.c b/tests/getversion.c new file mode 100644 index 0000000..711d376 --- /dev/null +++ b/tests/getversion.c @@ -0,0 +1,48 @@ +/* + * Copyright © 2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include "drmtest.h" + +/** + * Checks DRM_IOCTL_GET_VERSION and libdrm's drmGetVersion() interface to it. + */ +int main(int argc, char **argv) +{ + int fd; + drmVersionPtr v; + + fd = drm_open_any(); + v = drmGetVersion(fd); + assert(strlen(v->name) != 0); + assert(strlen(v->date) != 0); + assert(strlen(v->desc) != 0); + if (strcmp(v->name, "i915") == 0) + assert(v->version_major >= 1); + drmFree(v); + close(fd); + return 0; +} diff --git a/tests/kmstest/Makefile.am b/tests/kmstest/Makefile.am new file mode 100644 index 0000000..ae562a1 --- /dev/null +++ b/tests/kmstest/Makefile.am @@ -0,0 +1,17 @@ +AM_CFLAGS = \ + -I$(top_srcdir)/include/drm \ + -I$(top_srcdir)/libkms/ \ + -I$(top_srcdir) + +noinst_PROGRAMS = \ + kmstest + +kmstest_SOURCES = \ + main.c + +kmstest_LDADD = \ + $(top_builddir)/libdrm.la \ + $(top_builddir)/libkms/libkms.la + +run: kmstest + ./kmstest diff --git a/tests/kmstest/main.c b/tests/kmstest/main.c new file mode 100644 index 0000000..5df0a38 --- /dev/null +++ b/tests/kmstest/main.c @@ -0,0 +1,91 @@ +/************************************************************************** + * + * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + + +#include +#include +#include "xf86drm.h" +#include "libkms.h" + +#define CHECK_RET_RETURN(ret, str) \ + if (ret < 0) { \ + printf("%s: %s (%s)\n", __func__, str, strerror(-ret)); \ + return ret; \ + } + +int test_bo(struct kms_driver *kms) +{ + struct kms_bo *bo; + int ret; + unsigned attrs[7] = { + KMS_WIDTH, 1024, + KMS_HEIGHT, 768, + KMS_BO_TYPE, KMS_BO_TYPE_SCANOUT_X8R8G8B8, + KMS_TERMINATE_PROP_LIST, + }; + + ret = kms_bo_create(kms, attrs, &bo); + CHECK_RET_RETURN(ret, "Could not create bo"); + + kms_bo_destroy(&bo); + + return 0; +} + +char *drivers[] = { + "i915", + "radeon", + "nouveau", + "vmwgfx", + NULL +}; + +int main(int argc, char** argv) +{ + struct kms_driver *kms; + int ret, fd, i; + + for (i = 0, fd = -1; fd < 0 && drivers[i]; i++) + fd = drmOpen(drivers[i], NULL); + CHECK_RET_RETURN(fd, "Could not open device"); + + ret = kms_create(fd, &kms); + CHECK_RET_RETURN(ret, "Failed to create kms driver"); + + ret = test_bo(kms); + if (ret) + goto err; + + printf("%s: All ok!\n", __func__); + + kms_destroy(&kms); + return 0; + +err: + kms_destroy(&kms); + return ret; +} diff --git a/tests/lock.c b/tests/lock.c new file mode 100644 index 0000000..86caa28 --- /dev/null +++ b/tests/lock.c @@ -0,0 +1,263 @@ +/* + * Copyright © 2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +/** @file lock.c + * Tests various potential failures of the DRM locking mechanisms + */ + +#include +#include "drmtest.h" + +enum auth_event { + SERVER_READY, + CLIENT_MAGIC, + SERVER_LOCKED, + CLIENT_LOCKED, +}; + +int commfd[2]; +unsigned int lock1 = 0x00001111; +unsigned int lock2 = 0x00002222; + +/* return time in milliseconds */ +static unsigned int +get_millis() +{ + struct timeval tv; + + gettimeofday(&tv, NULL); + return tv.tv_sec * 1000 + tv.tv_usec / 1000; +} + +static void +wait_event(int pipe, enum auth_event expected_event) +{ + int ret; + enum auth_event event; + unsigned char in; + + ret = read(commfd[pipe], &in, 1); + if (ret == -1) + err(1, "read error"); + event = in; + + if (event != expected_event) + errx(1, "unexpected event: %d\n", event); +} + +static void +send_event(int pipe, enum auth_event send_event) +{ + int ret; + unsigned char event; + + event = send_event; + ret = write(commfd[pipe], &event, 1); + if (ret == -1) + err(1, "failed to send event %d", event); +} + +static void +client_auth(int drmfd) +{ + struct drm_auth auth; + int ret; + + /* Get a client magic number and pass it to the master for auth. */ + ret = ioctl(drmfd, DRM_IOCTL_GET_MAGIC, &auth); + if (ret == -1) + err(1, "Couldn't get client magic"); + send_event(0, CLIENT_MAGIC); + ret = write(commfd[0], &auth.magic, sizeof(auth.magic)); + if (ret == -1) + err(1, "Couldn't write auth data"); +} + +static void +server_auth(int drmfd) +{ + struct drm_auth auth; + int ret; + + send_event(1, SERVER_READY); + wait_event(1, CLIENT_MAGIC); + ret = read(commfd[1], &auth.magic, sizeof(auth.magic)); + if (ret == -1) + err(1, "Failure to read client magic"); + + ret = ioctl(drmfd, DRM_IOCTL_AUTH_MAGIC, &auth); + if (ret == -1) + err(1, "Failure to authenticate client magic\n"); +} + +/** Tests that locking is successful in normal conditions */ +static void +test_lock_unlock(int drmfd) +{ + int ret; + + ret = drmGetLock(drmfd, lock1, 0); + if (ret != 0) + err(1, "Locking failed"); + ret = drmUnlock(drmfd, lock1); + if (ret != 0) + err(1, "Unlocking failed"); +} + +/** Tests that unlocking the lock while it's not held works correctly */ +static void +test_unlock_unlocked(int drmfd) +{ + int ret; + + ret = drmUnlock(drmfd, lock1); + if (ret == 0) + err(1, "Unlocking unlocked lock succeeded"); +} + +/** Tests that unlocking a lock held by another context fails appropriately */ +static void +test_unlock_unowned(int drmfd) +{ + int ret; + + ret = drmGetLock(drmfd, lock1, 0); + assert(ret == 0); + ret = drmUnlock(drmfd, lock2); + if (ret == 0) + errx(1, "Unlocking other context's lock succeeded"); + ret = drmUnlock(drmfd, lock1); + assert(ret == 0); +} + +/** + * Tests that an open/close by the same process doesn't result in the lock + * being dropped. + */ +static void test_open_close_locked(drmfd) +{ + int ret, tempfd; + + ret = drmGetLock(drmfd, lock1, 0); + assert(ret == 0); + /* XXX: Need to make sure that this is the same device as drmfd */ + tempfd = drm_open_any(); + close(tempfd); + ret = drmUnlock(drmfd, lock1); + if (ret != 0) + errx(1, "lock lost during open/close by same pid"); +} + +static void client() +{ + int drmfd, ret; + unsigned int time; + + wait_event(0, SERVER_READY); + + /* XXX: Should make sure we open the same DRM as the master */ + drmfd = drm_open_any(); + + client_auth(drmfd); + + /* Wait for the server to grab the lock, then grab it ourselves (to + * contest it). Hopefully we hit it within the window of when the + * server locks. + */ + wait_event(0, SERVER_LOCKED); + ret = drmGetLock(drmfd, lock2, 0); + time = get_millis(); + if (ret != 0) + err(1, "Failed to get lock on client\n"); + drmUnlock(drmfd, lock2); + + /* Tell the server that our locking completed, and when it did */ + send_event(0, CLIENT_LOCKED); + ret = write(commfd[0], &time, sizeof(time)); + + close(drmfd); + exit(0); +} + +static void server() +{ + int drmfd, tempfd, ret; + unsigned int client_time, unlock_time; + + drmfd = drm_open_any_master(); + + test_lock_unlock(drmfd); + test_unlock_unlocked(drmfd); + test_unlock_unowned(drmfd); + test_open_close_locked(drmfd); + + /* Perform the authentication sequence with the client. */ + server_auth(drmfd); + + /* Now, test that the client attempting to lock while the server + * holds the lock works correctly. + */ + ret = drmGetLock(drmfd, lock1, 0); + assert(ret == 0); + send_event(1, SERVER_LOCKED); + /* Wait a while for the client to do its thing */ + sleep(1); + ret = drmUnlock(drmfd, lock1); + assert(ret == 0); + unlock_time = get_millis(); + + wait_event(1, CLIENT_LOCKED); + ret = read(commfd[1], &client_time, sizeof(client_time)); + if (ret == -1) + err(1, "Failure to read client magic"); + + if (client_time < unlock_time) + errx(1, "Client took lock before server released it"); + + close(drmfd); +} + +int main(int argc, char **argv) +{ + int ret; + + + ret = pipe(commfd); + if (ret == -1) + err(1, "Couldn't create pipe"); + + ret = fork(); + if (ret == -1) + err(1, "failure to fork client"); + if (ret == 0) + client(); + else + server(); + + return 0; +} + diff --git a/tests/modeprint/Makefile.am b/tests/modeprint/Makefile.am new file mode 100644 index 0000000..c4862ac --- /dev/null +++ b/tests/modeprint/Makefile.am @@ -0,0 +1,11 @@ +AM_CFLAGS = \ + -I$(top_srcdir)/include/drm \ + -I$(top_srcdir) + +noinst_PROGRAMS = \ + modeprint + +modeprint_SOURCES = \ + modeprint.c +modeprint_LDADD = \ + $(top_builddir)/libdrm.la diff --git a/tests/modeprint/modeprint.c b/tests/modeprint/modeprint.c new file mode 100644 index 0000000..545ff40 --- /dev/null +++ b/tests/modeprint/modeprint.c @@ -0,0 +1,403 @@ +/* + * \file modedemo.c + * Test program to dump DRM kernel mode setting related information. + * Queries the kernel for all available information and dumps it to stdout. + * + * \author Jakob Bornecrantz + */ + +/* + * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas. + * Copyright (c) 2007-2008 Jakob Bornecrantz + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "xf86drm.h" +#include "xf86drmMode.h" + +int connectors; +int full_props; +int edid; +int modes; +int full_modes; +int encoders; +int crtcs; +int fbs; +char *module_name; + +const char* getConnectionText(drmModeConnection conn) +{ + switch (conn) { + case DRM_MODE_CONNECTED: + return "connected"; + case DRM_MODE_DISCONNECTED: + return "disconnected"; + default: + return "unknown"; + } + +} + +int printMode(struct drm_mode_modeinfo *mode) +{ + if (full_modes) { + printf("Mode: %s\n", mode->name); + printf("\tclock : %i\n", mode->clock); + printf("\thdisplay : %i\n", mode->hdisplay); + printf("\thsync_start : %i\n", mode->hsync_start); + printf("\thsync_end : %i\n", mode->hsync_end); + printf("\thtotal : %i\n", mode->htotal); + printf("\thskew : %i\n", mode->hskew); + printf("\tvdisplay : %i\n", mode->vdisplay); + printf("\tvsync_start : %i\n", mode->vsync_start); + printf("\tvsync_end : %i\n", mode->vsync_end); + printf("\tvtotal : %i\n", mode->vtotal); + printf("\tvscan : %i\n", mode->vscan); + printf("\tvrefresh : %i\n", mode->vrefresh); + printf("\tflags : %i\n", mode->flags); + } else { + printf("Mode: \"%s\" %ix%i %i\n", mode->name, + mode->hdisplay, mode->vdisplay, mode->vrefresh); + } + return 0; +} + +int printProperty(int fd, drmModeResPtr res, drmModePropertyPtr props, uint64_t value) +{ + const char *name = NULL; + int j; + + printf("Property: %s\n", props->name); + printf("\tid : %i\n", props->prop_id); + printf("\tflags : %i\n", props->flags); + printf("\tcount_values : %d\n", props->count_values); + + + if (props->count_values) { + printf("\tvalues :"); + for (j = 0; j < props->count_values; j++) + printf(" %" PRIu64, props->values[j]); + printf("\n"); + } + + + printf("\tcount_enums : %d\n", props->count_enums); + + if (props->flags & DRM_MODE_PROP_BLOB) { + drmModePropertyBlobPtr blob; + + blob = drmModeGetPropertyBlob(fd, value); + if (blob) { + printf("blob is %d length, %08X\n", blob->length, *(uint32_t *)blob->data); + drmModeFreePropertyBlob(blob); + } else { + printf("error getting blob %" PRIu64 "\n", value); + } + + } else { + if (!strncmp(props->name, "DPMS", 4)) + ; + + for (j = 0; j < props->count_enums; j++) { + printf("\t\t%lld = %s\n", props->enums[j].value, props->enums[j].name); + if (props->enums[j].value == value) + name = props->enums[j].name; + } + + if (props->count_enums && name) { + printf("\tcon_value : %s\n", name); + } else { + printf("\tcon_value : %" PRIu64 "\n", value); + } + } + + return 0; +} + +int printConnector(int fd, drmModeResPtr res, drmModeConnectorPtr connector, uint32_t id) +{ + int i = 0; + struct drm_mode_modeinfo *mode = NULL; + drmModePropertyPtr props; + + printf("Connector: %d-%d\n", connector->connector_type, connector->connector_type_id); + printf("\tid : %i\n", id); + printf("\tencoder id : %i\n", connector->encoder_id); + printf("\tconn : %s\n", getConnectionText(connector->connection)); + printf("\tsize : %ix%i (mm)\n", connector->mmWidth, connector->mmHeight); + printf("\tcount_modes : %i\n", connector->count_modes); + printf("\tcount_props : %i\n", connector->count_props); + if (connector->count_props) { + printf("\tprops :"); + for (i = 0; i < connector->count_props; i++) + printf(" %i", connector->props[i]); + printf("\n"); + } + + printf("\tcount_encoders : %i\n", connector->count_encoders); + if (connector->count_encoders) { + printf("\tencoders :"); + for (i = 0; i < connector->count_encoders; i++) + printf(" %i", connector->encoders[i]); + printf("\n"); + } + + if (modes) { + for (i = 0; i < connector->count_modes; i++) { + mode = (struct drm_mode_modeinfo *)&connector->modes[i]; + printMode(mode); + } + } + + if (full_props) { + for (i = 0; i < connector->count_props; i++) { + props = drmModeGetProperty(fd, connector->props[i]); + if (props) { + printProperty(fd, res, props, connector->prop_values[i]); + drmModeFreeProperty(props); + } + } + } + + return 0; +} + +int printEncoder(int fd, drmModeResPtr res, drmModeEncoderPtr encoder, uint32_t id) +{ + printf("Encoder\n"); + printf("\tid :%i\n", id); + printf("\tcrtc_id :%d\n", encoder->crtc_id); + printf("\ttype :%d\n", encoder->encoder_type); + printf("\tpossible_crtcs :0x%x\n", encoder->possible_crtcs); + printf("\tpossible_clones :0x%x\n", encoder->possible_clones); + return 0; +} + +int printCrtc(int fd, drmModeResPtr res, drmModeCrtcPtr crtc, uint32_t id) +{ + printf("Crtc\n"); + printf("\tid : %i\n", id); + printf("\tx : %i\n", crtc->x); + printf("\ty : %i\n", crtc->y); + printf("\twidth : %i\n", crtc->width); + printf("\theight : %i\n", crtc->height); + printf("\tmode : %p\n", &crtc->mode); + printf("\tgamma size : %d\n", crtc->gamma_size); + + return 0; +} + +int printFrameBuffer(int fd, drmModeResPtr res, drmModeFBPtr fb) +{ + printf("Framebuffer\n"); + printf("\thandle : %i\n", fb->handle); + printf("\twidth : %i\n", fb->width); + printf("\theight : %i\n", fb->height); + printf("\tpitch : %i\n", fb->pitch);; + printf("\tbpp : %i\n", fb->bpp); + printf("\tdepth : %i\n", fb->depth); + printf("\tbuffer_id : %i\n", fb->handle); + + return 0; +} + +int printRes(int fd, drmModeResPtr res) +{ + int i; + drmModeFBPtr fb; + drmModeCrtcPtr crtc; + drmModeEncoderPtr encoder; + drmModeConnectorPtr connector; + + printf("Resources\n\n"); + + printf("count_connectors : %i\n", res->count_connectors); + printf("count_encoders : %i\n", res->count_encoders); + printf("count_crtcs : %i\n", res->count_crtcs); + printf("count_fbs : %i\n", res->count_fbs); + + printf("\n"); + + if (connectors) { + for (i = 0; i < res->count_connectors; i++) { + connector = drmModeGetConnector(fd, res->connectors[i]); + + if (!connector) + printf("Could not get connector %i\n", res->connectors[i]); + else { + printConnector(fd, res, connector, res->connectors[i]); + drmModeFreeConnector(connector); + } + } + printf("\n"); + } + + + if (encoders) { + for (i = 0; i < res->count_encoders; i++) { + encoder = drmModeGetEncoder(fd, res->encoders[i]); + + if (!encoder) + printf("Could not get encoder %i\n", res->encoders[i]); + else { + printEncoder(fd, res, encoder, res->encoders[i]); + drmModeFreeEncoder(encoder); + } + } + printf("\n"); + } + + if (crtcs) { + for (i = 0; i < res->count_crtcs; i++) { + crtc = drmModeGetCrtc(fd, res->crtcs[i]); + + if (!crtc) + printf("Could not get crtc %i\n", res->crtcs[i]); + else { + printCrtc(fd, res, crtc, res->crtcs[i]); + drmModeFreeCrtc(crtc); + } + } + printf("\n"); + } + + if (fbs) { + for (i = 0; i < res->count_fbs; i++) { + fb = drmModeGetFB(fd, res->fbs[i]); + + if (!fb) + printf("Could not get fb %i\n", res->fbs[i]); + else { + printFrameBuffer(fd, res, fb); + drmModeFreeFB(fb); + } + } + } + + return 0; +} + +void args(int argc, char **argv) +{ + int i; + + fbs = 0; + edid = 0; + crtcs = 0; + modes = 0; + encoders = 0; + full_modes = 0; + full_props = 0; + connectors = 0; + + module_name = argv[1]; + + for (i = 2; i < argc; i++) { + if (strcmp(argv[i], "-fb") == 0) { + fbs = 1; + } else if (strcmp(argv[i], "-crtcs") == 0) { + crtcs = 1; + } else if (strcmp(argv[i], "-cons") == 0) { + connectors = 1; + modes = 1; + } else if (strcmp(argv[i], "-modes") == 0) { + connectors = 1; + modes = 1; + } else if (strcmp(argv[i], "-full") == 0) { + connectors = 1; + modes = 1; + full_modes = 1; + } else if (strcmp(argv[i], "-props") == 0) { + connectors = 1; + full_props = 1; + } else if (strcmp(argv[i], "-edids") == 0) { + connectors = 1; + edid = 1; + } else if (strcmp(argv[i], "-encoders") == 0) { + encoders = 1; + } else if (strcmp(argv[i], "-v") == 0) { + fbs = 1; + edid = 1; + crtcs = 1; + modes = 1; + encoders = 1; + full_modes = 1; + full_props = 1; + connectors = 1; + } + } + + if (argc == 2) { + fbs = 1; + edid = 1; + crtcs = 1; + modes = 1; + encoders = 1; + full_modes = 0; + full_props = 0; + connectors = 1; + } +} + +int main(int argc, char **argv) +{ + int fd; + drmModeResPtr res; + + if (argc == 1) { + printf("Please add modulename as first argument\n"); + return 1; + } + + args(argc, argv); + + printf("Starting test\n"); + + fd = drmOpen(module_name, NULL); + + if (fd < 0) { + printf("Failed to open the card fd (%d)\n",fd); + return 1; + } + + res = drmModeGetResources(fd); + if (res == 0) { + printf("Failed to get resources from card\n"); + drmClose(fd); + return 1; + } + + printRes(fd, res); + + drmModeFreeResources(res); + + printf("Ok\n"); + + return 0; +} diff --git a/tests/modetest/Makefile.am b/tests/modetest/Makefile.am new file mode 100644 index 0000000..2191242 --- /dev/null +++ b/tests/modetest/Makefile.am @@ -0,0 +1,15 @@ +AM_CFLAGS = \ + -I$(top_srcdir)/include/drm \ + -I$(top_srcdir)/libkms/ \ + -I$(top_srcdir) \ + $(CAIRO_CFLAGS) + +noinst_PROGRAMS = \ + modetest + +modetest_SOURCES = \ + modetest.c +modetest_LDADD = \ + $(top_builddir)/libdrm.la \ + $(top_builddir)/libkms/libkms.la \ + $(CAIRO_LIBS) diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c new file mode 100644 index 0000000..dc84cf3 --- /dev/null +++ b/tests/modetest/modetest.c @@ -0,0 +1,1245 @@ +/* + * DRM based mode setting test program + * Copyright 2008 Tungsten Graphics + * Jakob Bornecrantz + * Copyright 2008 Intel Corporation + * Jesse Barnes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +/* + * This fairly simple test program dumps output in a similar format to the + * "xrandr" tool everyone knows & loves. It's necessarily slightly different + * since the kernel separates outputs into encoder and connector structures, + * each with their own unique ID. The program also allows test testing of the + * memory management and mode setting APIs by allowing the user to specify a + * connector and mode to use for mode setting. If all works as expected, a + * blue background should be painted on the monitor attached to the specified + * connector after the selected mode is set. + * + * TODO: use cairo to write the mode info on the selected output once + * the mode has been programmed, along with possible test patterns. + */ +#include "config.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xf86drm.h" +#include "xf86drmMode.h" +#include "drm_fourcc.h" +#include "libkms.h" + +#ifdef HAVE_CAIRO +#include +#include +#endif + +drmModeRes *resources; +int fd, modes; + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +struct type_name { + int type; + char *name; +}; + +#define type_name_fn(res) \ +char * res##_str(int type) { \ + unsigned int i; \ + for (i = 0; i < ARRAY_SIZE(res##_names); i++) { \ + if (res##_names[i].type == type) \ + return res##_names[i].name; \ + } \ + return "(invalid)"; \ +} + +struct type_name encoder_type_names[] = { + { DRM_MODE_ENCODER_NONE, "none" }, + { DRM_MODE_ENCODER_DAC, "DAC" }, + { DRM_MODE_ENCODER_TMDS, "TMDS" }, + { DRM_MODE_ENCODER_LVDS, "LVDS" }, + { DRM_MODE_ENCODER_TVDAC, "TVDAC" }, +}; + +type_name_fn(encoder_type) + +struct type_name connector_status_names[] = { + { DRM_MODE_CONNECTED, "connected" }, + { DRM_MODE_DISCONNECTED, "disconnected" }, + { DRM_MODE_UNKNOWNCONNECTION, "unknown" }, +}; + +type_name_fn(connector_status) + +struct type_name connector_type_names[] = { + { DRM_MODE_CONNECTOR_Unknown, "unknown" }, + { DRM_MODE_CONNECTOR_VGA, "VGA" }, + { DRM_MODE_CONNECTOR_DVII, "DVI-I" }, + { DRM_MODE_CONNECTOR_DVID, "DVI-D" }, + { DRM_MODE_CONNECTOR_DVIA, "DVI-A" }, + { DRM_MODE_CONNECTOR_Composite, "composite" }, + { DRM_MODE_CONNECTOR_SVIDEO, "s-video" }, + { DRM_MODE_CONNECTOR_LVDS, "LVDS" }, + { DRM_MODE_CONNECTOR_Component, "component" }, + { DRM_MODE_CONNECTOR_9PinDIN, "9-pin DIN" }, + { DRM_MODE_CONNECTOR_DisplayPort, "displayport" }, + { DRM_MODE_CONNECTOR_HDMIA, "HDMI-A" }, + { DRM_MODE_CONNECTOR_HDMIB, "HDMI-B" }, + { DRM_MODE_CONNECTOR_TV, "TV" }, + { DRM_MODE_CONNECTOR_eDP, "embedded displayport" }, +}; + +type_name_fn(connector_type) + +void dump_encoders(void) +{ + drmModeEncoder *encoder; + int i; + + printf("Encoders:\n"); + printf("id\tcrtc\ttype\tpossible crtcs\tpossible clones\t\n"); + for (i = 0; i < resources->count_encoders; i++) { + encoder = drmModeGetEncoder(fd, resources->encoders[i]); + + if (!encoder) { + fprintf(stderr, "could not get encoder %i: %s\n", + resources->encoders[i], strerror(errno)); + continue; + } + printf("%d\t%d\t%s\t0x%08x\t0x%08x\n", + encoder->encoder_id, + encoder->crtc_id, + encoder_type_str(encoder->encoder_type), + encoder->possible_crtcs, + encoder->possible_clones); + drmModeFreeEncoder(encoder); + } + printf("\n"); +} + +void dump_mode(drmModeModeInfo *mode) +{ + printf("\t%s %d %d %d %d %d %d %d %d %d\n", + mode->name, + mode->vrefresh, + mode->hdisplay, + mode->hsync_start, + mode->hsync_end, + mode->htotal, + mode->vdisplay, + mode->vsync_start, + mode->vsync_end, + mode->vtotal); +} + +static void +dump_blob(uint32_t blob_id) +{ + uint32_t i; + unsigned char *blob_data; + drmModePropertyBlobPtr blob; + + blob = drmModeGetPropertyBlob(fd, blob_id); + if (!blob) + return; + + blob_data = blob->data; + + for (i = 0; i < blob->length; i++) { + if (i % 16 == 0) + printf("\n\t\t\t"); + printf("%.2hhx", blob_data[i]); + } + printf("\n"); + + drmModeFreePropertyBlob(blob); +} + +static void +dump_prop(uint32_t prop_id, uint64_t value) +{ + int i; + drmModePropertyPtr prop; + + prop = drmModeGetProperty(fd, prop_id); + + printf("\t%d", prop_id); + if (!prop) { + printf("\n"); + return; + } + + printf(" %s:\n", prop->name); + + printf("\t\tflags:"); + if (prop->flags & DRM_MODE_PROP_PENDING) + printf(" pending"); + if (prop->flags & DRM_MODE_PROP_RANGE) + printf(" range"); + if (prop->flags & DRM_MODE_PROP_IMMUTABLE) + printf(" immutable"); + if (prop->flags & DRM_MODE_PROP_ENUM) + printf(" enum"); + if (prop->flags & DRM_MODE_PROP_BITMASK) + printf(" bitmask"); + if (prop->flags & DRM_MODE_PROP_BLOB) + printf(" blob"); + printf("\n"); + + if (prop->flags & DRM_MODE_PROP_RANGE) { + printf("\t\tvalues:"); + for (i = 0; i < prop->count_values; i++) + printf(" %"PRIu64, prop->values[i]); + printf("\n"); + } + + if (prop->flags & DRM_MODE_PROP_ENUM) { + printf("\t\tenums:"); + for (i = 0; i < prop->count_enums; i++) + printf(" %s=%llu", prop->enums[i].name, + prop->enums[i].value); + printf("\n"); + } else if (prop->flags & DRM_MODE_PROP_BITMASK) { + printf("\t\tvalues:"); + for (i = 0; i < prop->count_enums; i++) + printf(" %s=0x%llx", prop->enums[i].name, + (1LL << prop->enums[i].value)); + printf("\n"); + } else { + assert(prop->count_enums == 0); + } + + if (prop->flags & DRM_MODE_PROP_BLOB) { + printf("\t\tblobs:\n"); + for (i = 0; i < prop->count_blobs; i++) + dump_blob(prop->blob_ids[i]); + printf("\n"); + } else { + assert(prop->count_blobs == 0); + } + + printf("\t\tvalue:"); + if (prop->flags & DRM_MODE_PROP_BLOB) + dump_blob(value); + else + printf(" %"PRIu64"\n", value); + + drmModeFreeProperty(prop); +} + +void dump_connectors(void) +{ + drmModeConnector *connector; + int i, j; + + printf("Connectors:\n"); + printf("id\tencoder\tstatus\t\ttype\tsize (mm)\tmodes\tencoders\n"); + for (i = 0; i < resources->count_connectors; i++) { + connector = drmModeGetConnector(fd, resources->connectors[i]); + + if (!connector) { + fprintf(stderr, "could not get connector %i: %s\n", + resources->connectors[i], strerror(errno)); + continue; + } + + printf("%d\t%d\t%s\t%s\t%dx%d\t\t%d\t", + connector->connector_id, + connector->encoder_id, + connector_status_str(connector->connection), + connector_type_str(connector->connector_type), + connector->mmWidth, connector->mmHeight, + connector->count_modes); + + for (j = 0; j < connector->count_encoders; j++) + printf("%s%d", j > 0 ? ", " : "", connector->encoders[j]); + printf("\n"); + + if (connector->count_modes) { + printf(" modes:\n"); + printf("\tname refresh (Hz) hdisp hss hse htot vdisp " + "vss vse vtot)\n"); + for (j = 0; j < connector->count_modes; j++) + dump_mode(&connector->modes[j]); + + printf(" props:\n"); + for (j = 0; j < connector->count_props; j++) + dump_prop(connector->props[j], + connector->prop_values[j]); + } + + drmModeFreeConnector(connector); + } + printf("\n"); +} + +void dump_crtcs(void) +{ + drmModeCrtc *crtc; + drmModeObjectPropertiesPtr props; + int i; + uint32_t j; + + printf("CRTCs:\n"); + printf("id\tfb\tpos\tsize\n"); + for (i = 0; i < resources->count_crtcs; i++) { + crtc = drmModeGetCrtc(fd, resources->crtcs[i]); + + if (!crtc) { + fprintf(stderr, "could not get crtc %i: %s\n", + resources->crtcs[i], strerror(errno)); + continue; + } + printf("%d\t%d\t(%d,%d)\t(%dx%d)\n", + crtc->crtc_id, + crtc->buffer_id, + crtc->x, crtc->y, + crtc->width, crtc->height); + dump_mode(&crtc->mode); + + printf(" props:\n"); + props = drmModeObjectGetProperties(fd, crtc->crtc_id, + DRM_MODE_OBJECT_CRTC); + if (props) { + for (j = 0; j < props->count_props; j++) + dump_prop(props->props[j], + props->prop_values[j]); + drmModeFreeObjectProperties(props); + } else { + printf("\tcould not get crtc properties: %s\n", + strerror(errno)); + } + + drmModeFreeCrtc(crtc); + } + printf("\n"); +} + +void dump_framebuffers(void) +{ + drmModeFB *fb; + int i; + + printf("Frame buffers:\n"); + printf("id\tsize\tpitch\n"); + for (i = 0; i < resources->count_fbs; i++) { + fb = drmModeGetFB(fd, resources->fbs[i]); + + if (!fb) { + fprintf(stderr, "could not get fb %i: %s\n", + resources->fbs[i], strerror(errno)); + continue; + } + printf("%u\t(%ux%u)\t%u\n", + fb->fb_id, + fb->width, fb->height, + fb->pitch); + + drmModeFreeFB(fb); + } + printf("\n"); +} + +static void dump_planes(void) +{ + drmModeObjectPropertiesPtr props; + drmModePlaneRes *plane_resources; + drmModePlane *ovr; + unsigned int i, j; + + plane_resources = drmModeGetPlaneResources(fd); + if (!plane_resources) { + fprintf(stderr, "drmModeGetPlaneResources failed: %s\n", + strerror(errno)); + return; + } + + printf("Planes:\n"); + printf("id\tcrtc\tfb\tCRTC x,y\tx,y\tgamma size\n"); + for (i = 0; i < plane_resources->count_planes; i++) { + ovr = drmModeGetPlane(fd, plane_resources->planes[i]); + if (!ovr) { + fprintf(stderr, "drmModeGetPlane failed: %s\n", + strerror(errno)); + continue; + } + + printf("%d\t%d\t%d\t%d,%d\t\t%d,%d\t%d\n", + ovr->plane_id, ovr->crtc_id, ovr->fb_id, + ovr->crtc_x, ovr->crtc_y, ovr->x, ovr->y, + ovr->gamma_size); + + if (!ovr->count_formats) + continue; + + printf(" formats:"); + for (j = 0; j < ovr->count_formats; j++) + printf(" %4.4s", (char *)&ovr->formats[j]); + printf("\n"); + + printf(" props:\n"); + props = drmModeObjectGetProperties(fd, ovr->plane_id, + DRM_MODE_OBJECT_PLANE); + if (props) { + for (j = 0; j < props->count_props; j++) + dump_prop(props->props[j], + props->prop_values[j]); + drmModeFreeObjectProperties(props); + } else { + printf("\tcould not get plane properties: %s\n", + strerror(errno)); + } + + drmModeFreePlane(ovr); + } + printf("\n"); + + drmModeFreePlaneResources(plane_resources); + return; +} + +/* + * Mode setting with the kernel interfaces is a bit of a chore. + * First you have to find the connector in question and make sure the + * requested mode is available. + * Then you need to find the encoder attached to that connector so you + * can bind it with a free crtc. + */ +struct connector { + uint32_t id; + char mode_str[64]; + drmModeModeInfo *mode; + drmModeEncoder *encoder; + int crtc; + int pipe; + unsigned int fb_id[2], current_fb_id; + struct timeval start; + + int swap_count; +}; + +struct plane { + uint32_t con_id; /* the id of connector to bind to */ + uint32_t w, h; + unsigned int fb_id; + char format_str[5]; /* need to leave room for terminating \0 */ +}; + +static void +connector_find_mode(struct connector *c) +{ + drmModeConnector *connector; + int i, j; + + /* First, find the connector & mode */ + c->mode = NULL; + for (i = 0; i < resources->count_connectors; i++) { + connector = drmModeGetConnector(fd, resources->connectors[i]); + + if (!connector) { + fprintf(stderr, "could not get connector %i: %s\n", + resources->connectors[i], strerror(errno)); + drmModeFreeConnector(connector); + continue; + } + + if (!connector->count_modes) { + drmModeFreeConnector(connector); + continue; + } + + if (connector->connector_id != c->id) { + drmModeFreeConnector(connector); + continue; + } + + for (j = 0; j < connector->count_modes; j++) { + c->mode = &connector->modes[j]; + if (!strcmp(c->mode->name, c->mode_str)) + break; + } + + /* Found it, break out */ + if (c->mode) + break; + + drmModeFreeConnector(connector); + } + + if (!c->mode) { + fprintf(stderr, "failed to find mode \"%s\"\n", c->mode_str); + return; + } + + /* Now get the encoder */ + for (i = 0; i < resources->count_encoders; i++) { + c->encoder = drmModeGetEncoder(fd, resources->encoders[i]); + + if (!c->encoder) { + fprintf(stderr, "could not get encoder %i: %s\n", + resources->encoders[i], strerror(errno)); + drmModeFreeEncoder(c->encoder); + continue; + } + + if (c->encoder->encoder_id == connector->encoder_id) + break; + + drmModeFreeEncoder(c->encoder); + } + + if (c->crtc == -1) + c->crtc = c->encoder->crtc_id; + + /* and figure out which crtc index it is: */ + for (i = 0; i < resources->count_crtcs; i++) { + if (c->crtc == resources->crtcs[i]) { + c->pipe = i; + break; + } + } + +} + +static struct kms_bo * +allocate_buffer(struct kms_driver *kms, + int width, int height, int *stride) +{ + struct kms_bo *bo; + unsigned bo_attribs[] = { + KMS_WIDTH, 0, + KMS_HEIGHT, 0, + KMS_BO_TYPE, KMS_BO_TYPE_SCANOUT_X8R8G8B8, + KMS_TERMINATE_PROP_LIST + }; + int ret; + + bo_attribs[1] = width; + bo_attribs[3] = height; + + ret = kms_bo_create(kms, bo_attribs, &bo); + if (ret) { + fprintf(stderr, "failed to alloc buffer: %s\n", + strerror(-ret)); + return NULL; + } + + ret = kms_bo_get_prop(bo, KMS_PITCH, stride); + if (ret) { + fprintf(stderr, "failed to retreive buffer stride: %s\n", + strerror(-ret)); + kms_bo_destroy(&bo); + return NULL; + } + + return bo; +} + +static void +make_pwetty(void *data, int width, int height, int stride) +{ +#ifdef HAVE_CAIRO + cairo_surface_t *surface; + cairo_t *cr; + int x, y; + + surface = cairo_image_surface_create_for_data(data, + CAIRO_FORMAT_ARGB32, + width, height, + stride); + cr = cairo_create(surface); + cairo_surface_destroy(surface); + + cairo_set_line_cap(cr, CAIRO_LINE_CAP_SQUARE); + for (x = 0; x < width; x += 250) + for (y = 0; y < height; y += 250) { + char buf[64]; + + cairo_move_to(cr, x, y - 20); + cairo_line_to(cr, x, y + 20); + cairo_move_to(cr, x - 20, y); + cairo_line_to(cr, x + 20, y); + cairo_new_sub_path(cr); + cairo_arc(cr, x, y, 10, 0, M_PI * 2); + cairo_set_line_width(cr, 4); + cairo_set_source_rgb(cr, 0, 0, 0); + cairo_stroke_preserve(cr); + cairo_set_source_rgb(cr, 1, 1, 1); + cairo_set_line_width(cr, 2); + cairo_stroke(cr); + + snprintf(buf, sizeof buf, "%d, %d", x, y); + cairo_move_to(cr, x + 20, y + 20); + cairo_text_path(cr, buf); + cairo_set_source_rgb(cr, 0, 0, 0); + cairo_stroke_preserve(cr); + cairo_set_source_rgb(cr, 1, 1, 1); + cairo_fill(cr); + } + + cairo_destroy(cr); +#endif +} + +static int +create_test_buffer(struct kms_driver *kms, + int width, int height, int *stride_out, + struct kms_bo **bo_out) +{ + struct kms_bo *bo; + int ret, i, j, stride; + void *virtual; + + bo = allocate_buffer(kms, width, height, &stride); + if (!bo) + return -1; + + ret = kms_bo_map(bo, &virtual); + if (ret) { + fprintf(stderr, "failed to map buffer: %s\n", + strerror(-ret)); + kms_bo_destroy(&bo); + return -1; + } + + /* paint the buffer with colored tiles */ + for (j = 0; j < height; j++) { + uint32_t *fb_ptr = (uint32_t*)((char*)virtual + j * stride); + for (i = 0; i < width; i++) { + div_t d = div(i, width); + fb_ptr[i] = + 0x00130502 * (d.quot >> 6) + + 0x000a1120 * (d.rem >> 6); + } + } + + make_pwetty(virtual, width, height, stride); + + kms_bo_unmap(bo); + + *bo_out = bo; + *stride_out = stride; + return 0; +} + +static int +create_grey_buffer(struct kms_driver *kms, + int width, int height, int *stride_out, + struct kms_bo **bo_out) +{ + struct kms_bo *bo; + int size, ret, stride; + void *virtual; + + bo = allocate_buffer(kms, width, height, &stride); + if (!bo) + return -1; + + ret = kms_bo_map(bo, &virtual); + if (ret) { + fprintf(stderr, "failed to map buffer: %s\n", + strerror(-ret)); + kms_bo_destroy(&bo); + return -1; + } + + size = stride * height; + memset(virtual, 0x77, size); + kms_bo_unmap(bo); + + *bo_out = bo; + *stride_out = stride; + + return 0; +} + +void +page_flip_handler(int fd, unsigned int frame, + unsigned int sec, unsigned int usec, void *data) +{ + struct connector *c; + unsigned int new_fb_id; + struct timeval end; + double t; + + c = data; + if (c->current_fb_id == c->fb_id[0]) + new_fb_id = c->fb_id[1]; + else + new_fb_id = c->fb_id[0]; + + drmModePageFlip(fd, c->crtc, new_fb_id, + DRM_MODE_PAGE_FLIP_EVENT, c); + c->current_fb_id = new_fb_id; + c->swap_count++; + if (c->swap_count == 60) { + gettimeofday(&end, NULL); + t = end.tv_sec + end.tv_usec * 1e-6 - + (c->start.tv_sec + c->start.tv_usec * 1e-6); + fprintf(stderr, "freq: %.02fHz\n", c->swap_count / t); + c->swap_count = 0; + c->start = end; + } +} + +/* swap these for big endian.. */ +#define RED 2 +#define GREEN 1 +#define BLUE 0 + +static void +fill420(unsigned char *y, unsigned char *u, unsigned char *v, + int cs /*chroma pixel stride */, + int n, int width, int height, int stride) +{ + int i, j; + + /* paint the buffer with colored tiles, in blocks of 2x2 */ + for (j = 0; j < height; j+=2) { + unsigned char *y1p = y + j * stride; + unsigned char *y2p = y1p + stride; + unsigned char *up = u + (j/2) * stride * cs / 2; + unsigned char *vp = v + (j/2) * stride * cs / 2; + + for (i = 0; i < width; i+=2) { + div_t d = div(n+i+j, width); + uint32_t rgb = 0x00130502 * (d.quot >> 6) + 0x000a1120 * (d.rem >> 6); + unsigned char *rgbp = (unsigned char *)&rgb; + unsigned char y = (0.299 * rgbp[RED]) + (0.587 * rgbp[GREEN]) + (0.114 * rgbp[BLUE]); + + *(y2p++) = *(y1p++) = y; + *(y2p++) = *(y1p++) = y; + + *up = (rgbp[BLUE] - y) * 0.565 + 128; + *vp = (rgbp[RED] - y) * 0.713 + 128; + up += cs; + vp += cs; + } + } +} + +static void +fill422(unsigned char *virtual, int n, int width, int height, int stride) +{ + int i, j; + /* paint the buffer with colored tiles */ + for (j = 0; j < height; j++) { + uint8_t *ptr = (uint8_t*)((char*)virtual + j * stride); + for (i = 0; i < width; i++) { + div_t d = div(n+i+j, width); + uint32_t rgb = 0x00130502 * (d.quot >> 6) + 0x000a1120 * (d.rem >> 6); + unsigned char *rgbp = (unsigned char *)&rgb; + unsigned char y = (0.299 * rgbp[RED]) + (0.587 * rgbp[GREEN]) + (0.114 * rgbp[BLUE]); + + *(ptr++) = y; + *(ptr++) = (rgbp[BLUE] - y) * 0.565 + 128; + *(ptr++) = y; + *(ptr++) = (rgbp[RED] - y) * 0.713 + 128; + } + } +} + +static void +fill1555(unsigned char *virtual, int n, int width, int height, int stride) +{ + int i, j; + /* paint the buffer with colored tiles */ + for (j = 0; j < height; j++) { + uint16_t *ptr = (uint16_t*)((char*)virtual + j * stride); + for (i = 0; i < width; i++) { + div_t d = div(n+i+j, width); + uint32_t rgb = 0x00130502 * (d.quot >> 6) + 0x000a1120 * (d.rem >> 6); + unsigned char *rgbp = (unsigned char *)&rgb; + + *(ptr++) = 0x8000 | + (rgbp[RED] >> 3) << 10 | + (rgbp[GREEN] >> 3) << 5 | + (rgbp[BLUE] >> 3); + } + } +} + +static int +set_plane(struct kms_driver *kms, struct connector *c, struct plane *p) +{ + drmModePlaneRes *plane_resources; + drmModePlane *ovr; + uint32_t handles[4], pitches[4], offsets[4] = {0}; /* we only use [0] */ + uint32_t plane_id = 0; + struct kms_bo *plane_bo; + uint32_t plane_flags = 0, format; + int ret, crtc_x, crtc_y, crtc_w, crtc_h; + unsigned int i; + + /* find an unused plane which can be connected to our crtc */ + plane_resources = drmModeGetPlaneResources(fd); + if (!plane_resources) { + fprintf(stderr, "drmModeGetPlaneResources failed: %s\n", + strerror(errno)); + return -1; + } + + for (i = 0; i < plane_resources->count_planes && !plane_id; i++) { + ovr = drmModeGetPlane(fd, plane_resources->planes[i]); + if (!ovr) { + fprintf(stderr, "drmModeGetPlane failed: %s\n", + strerror(errno)); + return -1; + } + + if ((ovr->possible_crtcs & (1 << c->pipe)) && !ovr->crtc_id) + plane_id = ovr->plane_id; + + drmModeFreePlane(ovr); + } + + fprintf(stderr, "testing %dx%d@%s overlay plane\n", + p->w, p->h, p->format_str); + + if (!plane_id) { + fprintf(stderr, "failed to find plane!\n"); + return -1; + } + + if (!strcmp(p->format_str, "XR24")) { + if (create_test_buffer(kms, p->w, p->h, &pitches[0], &plane_bo)) + return -1; + kms_bo_get_prop(plane_bo, KMS_HANDLE, &handles[0]); + format = DRM_FORMAT_XRGB8888; + } else { + void *virtual; + + /* TODO: this always allocates a buffer for 32bpp RGB.. but for + * YUV formats, we don't use all of it.. since 4bytes/pixel is + * worst case, so live with it for now and just don't use all + * the buffer: + */ + plane_bo = allocate_buffer(kms, p->w, p->h, &pitches[0]); + if (!plane_bo) + return -1; + + ret = kms_bo_map(plane_bo, &virtual); + if (ret) { + fprintf(stderr, "failed to map buffer: %s\n", + strerror(-ret)); + kms_bo_destroy(&plane_bo); + return -1; + } + + /* just testing a limited # of formats to test single + * and multi-planar path.. would be nice to add more.. + */ + if (!strcmp(p->format_str, "YUYV")) { + pitches[0] = p->w * 2; + offsets[0] = 0; + kms_bo_get_prop(plane_bo, KMS_HANDLE, &handles[0]); + + fill422(virtual, 0, p->w, p->h, pitches[0]); + + format = DRM_FORMAT_YUYV; + } else if (!strcmp(p->format_str, "NV12")) { + pitches[0] = p->w; + offsets[0] = 0; + kms_bo_get_prop(plane_bo, KMS_HANDLE, &handles[0]); + pitches[1] = p->w; + offsets[1] = p->w * p->h; + kms_bo_get_prop(plane_bo, KMS_HANDLE, &handles[1]); + + fill420(virtual, virtual+offsets[1], virtual+offsets[1]+1, + 2, 0, p->w, p->h, pitches[0]); + + format = DRM_FORMAT_NV12; + } else if (!strcmp(p->format_str, "YV12")) { + pitches[0] = p->w; + offsets[0] = 0; + kms_bo_get_prop(plane_bo, KMS_HANDLE, &handles[0]); + pitches[1] = p->w / 2; + offsets[1] = p->w * p->h; + kms_bo_get_prop(plane_bo, KMS_HANDLE, &handles[1]); + pitches[2] = p->w / 2; + offsets[2] = offsets[1] + (p->w * p->h) / 4; + kms_bo_get_prop(plane_bo, KMS_HANDLE, &handles[2]); + + fill420(virtual, virtual+offsets[1], virtual+offsets[2], + 1, 0, p->w, p->h, pitches[0]); + + format = DRM_FORMAT_YVU420; + } else if (!strcmp(p->format_str, "XR15")) { + pitches[0] = p->w * 2; + offsets[0] = 0; + kms_bo_get_prop(plane_bo, KMS_HANDLE, &handles[0]); + + fill1555(virtual, 0, p->w, p->h, pitches[0]); + + format = DRM_FORMAT_XRGB1555; + } else if (!strcmp(p->format_str, "AR15")) { + pitches[0] = p->w * 2; + offsets[0] = 0; + kms_bo_get_prop(plane_bo, KMS_HANDLE, &handles[0]); + + fill1555(virtual, 0, p->w, p->h, pitches[0]); + + format = DRM_FORMAT_ARGB1555; + } else { + fprintf(stderr, "Unknown format: %s\n", p->format_str); + return -1; + } + + kms_bo_unmap(plane_bo); + } + + /* just use single plane format for now.. */ + if (drmModeAddFB2(fd, p->w, p->h, format, + handles, pitches, offsets, &p->fb_id, plane_flags)) { + fprintf(stderr, "failed to add fb: %s\n", strerror(errno)); + return -1; + } + + /* ok, boring.. but for now put in middle of screen: */ + crtc_x = c->mode->hdisplay / 3; + crtc_y = c->mode->vdisplay / 3; + crtc_w = crtc_x; + crtc_h = crtc_y; + + /* note src coords (last 4 args) are in Q16 format */ + if (drmModeSetPlane(fd, plane_id, c->crtc, p->fb_id, + plane_flags, crtc_x, crtc_y, crtc_w, crtc_h, + 0, 0, p->w << 16, p->h << 16)) { + fprintf(stderr, "failed to enable plane: %s\n", + strerror(errno)); + return -1; + } + + return 0; +} + +static void +set_mode(struct connector *c, int count, struct plane *p, int plane_count, + int page_flip) +{ + struct kms_driver *kms; + struct kms_bo *bo, *other_bo; + unsigned int fb_id, other_fb_id; + int i, j, ret, width, height, x, stride; + unsigned handle; + drmEventContext evctx; + + width = 0; + height = 0; + for (i = 0; i < count; i++) { + connector_find_mode(&c[i]); + if (c[i].mode == NULL) + continue; + width += c[i].mode->hdisplay; + if (height < c[i].mode->vdisplay) + height = c[i].mode->vdisplay; + } + + ret = kms_create(fd, &kms); + if (ret) { + fprintf(stderr, "failed to create kms driver: %s\n", + strerror(-ret)); + return; + } + + if (create_test_buffer(kms, width, height, &stride, &bo)) + return; + + kms_bo_get_prop(bo, KMS_HANDLE, &handle); + ret = drmModeAddFB(fd, width, height, 24, 32, stride, handle, &fb_id); + if (ret) { + fprintf(stderr, "failed to add fb (%ux%u): %s\n", + width, height, strerror(errno)); + return; + } + + x = 0; + for (i = 0; i < count; i++) { + if (c[i].mode == NULL) + continue; + + printf("setting mode %s on connector %d, crtc %d\n", + c[i].mode_str, c[i].id, c[i].crtc); + + ret = drmModeSetCrtc(fd, c[i].crtc, fb_id, x, 0, + &c[i].id, 1, c[i].mode); + + /* XXX: Actually check if this is needed */ + drmModeDirtyFB(fd, fb_id, NULL, 0); + + x += c[i].mode->hdisplay; + + if (ret) { + fprintf(stderr, "failed to set mode: %s\n", strerror(errno)); + return; + } + + /* if we have a plane/overlay to show, set that up now: */ + for (j = 0; j < plane_count; j++) + if (p[j].con_id == c[i].id) + if (set_plane(kms, &c[i], &p[j])) + return; + } + + if (!page_flip) + return; + + if (create_grey_buffer(kms, width, height, &stride, &other_bo)) + return; + + kms_bo_get_prop(other_bo, KMS_HANDLE, &handle); + ret = drmModeAddFB(fd, width, height, 32, 32, stride, handle, + &other_fb_id); + if (ret) { + fprintf(stderr, "failed to add fb: %s\n", strerror(errno)); + return; + } + + for (i = 0; i < count; i++) { + if (c[i].mode == NULL) + continue; + + ret = drmModePageFlip(fd, c[i].crtc, other_fb_id, + DRM_MODE_PAGE_FLIP_EVENT, &c[i]); + if (ret) { + fprintf(stderr, "failed to page flip: %s\n", strerror(errno)); + return; + } + gettimeofday(&c[i].start, NULL); + c[i].swap_count = 0; + c[i].fb_id[0] = fb_id; + c[i].fb_id[1] = other_fb_id; + c[i].current_fb_id = other_fb_id; + } + + memset(&evctx, 0, sizeof evctx); + evctx.version = DRM_EVENT_CONTEXT_VERSION; + evctx.vblank_handler = NULL; + evctx.page_flip_handler = page_flip_handler; + + while (1) { +#if 0 + struct pollfd pfd[2]; + + pfd[0].fd = 0; + pfd[0].events = POLLIN; + pfd[1].fd = fd; + pfd[1].events = POLLIN; + + if (poll(pfd, 2, -1) < 0) { + fprintf(stderr, "poll error\n"); + break; + } + + if (pfd[0].revents) + break; +#else + struct timeval timeout = { .tv_sec = 3, .tv_usec = 0 }; + fd_set fds; + int ret; + + FD_ZERO(&fds); + FD_SET(0, &fds); + FD_SET(fd, &fds); + ret = select(fd + 1, &fds, NULL, NULL, &timeout); + + if (ret <= 0) { + fprintf(stderr, "select timed out or error (ret %d)\n", + ret); + continue; + } else if (FD_ISSET(0, &fds)) { + break; + } +#endif + + drmHandleEvent(fd, &evctx); + } + + kms_bo_destroy(&bo); + kms_bo_destroy(&other_bo); + kms_destroy(&kms); +} + +extern char *optarg; +extern int optind, opterr, optopt; +static char optstr[] = "ecpmfs:P:v"; + +void usage(char *name) +{ + fprintf(stderr, "usage: %s [-ecpmf]\n", name); + fprintf(stderr, "\t-e\tlist encoders\n"); + fprintf(stderr, "\t-c\tlist connectors\n"); + fprintf(stderr, "\t-p\tlist CRTCs and planes (pipes)\n"); + fprintf(stderr, "\t-m\tlist modes\n"); + fprintf(stderr, "\t-f\tlist framebuffers\n"); + fprintf(stderr, "\t-v\ttest vsynced page flipping\n"); + fprintf(stderr, "\t-s :\tset a mode\n"); + fprintf(stderr, "\t-s @:\tset a mode\n"); + fprintf(stderr, "\t-P :x\tset a plane\n"); + fprintf(stderr, "\t-P :x@\tset a plane\n"); + fprintf(stderr, "\n\tDefault is to dump all info.\n"); + exit(0); +} + +#define dump_resource(res) if (res) dump_##res() + +static int page_flipping_supported(void) +{ + /*FIXME: generic ioctl needed? */ + return 1; +#if 0 + int ret, value; + struct drm_i915_getparam gp; + + gp.param = I915_PARAM_HAS_PAGEFLIPPING; + gp.value = &value; + + ret = drmCommandWriteRead(fd, DRM_I915_GETPARAM, &gp, sizeof(gp)); + if (ret) { + fprintf(stderr, "drm_i915_getparam: %m\n"); + return 0; + } + + return *gp.value; +#endif +} + +int main(int argc, char **argv) +{ + int c; + int encoders = 0, connectors = 0, crtcs = 0, planes = 0, framebuffers = 0; + int test_vsync = 0; + char *modules[] = { "i915", "radeon", "nouveau", "vmwgfx", "omapdrm", "exynos" }; + unsigned int i; + int count = 0, plane_count = 0; + struct connector con_args[2]; + struct plane plane_args[2] = {0}; + + opterr = 0; + while ((c = getopt(argc, argv, optstr)) != -1) { + switch (c) { + case 'e': + encoders = 1; + break; + case 'c': + connectors = 1; + break; + case 'p': + crtcs = 1; + planes = 1; + break; + case 'm': + modes = 1; + break; + case 'f': + framebuffers = 1; + break; + case 'v': + test_vsync = 1; + break; + case 's': + con_args[count].crtc = -1; + if (sscanf(optarg, "%d:%64s", + &con_args[count].id, + con_args[count].mode_str) != 2 && + sscanf(optarg, "%d@%d:%64s", + &con_args[count].id, + &con_args[count].crtc, + con_args[count].mode_str) != 3) + usage(argv[0]); + count++; + break; + case 'P': + strcpy(plane_args[plane_count].format_str, "XR24"); + if (sscanf(optarg, "%d:%dx%d@%4s", + &plane_args[plane_count].con_id, + &plane_args[plane_count].w, + &plane_args[plane_count].h, + plane_args[plane_count].format_str) != 4 && + sscanf(optarg, "%d:%dx%d", + &plane_args[plane_count].con_id, + &plane_args[plane_count].w, + &plane_args[plane_count].h) != 3) + usage(argv[0]); + plane_count++; + break; + default: + usage(argv[0]); + break; + } + } + + if (argc == 1) + encoders = connectors = crtcs = planes = modes = framebuffers = 1; + + for (i = 0; i < ARRAY_SIZE(modules); i++) { + printf("trying to load module %s...", modules[i]); + fd = drmOpen(modules[i], NULL); + if (fd < 0) { + printf("failed.\n"); + } else { + printf("success.\n"); + break; + } + } + + if (test_vsync && !page_flipping_supported()) { + fprintf(stderr, "page flipping not supported by drm.\n"); + return -1; + } + + if (i == ARRAY_SIZE(modules)) { + fprintf(stderr, "failed to load any modules, aborting.\n"); + return -1; + } + + resources = drmModeGetResources(fd); + if (!resources) { + fprintf(stderr, "drmModeGetResources failed: %s\n", + strerror(errno)); + drmClose(fd); + return 1; + } + + dump_resource(encoders); + dump_resource(connectors); + dump_resource(crtcs); + dump_resource(planes); + dump_resource(framebuffers); + + if (count > 0) { + set_mode(con_args, count, plane_args, plane_count, test_vsync); + getchar(); + } + + drmModeFreeResources(resources); + + return 0; +} diff --git a/tests/name_from_fd.c b/tests/name_from_fd.c new file mode 100644 index 0000000..330c8ff --- /dev/null +++ b/tests/name_from_fd.c @@ -0,0 +1,58 @@ +/* + * Copyright © 2009 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Kristian Høgsberg + * + */ + +#include +#include +#include +#include "drmtest.h" + +/** + * Checks drmGetDeviceNameFromFd + * + * This tests that we can get the actual version out, and that setting invalid + * major/minor numbers fails appropriately. It does not check the actual + * behavior differenses resulting from an increased DI version. + */ +int main(int argc, char **argv) +{ + int fd, ret; + drm_set_version_t sv, version; + const char *name = "/dev/dri/card0"; + char *v; + + fd = open("/dev/dri/card0", O_RDWR); + if (fd == -1) + return 0; + + v = drmGetDeviceNameFromFd(fd); + close(fd); + + assert(strcmp(name, v) == 0); + drmFree(v); + + return 0; +} diff --git a/tests/openclose.c b/tests/openclose.c new file mode 100644 index 0000000..946a445 --- /dev/null +++ b/tests/openclose.c @@ -0,0 +1,37 @@ +/* + * Copyright © 2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include "drmtest.h" + +int main(int argc, char **argv) +{ + int fd; + + fd = drm_open_any(); + close(fd); + return 0; +} diff --git a/tests/proptest/Makefile.am b/tests/proptest/Makefile.am new file mode 100644 index 0000000..f81a3c0 --- /dev/null +++ b/tests/proptest/Makefile.am @@ -0,0 +1,11 @@ +AM_CFLAGS = \ + -I$(top_srcdir)/include/drm \ + -I$(top_srcdir) + +noinst_PROGRAMS = \ + proptest + +proptest_SOURCES = \ + proptest.c +proptest_LDADD = \ + $(top_builddir)/libdrm.la diff --git a/tests/proptest/proptest.c b/tests/proptest/proptest.c new file mode 100644 index 0000000..c6684eb --- /dev/null +++ b/tests/proptest/proptest.c @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2012 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Paulo Zanoni + * + */ + +#include +#include +#include +#include +#include +#include + +#include "xf86drm.h" +#include "xf86drmMode.h" + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +int fd; +drmModeResPtr res = NULL; +drmModePlaneResPtr plane_res = NULL; + +const char *connector_type_str(uint32_t type) +{ + switch (type) { + case DRM_MODE_CONNECTOR_Unknown: + return "Unknown"; + case DRM_MODE_CONNECTOR_VGA: + return "VGA"; + case DRM_MODE_CONNECTOR_DVII: + return "DVI-I"; + case DRM_MODE_CONNECTOR_DVID: + return "DVI-D"; + case DRM_MODE_CONNECTOR_DVIA: + return "DVI-A"; + case DRM_MODE_CONNECTOR_Composite: + return "Composite"; + case DRM_MODE_CONNECTOR_SVIDEO: + return "SVIDEO"; + case DRM_MODE_CONNECTOR_LVDS: + return "LVDS"; + case DRM_MODE_CONNECTOR_Component: + return "Component"; + case DRM_MODE_CONNECTOR_9PinDIN: + return "9PinDin"; + case DRM_MODE_CONNECTOR_DisplayPort: + return "DisplayPort"; + case DRM_MODE_CONNECTOR_HDMIA: + return "HDMI-A"; + case DRM_MODE_CONNECTOR_HDMIB: + return "HDMI-B"; + case DRM_MODE_CONNECTOR_TV: + return "TV"; + case DRM_MODE_CONNECTOR_eDP: + return "eDP"; + default: + return "Invalid"; + } +} + +/* dump_blob and dump_prop shamelessly copied from ../modetest/modetest.c */ +static void +dump_blob(uint32_t blob_id) +{ + uint32_t i; + unsigned char *blob_data; + drmModePropertyBlobPtr blob; + + blob = drmModeGetPropertyBlob(fd, blob_id); + if (!blob) + return; + + blob_data = blob->data; + + for (i = 0; i < blob->length; i++) { + if (i % 16 == 0) + printf("\n\t\t\t"); + printf("%.2hhx", blob_data[i]); + } + printf("\n"); + + drmModeFreePropertyBlob(blob); +} + +static void +dump_prop(uint32_t prop_id, uint64_t value) +{ + int i; + drmModePropertyPtr prop; + + prop = drmModeGetProperty(fd, prop_id); + + printf("\t%d", prop_id); + if (!prop) { + printf("\n"); + return; + } + + printf(" %s:\n", prop->name); + + printf("\t\tflags:"); + if (prop->flags & DRM_MODE_PROP_PENDING) + printf(" pending"); + if (prop->flags & DRM_MODE_PROP_RANGE) + printf(" range"); + if (prop->flags & DRM_MODE_PROP_IMMUTABLE) + printf(" immutable"); + if (prop->flags & DRM_MODE_PROP_ENUM) + printf(" enum"); + if (prop->flags & DRM_MODE_PROP_BITMASK) + printf(" bitmask"); + if (prop->flags & DRM_MODE_PROP_BLOB) + printf(" blob"); + printf("\n"); + + if (prop->flags & DRM_MODE_PROP_RANGE) { + printf("\t\tvalues:"); + for (i = 0; i < prop->count_values; i++) + printf(" %"PRIu64, prop->values[i]); + printf("\n"); + } + + if (prop->flags & DRM_MODE_PROP_ENUM) { + printf("\t\tenums:"); + for (i = 0; i < prop->count_enums; i++) + printf(" %s=%llu", prop->enums[i].name, + prop->enums[i].value); + printf("\n"); + } else if (prop->flags & DRM_MODE_PROP_BITMASK) { + printf("\t\tvalues:"); + for (i = 0; i < prop->count_enums; i++) + printf(" %s=0x%llx", prop->enums[i].name, + (1LL << prop->enums[i].value)); + printf("\n"); + } else { + assert(prop->count_enums == 0); + } + + if (prop->flags & DRM_MODE_PROP_BLOB) { + printf("\t\tblobs:"); + for (i = 0; i < prop->count_blobs; i++) + dump_blob(prop->blob_ids[i]); + printf("\n"); + } else { + assert(prop->count_blobs == 0); + } + + printf("\t\tvalue:"); + if (prop->flags & DRM_MODE_PROP_BLOB) { + dump_blob(value); + printf("\n"); + } else { + printf(" %"PRIu64"\n", value); + } + + drmModeFreeProperty(prop); +} + +static void listObjectProperties(uint32_t id, uint32_t type) +{ + unsigned int i; + drmModeObjectPropertiesPtr props; + + props = drmModeObjectGetProperties(fd, id, type); + + if (!props) { + printf("\tNo properties: %s.\n", strerror(errno)); + return; + } + + for (i = 0; i < props->count_props; i++) + dump_prop(props->props[i], props->prop_values[i]); + + drmModeFreeObjectProperties(props); +} + +static void listConnectorProperties(void) +{ + int i; + drmModeConnectorPtr c; + + for (i = 0; i < res->count_connectors; i++) { + c = drmModeGetConnector(fd, res->connectors[i]); + + if (!c) { + fprintf(stderr, "Could not get connector %u: %s\n", + res->connectors[i], strerror(errno)); + continue; + } + + printf("Connector %u (%s-%u)\n", c->connector_id, + connector_type_str(c->connector_type), + c->connector_type_id); + + listObjectProperties(c->connector_id, + DRM_MODE_OBJECT_CONNECTOR); + + drmModeFreeConnector(c); + } +} + +static void listCrtcProperties(void) +{ + int i; + drmModeCrtcPtr c; + + for (i = 0; i < res->count_crtcs; i++) { + c = drmModeGetCrtc(fd, res->crtcs[i]); + + if (!c) { + fprintf(stderr, "Could not get crtc %u: %s\n", + res->crtcs[i], strerror(errno)); + continue; + } + + printf("CRTC %u\n", c->crtc_id); + + listObjectProperties(c->crtc_id, DRM_MODE_OBJECT_CRTC); + + drmModeFreeCrtc(c); + } +} + +static void listPlaneProperties(void) +{ + int i; + drmModePlanePtr p; + + for (i = 0; i < plane_res->count_planes; i++) { + p = drmModeGetPlane(fd, plane_res->planes[i]); + + if (!p) { + fprintf(stderr, "Could not get plane %u: %s\n", + plane_res->planes[i], strerror(errno)); + continue; + } + + printf("Plane %u\n", p->plane_id); + + listObjectProperties(p->plane_id, DRM_MODE_OBJECT_PLANE); + + drmModeFreePlane(p); + } +} + +static void listAllProperties(void) +{ + listConnectorProperties(); + listCrtcProperties(); + listPlaneProperties(); +} + +static int setProperty(char *argv[]) +{ + uint32_t obj_id, obj_type, prop_id; + uint64_t value; + + obj_id = atoi(argv[1]); + + if (!strcmp(argv[2], "connector")) { + obj_type = DRM_MODE_OBJECT_CONNECTOR; + } else if (!strcmp(argv[2], "crtc")) { + obj_type = DRM_MODE_OBJECT_CRTC; + } else if (!strcmp(argv[2], "plane")) { + obj_type = DRM_MODE_OBJECT_PLANE; + } else { + fprintf(stderr, "Invalid object type.\n"); + return 1; + } + + prop_id = atoi(argv[3]); + value = atoll(argv[4]); + + return drmModeObjectSetProperty(fd, obj_id, obj_type, prop_id, value); +} + +static void printUsage(void) +{ + printf("Usage:\n" +" proptest\n" +" proptest [obj id] [obj type] [prop id] [value]\n" +"\n" +"The first form just prints all the existing properties. The second one is\n" +"used to set the value of a specified property. The object type can be one of\n" +"the following strings:\n" +" connector crtc plane\n" +"\n" +"Example:\n" +" proptest 7 connector 2 1\n" +"will set property 2 of connector 7 to 1\n"); +} + +int main(int argc, char *argv[]) +{ + char *modules[] = { "i915", "radeon", "nouveau", "vmwgfx", "omapdrm", "exynos" }; + unsigned int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(modules); i++){ + fd = drmOpen(modules[i], NULL); + if (fd >= 0) { + printf("Module %s loaded.\n", modules[i]); + break; + } + } + + if (i == ARRAY_SIZE(modules)) { + fprintf(stderr, "Failed to load drm modules.\n"); + return 1; + } + + res = drmModeGetResources(fd); + if (!res) { + fprintf(stderr, "Failed to get resources: %s\n", + strerror(errno)); + ret = 1; + goto done; + } + + plane_res = drmModeGetPlaneResources(fd); + if (!plane_res) { + fprintf(stderr, "Failed to get plane resources: %s\n", + strerror(errno)); + ret = 1; + goto done; + } + + if (argc < 2) { + listAllProperties(); + } else if (argc == 5) { + ret = setProperty(argv); + } else { + printUsage(); + ret = 1; + } + + drmModeFreeResources(res); +done: + drmClose(fd); + return ret; +} diff --git a/tests/radeon/Makefile.am b/tests/radeon/Makefile.am new file mode 100644 index 0000000..1775669 --- /dev/null +++ b/tests/radeon/Makefile.am @@ -0,0 +1,14 @@ +AM_CFLAGS = \ + -I $(top_srcdir)/include/drm \ + -I $(top_srcdir) + +LDADD = $(top_builddir)/libdrm.la + +noinst_PROGRAMS = \ + radeon_ttm + +radeon_ttm_SOURCES = \ + rbo.c \ + rbo.h \ + list.h \ + radeon_ttm.c diff --git a/tests/radeon/list.h b/tests/radeon/list.h new file mode 100644 index 0000000..305c903 --- /dev/null +++ b/tests/radeon/list.h @@ -0,0 +1,137 @@ +/* + * + * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND. USA. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ + +/** + * \file + * List macros heavily inspired by the Linux kernel + * list handling. No list looping yet. + * + * Is not threadsafe, so common operations need to + * be protected using an external mutex. + */ +#ifndef _U_DOUBLE_LIST_H_ +#define _U_DOUBLE_LIST_H_ + +#include + +struct list_head +{ + struct list_head *prev; + struct list_head *next; +}; + +static void list_inithead(struct list_head *item) +{ + item->prev = item; + item->next = item; +} + +static void list_add(struct list_head *item, struct list_head *list) +{ + item->prev = list; + item->next = list->next; + list->next->prev = item; + list->next = item; +} + +static void list_addtail(struct list_head *item, struct list_head *list) +{ + item->next = list; + item->prev = list->prev; + list->prev->next = item; + list->prev = item; +} + +static void list_replace(struct list_head *from, struct list_head *to) +{ + to->prev = from->prev; + to->next = from->next; + from->next->prev = to; + from->prev->next = to; +} + +static void list_del(struct list_head *item) +{ + item->prev->next = item->next; + item->next->prev = item->prev; +} + +static void list_delinit(struct list_head *item) +{ + item->prev->next = item->next; + item->next->prev = item->prev; + item->next = item; + item->prev = item; +} + +#define LIST_INITHEAD(__item) list_inithead(__item) +#define LIST_ADD(__item, __list) list_add(__item, __list) +#define LIST_ADDTAIL(__item, __list) list_addtail(__item, __list) +#define LIST_REPLACE(__from, __to) list_replace(__from, __to) +#define LIST_DEL(__item) list_del(__item) +#define LIST_DELINIT(__item) list_delinit(__item) + +#define LIST_ENTRY(__type, __item, __field) \ + ((__type *)(((char *)(__item)) - offsetof(__type, __field))) + +#define LIST_IS_EMPTY(__list) \ + ((__list)->next == (__list)) + +#ifndef container_of +#define container_of(ptr, sample, member) \ + (void *)((char *)(ptr) \ + - ((char *)&(sample)->member - (char *)(sample))) +#endif + +#define LIST_FOR_EACH_ENTRY(pos, head, member) \ + for (pos = container_of((head)->next, pos, member); \ + &pos->member != (head); \ + pos = container_of(pos->member.next, pos, member)) + +#define LIST_FOR_EACH_ENTRY_SAFE(pos, storage, head, member) \ + for (pos = container_of((head)->next, pos, member), \ + storage = container_of(pos->member.next, pos, member); \ + &pos->member != (head); \ + pos = storage, storage = container_of(storage->member.next, storage, member)) + +#define LIST_FOR_EACH_ENTRY_SAFE_REV(pos, storage, head, member) \ + for (pos = container_of((head)->prev, pos, member), \ + storage = container_of(pos->member.prev, pos, member); \ + &pos->member != (head); \ + pos = storage, storage = container_of(storage->member.prev, storage, member)) + +#define LIST_FOR_EACH_ENTRY_FROM(pos, start, head, member) \ + for (pos = container_of((start), pos, member); \ + &pos->member != (head); \ + pos = container_of(pos->member.next, pos, member)) + +#define LIST_FOR_EACH_ENTRY_FROM_REV(pos, start, head, member) \ + for (pos = container_of((start), pos, member); \ + &pos->member != (head); \ + pos = container_of(pos->member.prev, pos, member)) + +#endif /*_U_DOUBLE_LIST_H_*/ diff --git a/tests/radeon/radeon_ttm.c b/tests/radeon/radeon_ttm.c new file mode 100644 index 0000000..246fd99 --- /dev/null +++ b/tests/radeon/radeon_ttm.c @@ -0,0 +1,75 @@ +/* + * Copyright © 2011 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include +#include +#include "rbo.h" + +/* allocate as many single page bo to try to starve the kernel + * memory zone (below highmem) + */ +void ttm_starve_kernel_private_memory(int fd) +{ + struct list_head list; + struct rbo *bo, *tmp; + unsigned nbo = 0; + + printf("\n[%s]\n", __func__); + list_inithead(&list); + while (1) { + bo = rbo(fd, 0, 4096, 0, NULL); + if (bo == NULL) { + printf("failing after %d bo\n", nbo); + break; + } + nbo++; + list_add(&bo->list, &list); + } + LIST_FOR_EACH_ENTRY_SAFE(bo, tmp, &list, list) { + list_del(&bo->list); + rbo_decref(bo); + } +} + +int radeon_open_fd(void) +{ + return drmOpen("radeon", NULL); +} + +int main(void) +{ + int radeonfd; + + radeonfd = radeon_open_fd(); + if (radeonfd < 0) { + fprintf(stderr, "failed to open radeon fd\n"); + return -1; + } + + ttm_starve_kernel_private_memory(radeonfd); + + close(radeonfd); + return 0; +} diff --git a/tests/radeon/rbo.c b/tests/radeon/rbo.c new file mode 100644 index 0000000..70a288c --- /dev/null +++ b/tests/radeon/rbo.c @@ -0,0 +1,171 @@ +/* + * Copyright © 2011 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#define _FILE_OFFSET_BITS 64 +#include +#include +#include +#include +#include +#include "xf86drm.h" +#include "radeon_drm.h" +#include "rbo.h" + +struct rbo *rbo(int fd, unsigned handle, unsigned size, + unsigned alignment, void *ptr) +{ + struct rbo *bo; + int r; + + bo = calloc(1, sizeof(*bo)); + if (bo == NULL) { + return NULL; + } + list_inithead(&bo->list); + bo->fd = fd; + bo->size = size; + bo->handle = handle; + bo->refcount = 1; + bo->alignment = alignment; + + if (handle) { + struct drm_gem_open open_arg; + + memset(&open_arg, 0, sizeof(open_arg)); + open_arg.name = handle; + r = drmIoctl(fd, DRM_IOCTL_GEM_OPEN, &open_arg); + if (r != 0) { + free(bo); + return NULL; + } + bo->handle = open_arg.handle; + } else { + struct drm_radeon_gem_create args; + + args.size = size; + args.alignment = alignment; + args.initial_domain = RADEON_GEM_DOMAIN_CPU; + args.flags = 0; + args.handle = 0; + r = drmCommandWriteRead(fd, DRM_RADEON_GEM_CREATE, + &args, sizeof(args)); + bo->handle = args.handle; + if (r) { + fprintf(stderr, "Failed to allocate :\n"); + fprintf(stderr, " size : %d bytes\n", size); + fprintf(stderr, " alignment : %d bytes\n", alignment); + free(bo); + return NULL; + } + } + if (ptr) { + if (rbo_map(bo)) { + fprintf(stderr, "%s failed to copy data into bo\n", __func__); + return rbo_decref(bo); + } + memcpy(bo->data, ptr, size); + rbo_unmap(bo); + } + return bo; +} + +int rbo_map(struct rbo *bo) +{ + struct drm_radeon_gem_mmap args; + void *ptr; + int r; + + if (bo->mapcount++ != 0) { + return 0; + } + /* Zero out args to make valgrind happy */ + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + args.offset = 0; + args.size = (uint64_t)bo->size; + r = drmCommandWriteRead(bo->fd, DRM_RADEON_GEM_MMAP, + &args, sizeof(args)); + if (r) { + fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n", + bo, bo->handle, r); + return r; + } + ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, bo->fd, args.addr_ptr); + if (ptr == MAP_FAILED) { + fprintf(stderr, "%s failed to map bo\n", __func__); + return -errno; + } + bo->data = ptr; + return 0; +} + +void rbo_unmap(struct rbo *bo) +{ + if (--bo->mapcount > 0) { + return; + } + munmap(bo->data, bo->size); + bo->data = NULL; +} + +struct rbo *rbo_incref(struct rbo *bo) +{ + bo->refcount++; + return bo; +} + +struct rbo *rbo_decref(struct rbo *bo) +{ + struct drm_gem_close args; + + if (bo == NULL) + return NULL; + if (--bo->refcount > 0) { + return NULL; + } + + munmap(bo->data, bo->size); + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + drmIoctl(bo->fd, DRM_IOCTL_GEM_CLOSE, &args); + memset(bo, 0, sizeof(struct rbo)); + free(bo); + return NULL; +} + +int rbo_wait(struct rbo *bo) +{ + struct drm_radeon_gem_wait_idle args; + int ret; + + /* Zero out args to make valgrind happy */ + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + do { + ret = drmCommandWriteRead(bo->fd, DRM_RADEON_GEM_WAIT_IDLE, + &args, sizeof(args)); + } while (ret == -EBUSY); + return ret; +} diff --git a/tests/radeon/rbo.h b/tests/radeon/rbo.h new file mode 100644 index 0000000..c25c73a --- /dev/null +++ b/tests/radeon/rbo.h @@ -0,0 +1,50 @@ +/* + * Copyright © 2011 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef RBO_H +#define RBO_H + +#include "list.h" + +struct rbo { + struct list_head list; + int fd; + unsigned refcount; + unsigned mapcount; + unsigned handle; + unsigned size; + unsigned alignment; + void *data; +}; + +struct rbo *rbo(int fd, unsigned handle, unsigned size, + unsigned alignment, void *ptr); +int rbo_map(struct rbo *bo); +void rbo_unmap(struct rbo *bo); +struct rbo *rbo_incref(struct rbo *bo); +struct rbo *rbo_decref(struct rbo *bo); +int rbo_wait(struct rbo *bo); + +#endif diff --git a/tests/rottest/Makefile.am b/tests/rottest/Makefile.am new file mode 100644 index 0000000..966173f --- /dev/null +++ b/tests/rottest/Makefile.am @@ -0,0 +1,21 @@ +AM_CFLAGS = \ + -I$(top_srcdir)/include/drm \ + -I$(top_srcdir)/libkms/ \ + -I$(top_srcdir)/exynos/ \ + -I$(top_srcdir) \ + $(CAIRO_CFLAGS) + +noinst_PROGRAMS = \ + rottest + +rottest_SOURCES = \ + rottest.c \ + gem.c \ + util.c \ + rotator.c + +rottest_LDADD = \ + $(top_builddir)/libdrm.la \ + $(top_builddir)/libkms/libkms.la \ + $(top_builddir)/exynos/libdrm_exynos.la \ + $(CAIRO_LIBS) diff --git a/tests/rottest/gem.c b/tests/rottest/gem.c new file mode 100644 index 0000000..f5bf811 --- /dev/null +++ b/tests/rottest/gem.c @@ -0,0 +1,92 @@ +/* + * DRM based rotator test program + * Copyright 2012 Samsung Electronics + * YoungJun Cho + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "xf86drm.h" +#include "xf86drmMode.h" +#include "libkms.h" + +#include "exynos_drm.h" + +int exynos_gem_create(int fd, struct drm_exynos_gem_create *gem) +{ + int ret = 0; + + if (!gem) { + fprintf(stderr, "gem object is null.\n"); + return -EFAULT; + } + ret = ioctl(fd, DRM_IOCTL_EXYNOS_GEM_CREATE, gem); + if (ret < 0) + fprintf(stderr, "failed to create gem buffer: %s\n", + strerror(-ret)); + return ret; +} + +int exynos_gem_userptr(int fd, struct drm_exynos_gem_userptr *gem_userptr) +{ + int ret = 0; + + ret = ioctl(fd, DRM_IOCTL_EXYNOS_GEM_USERPTR, gem_userptr); + if (ret < 0) + fprintf(stderr, "failed to userptr: %s\n", strerror(-ret)); + return ret; +} + +int exynos_gem_mmap(int fd, struct drm_exynos_gem_mmap *in_mmap) +{ + int ret = 0; + + ret = ioctl(fd, DRM_IOCTL_EXYNOS_GEM_MMAP, in_mmap); + if (ret < 0) + fprintf(stderr, "failed to mmap: %s\n", strerror(-ret)); + return ret; +} + +int exynos_gem_close(int fd, struct drm_gem_close *gem_close) +{ + int ret = 0; + + ret = ioctl(fd, DRM_IOCTL_GEM_CLOSE, gem_close); + if (ret < 0) + fprintf(stderr, "failed to close: %s\n", strerror(-ret)); + return ret; +} + +int exynos_gem_cache_op(int fd, struct drm_exynos_gem_cache_op *cache_op) +{ + int ret = 0; + + ret = ioctl(fd, DRM_IOCTL_EXYNOS_GEM_CACHE_OP, cache_op); + if (ret < 0) + fprintf(stderr, "failed to cache op: %s\n", strerror(-ret)); + return ret; +} diff --git a/tests/rottest/gem.h b/tests/rottest/gem.h new file mode 100644 index 0000000..2a5ed1d --- /dev/null +++ b/tests/rottest/gem.h @@ -0,0 +1,12 @@ +#ifndef __GEM_H__ +#define __GEM_H__ + +extern int exynos_gem_create(int fd, struct drm_exynos_gem_create *gem); +extern int exynos_gem_userptr(int fd, + struct drm_exynos_gem_userptr *gem_userptr); +extern int exynos_gem_mmap(int fd, struct drm_exynos_gem_mmap *in_mmap); +extern int exynos_gem_close(int fd, struct drm_gem_close *gem_close); +extern int exynos_gem_cache_op(int fd, + struct drm_exynos_gem_cache_op *cache_op); + +#endif diff --git a/tests/rottest/rotator.c b/tests/rottest/rotator.c new file mode 100644 index 0000000..996385b --- /dev/null +++ b/tests/rottest/rotator.c @@ -0,0 +1,297 @@ +/* + * DRM based rotator test program + * Copyright 2012 Samsung Electronics + * YoungJun Cho + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "exynos_drm.h" +#include "rottest.h" +#include "gem.h" +#include "util.h" + +#include "drm_fourcc.h" + +static int exynos_drm_ipp_property(int fd, + struct drm_exynos_ipp_property *property, + struct drm_exynos_pos *pos, + struct drm_exynos_sz *sz) +{ + int ret = 0; + + memset(property, 0x00, sizeof(struct drm_exynos_ipp_property)); + + property->config[EXYNOS_DRM_OPS_SRC].ops_id = EXYNOS_DRM_OPS_SRC; + property->config[EXYNOS_DRM_OPS_SRC].flip = EXYNOS_DRM_FLIP_NONE; + property->config[EXYNOS_DRM_OPS_SRC].degree = EXYNOS_DRM_DEGREE_0; + property->config[EXYNOS_DRM_OPS_SRC].fmt = DRM_FORMAT_XRGB8888; + property->config[EXYNOS_DRM_OPS_SRC].pos = *pos; + property->config[EXYNOS_DRM_OPS_SRC].sz = *sz; + + property->config[EXYNOS_DRM_OPS_DST].ops_id = EXYNOS_DRM_OPS_DST; + property->config[EXYNOS_DRM_OPS_DST].flip = EXYNOS_DRM_FLIP_NONE; + property->config[EXYNOS_DRM_OPS_DST].degree = EXYNOS_DRM_DEGREE_90; + property->config[EXYNOS_DRM_OPS_DST].fmt = DRM_FORMAT_XRGB8888; + property->config[EXYNOS_DRM_OPS_DST].pos = *pos; + property->config[EXYNOS_DRM_OPS_DST].sz = *sz; + + ret = ioctl(fd, DRM_IOCTL_EXYNOS_IPP_PROPERTY, property); + if (ret) + fprintf(stderr, + "failed to DRM_IOCTL_EXYNOS_IPP_PROPERTY : %s\n", + strerror(errno)); + + return ret; +} + +static int exynos_drm_ipp_buf(int fd, struct drm_exynos_ipp_buf *buf, + enum drm_exynos_ops_id ops_id, + enum drm_exynos_ipp_buf_ctrl ctrl, + unsigned int gem_handle) +{ + int ret = 0; + + memset(buf, 0x00, sizeof(struct drm_exynos_ipp_buf)); + + buf->ops_id = ops_id; + buf->buf_ctrl = ctrl; + buf->user_data = 0; + buf->id = 0; + buf->handle[EXYNOS_DRM_PLANAR_Y] = gem_handle; + buf->handle[EXYNOS_DRM_PLANAR_CB] = 0; + buf->handle[EXYNOS_DRM_PLANAR_CR] = 0; + + ret = ioctl(fd, DRM_IOCTL_EXYNOS_IPP_BUF, buf); + if (ret) + fprintf(stderr, + "failed to DRM_IOCTL_EXYNOS_IPP_BUF[id:%d][ctrl:%d] : %s\n", + ops_id, ctrl, strerror(errno)); + + return ret; +} + +static int exynos_drm_ipp_ctrl(int fd, struct drm_exynos_ipp_ctrl *ctrl, + enum drm_exynos_ipp_cmd cmd, unsigned int use) +{ + int ret = 0; + + memset(ctrl, 0x00, sizeof(struct drm_exynos_ipp_ctrl)); + + ctrl->cmd = cmd; + ctrl->use = use; + + ret = ioctl(fd, DRM_IOCTL_EXYNOS_IPP_CTRL, ctrl); + if (ret) + fprintf(stderr, + "failed to DRM_IOCTL_EXYNOS_IPP_CTRL[cmd:%d][use:%d] : %s\n", + cmd, use, strerror(errno)); + + return ret; +} + +void rotator_set_mode(struct connector *c, int count, int page_flip, + long int *usec) +{ + struct drm_exynos_pos def_pos = {0, 0, 720, 1280}; + struct drm_exynos_sz def_sz = {720, 1280}; + struct drm_exynos_ipp_property property; + struct drm_exynos_ipp_buf buf1, buf2; + struct drm_exynos_ipp_ctrl ctrl; + unsigned int width, height, stride; + int ret, i, j, x; + struct drm_exynos_gem_create gem1, gem2; + struct drm_exynos_gem_mmap mmap1, mmap2; + void *usr_addr1, *usr_addr2; + struct timeval begin, end; + struct drm_gem_close args; + char filename[100]; + + /* For property */ + ret = exynos_drm_ipp_property(fd, &property, &def_pos, &def_sz); + if (ret) { + fprintf(stderr, "failed to ipp property\n"); + return; + } + + /* For mode */ + width = height = 0; + for (i = 0; i < count; i++) { + connector_find_mode(&c[i]); + if (c[i].mode == NULL) continue; + width += c[i].mode->hdisplay; + if (height < c[i].mode->vdisplay) height = c[i].mode->vdisplay; + } + stride = width * 4; + + /* For source buffer */ + ret = util_gem_create_mmap(fd, &gem1, &mmap1, stride * height); + if (ret) { + fprintf(stderr, "failed to gem create mmap: %s\n", + strerror(errno)); + if (ret == -1) return; + else if (ret == -2) goto err_gem_mmap1; + } + usr_addr1 = (void *)(unsigned long)mmap1.mapped; + + util_draw_buffer(usr_addr1, 1, width, height, stride, 0); + + sprintf(filename, "/opt/media/rot_src.bmp", j); + util_write_bmp(filename, usr_addr1, width, height); + + /* For destination buffer */ + ret = util_gem_create_mmap(fd, &gem2, &mmap2, stride * height); + if (ret) { + fprintf(stderr, "failed to gem create mmap: %s\n", + strerror(errno)); + if (ret == -1) goto err_gem_create2; + else if (ret == -2) goto err_gem_mmap2; + } + usr_addr2 = (void*)(unsigned long)mmap2.mapped; + + util_draw_buffer(usr_addr2, 0, 0, 0, 0, mmap2.size); + + sprintf(filename, "/opt/media/rot_dst.bmp", j); + util_write_bmp(filename, usr_addr2, height, width); + + /* For source buffer map to IPP */ + ret = exynos_drm_ipp_buf(fd, &buf1, EXYNOS_DRM_OPS_SRC, + IPP_BUF_CTRL_MAP, gem1.handle); + if (ret) { + fprintf(stderr, "failed to ipp buf src map\n"); + goto err_ipp_buf_map1; + } + + /* For destination buffer map to IPP */ + ret = exynos_drm_ipp_buf(fd, &buf2, EXYNOS_DRM_OPS_DST, + IPP_BUF_CTRL_MAP, gem2.handle); + if (ret) { + fprintf(stderr, "failed to ipp buf dst map\n"); + goto err_ipp_buf_map2; + } + + for (j = 0; j < MAX_LOOP; j++) { + /* Start */ + gettimeofday(&begin, NULL); + ret = exynos_drm_ipp_ctrl(fd, &ctrl, IPP_CMD_M2M, 1); + if (ret) { + fprintf(stderr, + "failed to ipp ctrl IPP_CMD_M2M start\n"); + goto err_ipp_ctrl_start; + } + + while (1) { + struct timeval timeout = { .tv_sec = 3, .tv_usec = 0 }; + fd_set fds; + + FD_ZERO(&fds); + FD_SET(0, &fds); + FD_SET(fd, &fds); + ret = select(fd + 1, &fds, NULL, NULL, &timeout); + if (ret <= 0) { + fprintf(stderr, "select timed out or error.\n"); + continue; + } else if (FD_ISSET(0, &fds)) { + break; + } + + gettimeofday(&end, NULL); + usec[j] = (end.tv_sec - begin.tv_sec) * 1000000 + + (end.tv_usec - begin.tv_usec); + + sprintf(filename, "/opt/media/rot_%d.bmp", j); + util_write_bmp(filename, usr_addr2, height, width); + + break; + } + + /* For destination buffer queue to IPP */ + ret = exynos_drm_ipp_buf(fd, &buf2, EXYNOS_DRM_OPS_DST, + IPP_BUF_CTRL_QUEUE, gem2.handle); + if (ret) { + fprintf(stderr, "failed to ipp buf dst queue\n"); + goto err_ipp_ctrl_start; + } + } + + /* For source buffer unmap to IPP */ + ret = exynos_drm_ipp_buf(fd, &buf1, EXYNOS_DRM_OPS_SRC, + IPP_BUF_CTRL_UNMAP, gem1.handle); + if (ret) { + fprintf(stderr, "failed to ipp buf src unmap\n"); + goto err_ipp_buf_unmap; + } + + /* For destination buffer unmap to IPP */ + ret = exynos_drm_ipp_buf(fd, &buf2, EXYNOS_DRM_OPS_DST, + IPP_BUF_CTRL_UNMAP, gem2.handle); + if (ret < 0) { + fprintf(stderr, "failed to ipp buf dst unmap\n"); + goto err_ipp_buf_unmap; + } + + /* Stop */ + ret = exynos_drm_ipp_ctrl(fd, &ctrl, IPP_CMD_M2M, 0); + if (ret) { + fprintf(stderr, "failed to ipp ctrl IPP_CMD_M2M stop\n"); + goto err_ipp_buf_unmap; + } + + munmap(usr_addr2, mmap2.size); + munmap(usr_addr1, mmap1.size); + + memset(&args, 0x00, sizeof(struct drm_gem_close)); + args.handle = gem2.handle; + exynos_gem_close(fd, &args); + memset(&args, 0x00, sizeof(struct drm_gem_close)); + args.handle = gem1.handle; + exynos_gem_close(fd, &args); + + return; + +err_ipp_buf_unmap: + exynos_drm_ipp_ctrl(fd, &ctrl, IPP_CMD_M2M, 0); +err_ipp_ctrl_start: + exynos_drm_ipp_buf(fd, &buf2, EXYNOS_DRM_OPS_DST, IPP_BUF_CTRL_UNMAP, + gem2.handle); +err_ipp_buf_map2: + exynos_drm_ipp_buf(fd, &buf1, EXYNOS_DRM_OPS_SRC, IPP_BUF_CTRL_UNMAP, + gem1.handle); +err_ipp_buf_map1: + munmap(usr_addr2, mmap2.size); +err_gem_mmap2: + memset(&args, 0x00, sizeof(struct drm_gem_close)); + args.handle = gem2.handle; + exynos_gem_close(fd, &args); +err_gem_create2: + munmap(usr_addr1, mmap1.size); +err_gem_mmap1: + memset(&args, 0x00, sizeof(struct drm_gem_close)); + args.handle = gem1.handle; + exynos_gem_close(fd, &args); +} diff --git a/tests/rottest/rotator.h b/tests/rottest/rotator.h new file mode 100644 index 0000000..8835ee3 --- /dev/null +++ b/tests/rottest/rotator.h @@ -0,0 +1,7 @@ +#ifndef __ROTATOR_H__ +#define __ROTATOR_H__ + +extern void rotator_set_mode(struct connector *c, int count, int page_flip, + long int *usec); + +#endif diff --git a/tests/rottest/rottest.c b/tests/rottest/rottest.c new file mode 100644 index 0000000..1da52f3 --- /dev/null +++ b/tests/rottest/rottest.c @@ -0,0 +1,460 @@ +/* + * DRM based rotator test program + * Copyright 2012 Samsung Electronics + * YoungJun Cho + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +/* + * This fairly simple test program dumps output in a similar format to the + * "xrandr" tool everyone knows & loves. It's necessarily slightly different + * since the kernel separates outputs into encoder and connector structures, + * each with their own unique ID. The program also allows test testing of the + * memory management and mode setting APIs by allowing the user to specify a + * connector and mode to use for mode setting. If all works as expected, a + * blue background should be painted on the monitor attached to the specified + * connector after the selected mode is set. + * + */ + +#include "config.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "libkms.h" + +#include "exynos_drm.h" + +#include "rottest.h" +#include "rotator.h" + +drmModeRes *resources; +int fd, modes; + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +struct type_name { + int type; + char *name; +}; + +#define type_name_fn(res) \ +char * res##_str(int type) { \ + int i; \ + for (i = 0; i < ARRAY_SIZE(res##_names); i++) { \ + if (res##_names[i].type == type) \ + return res##_names[i].name; \ + } \ + return "(invalid)"; \ +} + +struct type_name encoder_type_names[] = { + { DRM_MODE_ENCODER_NONE, "none" }, + { DRM_MODE_ENCODER_DAC, "DAC" }, + { DRM_MODE_ENCODER_TMDS, "TMDS" }, + { DRM_MODE_ENCODER_LVDS, "LVDS" }, + { DRM_MODE_ENCODER_TVDAC, "TVDAC" }, +}; + +type_name_fn(encoder_type) + +struct type_name connector_status_names[] = { + { DRM_MODE_CONNECTED, "connected" }, + { DRM_MODE_DISCONNECTED, "disconnected" }, + { DRM_MODE_UNKNOWNCONNECTION, "unknown" }, +}; + +type_name_fn(connector_status) + +struct type_name connector_type_names[] = { + { DRM_MODE_CONNECTOR_Unknown, "unknown" }, + { DRM_MODE_CONNECTOR_VGA, "VGA" }, + { DRM_MODE_CONNECTOR_DVII, "DVI-I" }, + { DRM_MODE_CONNECTOR_DVID, "DVI-D" }, + { DRM_MODE_CONNECTOR_DVIA, "DVI-A" }, + { DRM_MODE_CONNECTOR_Composite, "composite" }, + { DRM_MODE_CONNECTOR_SVIDEO, "s-video" }, + { DRM_MODE_CONNECTOR_LVDS, "LVDS" }, + { DRM_MODE_CONNECTOR_Component, "component" }, + { DRM_MODE_CONNECTOR_9PinDIN, "9-pin DIN" }, + { DRM_MODE_CONNECTOR_DisplayPort, "displayport" }, + { DRM_MODE_CONNECTOR_HDMIA, "HDMI-A" }, + { DRM_MODE_CONNECTOR_HDMIB, "HDMI-B" }, + { DRM_MODE_CONNECTOR_TV, "TV" }, + { DRM_MODE_CONNECTOR_eDP, "embedded displayport" }, + { DRM_MODE_CONNECTOR_VIRTUAL, "Virtual" }, +}; + +type_name_fn(connector_type) + +static void dump_encoders(void) +{ + drmModeEncoder *encoder; + int i; + + printf("Encoders:\n"); + printf("id\tcrtc\ttype\tpossible crtcs\tpossible clones\t\n"); + for (i = 0; i < resources->count_encoders; i++) { + encoder = drmModeGetEncoder(fd, resources->encoders[i]); + + if (!encoder) { + fprintf(stderr, "could not get encoder %i: %s\n", + resources->encoders[i], strerror(errno)); + continue; + } + printf("%d\t%d\t%s\t0x%08x\t0x%08x\n", + encoder->encoder_id, + encoder->crtc_id, + encoder_type_str(encoder->encoder_type), + encoder->possible_crtcs, + encoder->possible_clones); + drmModeFreeEncoder(encoder); + } + printf("\n"); +} + +static void dump_mode(drmModeModeInfo *mode) +{ + printf(" %s %d %d %d %d %d %d %d %d %d\n", + mode->name, + mode->vrefresh, + mode->hdisplay, + mode->hsync_start, + mode->hsync_end, + mode->htotal, + mode->vdisplay, + mode->vsync_start, + mode->vsync_end, + mode->vtotal); +} + +static void dump_props(drmModeConnector *connector) +{ + drmModePropertyPtr props; + int i; + + for (i = 0; i < connector->count_props; i++) { + props = drmModeGetProperty(fd, connector->props[i]); + printf("\t%s, flags %d\n", props->name, props->flags); + drmModeFreeProperty(props); + } +} + +static void dump_connectors(void) +{ + drmModeConnector *connector; + int i, j; + + printf("Connectors:\n"); + printf("id\tencoder\tstatus\t\ttype\tsize (mm)\tmodes\tencoders\n"); + for (i = 0; i < resources->count_connectors; i++) { + connector = drmModeGetConnector(fd, resources->connectors[i]); + + if (!connector) { + fprintf(stderr, "could not get connector %i: %s\n", + resources->connectors[i], strerror(errno)); + continue; + } + + printf("%d\t%d\t%s\t%s\t%dx%d\t\t%d\t", + connector->connector_id, + connector->encoder_id, + connector_status_str(connector->connection), + connector_type_str(connector->connector_type), + connector->mmWidth, connector->mmHeight, + connector->count_modes); + + for (j = 0; j < connector->count_encoders; j++) + printf("%s%d", j > 0 ? ", " : "", + connector->encoders[j]); + printf("\n"); + + if (!connector->count_modes) + continue; + + printf(" modes:\n"); + printf(" name refresh (Hz) hdisp hss hse htot vdisp " + "vss vse vtot)\n"); + for (j = 0; j < connector->count_modes; j++) + dump_mode(&connector->modes[j]); + + printf(" props:\n"); + dump_props(connector); + + drmModeFreeConnector(connector); + } + printf("\n"); +} + +static void dump_crtcs(void) +{ + drmModeCrtc *crtc; + int i; + + printf("CRTCs:\n"); + printf("id\tfb\tpos\tsize\n"); + for (i = 0; i < resources->count_crtcs; i++) { + crtc = drmModeGetCrtc(fd, resources->crtcs[i]); + + if (!crtc) { + fprintf(stderr, "could not get crtc %i: %s\n", + resources->crtcs[i], strerror(errno)); + continue; + } + printf("%d\t%d\t(%d,%d)\t(%dx%d)\n", + crtc->crtc_id, + crtc->buffer_id, + crtc->x, crtc->y, + crtc->width, crtc->height); + dump_mode(&crtc->mode); + + drmModeFreeCrtc(crtc); + } + printf("\n"); +} + +static void dump_framebuffers(void) +{ + drmModeFB *fb; + int i; + + printf("Frame buffers:\n"); + printf("id\tsize\tpitch\n"); + for (i = 0; i < resources->count_fbs; i++) { + fb = drmModeGetFB(fd, resources->fbs[i]); + + if (!fb) { + fprintf(stderr, "could not get fb %i: %s\n", + resources->fbs[i], strerror(errno)); + continue; + } + printf("%u\t(%ux%u)\t%u\n", + fb->fb_id, + fb->width, fb->height, + fb->pitch); + + drmModeFreeFB(fb); + } + printf("\n"); +} + +/* + * Mode setting with the kernel interfaces is a bit of a chore. + * First you have to find the connector in question and make sure the + * requested mode is available. + * Then you need to find the encoder attached to that connector so you + * can bind it with a free crtc. + */ + +void connector_find_mode(struct connector *c) +{ + drmModeConnector *connector; + int i, j; + + /* First, find the connector & mode */ + c->mode = NULL; + for (i = 0; i < resources->count_connectors; i++) { + connector = drmModeGetConnector(fd, resources->connectors[i]); + + if (!connector) { + fprintf(stderr, "could not get connector %i: %s\n", + resources->connectors[i], strerror(errno)); + drmModeFreeConnector(connector); + continue; + } + + if (!connector->count_modes) { + drmModeFreeConnector(connector); + continue; + } + + if (connector->connector_id != c->id) { + drmModeFreeConnector(connector); + continue; + } + + for (j = 0; j < connector->count_modes; j++) { + c->mode = &connector->modes[j]; + if (!strcmp(c->mode->name, c->mode_str)) + break; + } + + /* Found it, break out */ + if (c->mode) + break; + + drmModeFreeConnector(connector); + } + + if (!c->mode) { + fprintf(stderr, "failed to find mode \"%s\"\n", c->mode_str); + return; + } + + /* Now get the encoder */ + for (i = 0; i < resources->count_encoders; i++) { + c->encoder = drmModeGetEncoder(fd, resources->encoders[i]); + + if (!c->encoder) { + fprintf(stderr, "could not get encoder %i: %s\n", + resources->encoders[i], strerror(errno)); + drmModeFreeEncoder(c->encoder); + continue; + } + + if (c->encoder->encoder_id == connector->encoder_id) + break; + + drmModeFreeEncoder(c->encoder); + } + + if (c->crtc == -1) + c->crtc = c->encoder->crtc_id; +} + +extern char *optarg; +extern int optind, opterr, optopt; +static char optstr[] = "ecpmfs:v"; + +static void usage(char *name) +{ + fprintf(stderr, "usage: %s [-ecpmf]\n", name); + fprintf(stderr, "\t-e\tlist encoders\n"); + fprintf(stderr, "\t-c\tlist connectors\n"); + fprintf(stderr, "\t-p\tlist CRTCs (pipes)\n"); + fprintf(stderr, "\t-m\tlist modes\n"); + fprintf(stderr, "\t-f\tlist framebuffers\n"); + fprintf(stderr, "\t-v\ttest vsynced page flipping\n"); + fprintf(stderr, "\t-s :\tset a mode\n"); + fprintf(stderr, "\t-s @:\tset a mode\n"); + fprintf(stderr, "\n\tDefault is to dump all info.\n"); + exit(0); +} + +#define dump_resource(res) if (res) dump_##res() + +int main(int argc, char **argv) +{ + int c; + int encoders = 0, connectors = 0, crtcs = 0, framebuffers = 0; + int test_vsync = 0; + char *modules[] = {"exynos", "i915", "radeon", "nouveau", "vmwgfx"}; + char *modeset = NULL; + int i, count = 0; + struct connector con_args[2]; + + opterr = 0; + while ((c = getopt(argc, argv, optstr)) != -1) { + switch (c) { + case 'e': + encoders = 1; + break; + case 'c': + connectors = 1; + break; + case 'p': + crtcs = 1; + break; + case 'm': + modes = 1; + break; + case 'f': + framebuffers = 1; + break; + case 'v': + test_vsync = 1; + break; + case 's': + modeset = strdup(optarg); + con_args[count].crtc = -1; + if (sscanf(optarg, "%d:%64s", + &con_args[count].id, + con_args[count].mode_str) != 2 && + sscanf(optarg, "%d@%d:%64s", + &con_args[count].id, + &con_args[count].crtc, + con_args[count].mode_str) != 3) + usage(argv[0]); + count++; + break; + default: + usage(argv[0]); + break; + } + } + + if (argc == 1) + encoders = connectors = crtcs = modes = framebuffers = 1; + + for (i = 0; i < ARRAY_SIZE(modules); i++) { + printf("trying to load module %s...", modules[i]); + fd = drmOpen(modules[i], NULL); + if (fd < 0) { + printf("failed.\n"); + } else { + printf("success.\n"); + break; + } + } + + if (i == ARRAY_SIZE(modules)) { + fprintf(stderr, "failed to load any modules, aborting.\n"); + return -1; + } + + resources = drmModeGetResources(fd); + if (!resources) { + fprintf(stderr, "drmModeGetResources failed: %s\n", + strerror(errno)); + drmClose(fd); + return 1; + } + + dump_resource(encoders); + dump_resource(connectors); + dump_resource(crtcs); + dump_resource(framebuffers); + + if (count > 0) { + long int sum = 0, usec[MAX_LOOP]; + + rotator_set_mode(con_args, count, test_vsync, usec); + for (i = 0; i < MAX_LOOP; i++) { + printf("[%d] : %d\n", i + 1, usec[i]); + sum += usec[i]; + } + printf("rotator : cma\n"); + printf("avg : [%d]\n", sum / MAX_LOOP); + getchar(); + } + + drmModeFreeResources(resources); + + return 0; +} diff --git a/tests/rottest/rottest.h b/tests/rottest/rottest.h new file mode 100644 index 0000000..0edb3ca --- /dev/null +++ b/tests/rottest/rottest.h @@ -0,0 +1,25 @@ +#ifndef __ROTTEST_H__ +#define __ROTTEST_H__ + +#include "xf86drm.h" +#include "xf86drmMode.h" + +#define MAX_LOOP 20 + +struct connector { + uint32_t id; + char mode_str[64]; + drmModeModeInfo *mode; + drmModeEncoder *encoder; + int crtc; + unsigned int fb_id[2], current_fb_id; + struct timeval start; + + int swap_count; +}; + +extern int fd; + +extern void connector_find_mode(struct connector *c); + +#endif diff --git a/tests/rottest/util.c b/tests/rottest/util.c new file mode 100644 index 0000000..8800c48 --- /dev/null +++ b/tests/rottest/util.c @@ -0,0 +1,132 @@ +/* + * DRM based rotator test program + * Copyright 2012 Samsung Electronics + * YoungJun Cho + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include + +#include "exynos_drm.h" +#include "gem.h" + +int util_gem_create_mmap(int fd, struct drm_exynos_gem_create *gem, + struct drm_exynos_gem_mmap *mmap, + unsigned int size) +{ + /* initialize structure for gem create */ + memset(gem, 0x00, sizeof(struct drm_exynos_gem_create)); + gem->size = size; + + if (exynos_gem_create(fd, gem) < 0) { + fprintf(stderr, "failed to gem create: %s\n", strerror(errno)); + return -1; + } + + /* initialize structure for gem mmap */ + memset(mmap, 0x00, sizeof(struct drm_exynos_gem_mmap)); + mmap->handle = gem->handle; + mmap->size = gem->size; + + if (exynos_gem_mmap(fd, mmap) < 0) { + fprintf(stderr, "failed to gem mmap: %s\n", strerror(errno)); + return -2; + } + + return 0; +} + +void util_draw_buffer(void *addr, unsigned int stripe, + unsigned int width, unsigned int height, + unsigned int stride, unsigned int size) +{ + if (stripe == 1) { + int i, j; + unsigned int *fb_ptr; + div_t d; + + for (j = 0; j < height; j++) { + fb_ptr = (unsigned int *)((char *)addr + j * stride); + for (i = 0; i < width; i++) { + d = div(i, width); + fb_ptr[i] = 0x00130502 * (d.quot >> 6) + + 0x000a1120 * (d.rem >> 6); + } + } + } else + memset(addr, 0x77, size); +} + +int util_write_bmp(const char *file, const void *data, unsigned int width, + unsigned int height) +{ + int i; + unsigned int * blocks; + FILE *fp; + struct { + unsigned char magic[2]; + } bmpfile_magic = { {'B', 'M'} }; + struct { + unsigned int filesz; + unsigned short creator1; + unsigned short creator2; + unsigned int bmp_offset; + } bmpfile_header = { 0, 0, 0, 0x36 }; + struct { + unsigned int header_sz; + unsigned int width; + unsigned int height; + unsigned short nplanes; + unsigned short bitspp; + unsigned int compress_type; + unsigned int bmp_bytesz; + unsigned int hres; + unsigned int vres; + unsigned int ncolors; + unsigned int nimpcolors; + } bmp_dib_v3_header_t = { 0x28, 0, 0, 1, 32, 0, 0, 0, 0, 0, 0 }; + + fp = fopen(file, "wb"); + if (fp == NULL) return -1; + + bmpfile_header.filesz = sizeof(bmpfile_magic) + sizeof(bmpfile_header) + + sizeof(bmp_dib_v3_header_t) + width * height * 4; + bmp_dib_v3_header_t.header_sz = sizeof(bmp_dib_v3_header_t); + bmp_dib_v3_header_t.width = width; + bmp_dib_v3_header_t.height = -height; + bmp_dib_v3_header_t.nplanes = 1; + bmp_dib_v3_header_t.bmp_bytesz = width * height * 4; + + fwrite(&bmpfile_magic, sizeof(bmpfile_magic), 1, fp); + fwrite(&bmpfile_header, sizeof(bmpfile_header), 1, fp); + fwrite(&bmp_dib_v3_header_t, sizeof(bmp_dib_v3_header_t), 1, fp); + + blocks = (unsigned int*)data; + for (i = 0; i < height * width; i++) + fwrite(&blocks[i], 4, 1, fp); + + fclose(fp); + return 0; +} diff --git a/tests/rottest/util.h b/tests/rottest/util.h new file mode 100644 index 0000000..e1ffcca --- /dev/null +++ b/tests/rottest/util.h @@ -0,0 +1,12 @@ +#ifndef __UTIL_H__ +#define __UTIL_H__ + +extern int util_gem_create_mmap(int fd, struct drm_exynos_gem_create *gem, + struct drm_exynos_gem_mmap *mmap, + unsigned int size); +extern void util_draw_buffer(void *addr, unsigned int stripe, + unsigned int width, unsigned int height, + unsigned int stride, unsigned int size); +extern int util_write_bmp(const char *file, const void *data, + unsigned int width, unsigned int height); +#endif diff --git a/tests/setversion.c b/tests/setversion.c new file mode 100644 index 0000000..3aaf7cc --- /dev/null +++ b/tests/setversion.c @@ -0,0 +1,89 @@ +/* + * Copyright © 2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include "drmtest.h" + +/** + * Checks DRM_IOCTL_SET_VERSION. + * + * This tests that we can get the actual version out, and that setting invalid + * major/minor numbers fails appropriately. It does not check the actual + * behavior differenses resulting from an increased DI version. + */ +int main(int argc, char **argv) +{ + int fd, ret; + drm_set_version_t sv, version; + + if (getuid() != 0) { + fprintf(stderr, "setversion test requires root, skipping\n"); + return 0; + } + + fd = drm_open_any_master(); + + /* First, check that we can get the DD/DI versions. */ + memset(&version, 0, sizeof(version)); + version.drm_di_major = -1; + version.drm_di_minor = -1; + version.drm_dd_major = -1; + version.drm_dd_minor = -1; + ret = ioctl(fd, DRM_IOCTL_SET_VERSION, &version); + assert(ret == 0); + assert(version.drm_di_major != -1); + assert(version.drm_di_minor != -1); + assert(version.drm_dd_major != -1); + assert(version.drm_dd_minor != -1); + + /* Check that an invalid DI major fails */ + sv = version; + sv.drm_di_major++; + ret = ioctl(fd, DRM_IOCTL_SET_VERSION, &sv); + assert(ret == -1 && errno == EINVAL); + + /* Check that an invalid DI minor fails */ + sv = version; + sv.drm_di_major++; + ret = ioctl(fd, DRM_IOCTL_SET_VERSION, &sv); + assert(ret == -1 && errno == EINVAL); + + /* Check that an invalid DD major fails */ + sv = version; + sv.drm_dd_major++; + ret = ioctl(fd, DRM_IOCTL_SET_VERSION, &sv); + assert(ret == -1 && errno == EINVAL); + + /* Check that an invalid DD minor fails */ + sv = version; + sv.drm_dd_minor++; + ret = ioctl(fd, DRM_IOCTL_SET_VERSION, &sv); + assert(ret == -1 && errno == EINVAL); + + close(fd); + return 0; +} diff --git a/tests/ttmtest/AUTHORS b/tests/ttmtest/AUTHORS new file mode 100644 index 0000000..fa4a089 --- /dev/null +++ b/tests/ttmtest/AUTHORS @@ -0,0 +1 @@ +Thomas Hellström and others. diff --git a/tests/ttmtest/ChangeLog b/tests/ttmtest/ChangeLog new file mode 100644 index 0000000..4588c8d --- /dev/null +++ b/tests/ttmtest/ChangeLog @@ -0,0 +1,23 @@ +2006-01-24 Thomas Hellström + + * configure.ac: + * src/ttmtest.c: + + Fixed include path. + +2006-01-24 Thomas Hellström + + * AUTHORS: + * Makefile.am: + * configure.ac: + * reconf: + * src/Makefile.am: + * src/ttmtest.c: (fastrdtsc), (time_diff), (releaseContext), + (testAGP), (main): + * src/xf86dri.c: (uniDRIDestroyContext), (uniDRICreateDrawable), + (uniDRIDestroyDrawable), (uniDRIGetDrawableInfo): + * src/xf86dri.h: + * src/xf86dristr.h: + + Initial import of the ttmtest utility. + \ No newline at end of file diff --git a/tests/ttmtest/Makefile.am b/tests/ttmtest/Makefile.am new file mode 100644 index 0000000..af437a6 --- /dev/null +++ b/tests/ttmtest/Makefile.am @@ -0,0 +1 @@ +SUBDIRS = src diff --git a/tests/ttmtest/NEWS b/tests/ttmtest/NEWS new file mode 100644 index 0000000..e69de29 diff --git a/tests/ttmtest/README b/tests/ttmtest/README new file mode 100644 index 0000000..e69de29 diff --git a/tests/ttmtest/configure.ac b/tests/ttmtest/configure.ac new file mode 100644 index 0000000..c41e91a --- /dev/null +++ b/tests/ttmtest/configure.ac @@ -0,0 +1,33 @@ +AC_INIT +AC_PROG_CC +AC_PATH_X +if test "x$no_x" != "xyes"; then + savecpp="$CPPFLAGS" + CPPFLAGS="$CPPFLAGS -I$x_includes" + AC_CHECK_HEADER($x_includes/X11/Xlib.h,,\ + [AC_MSG_ERROR(Could not find X installation.)]) + CPPFLAGS="$savecpp" + MDRIINC="-I$x_includes" + LIBS="-L$x_libraries $LIBS" +else + AC_MSG_ERROR(Could not find X installation. Aborting.) +fi +AC_ARG_WITH(libdrm, + AC_HELP_STRING([--with-libdrm=DIR], + [Installation prefix of libdrm [[default=/usr]]]), + [libdrmpref="$withval"], + [libdrmpref="/usr"]) +savecpp="$CPPFLAGS" +MDRIINC="-I$libdrmpref/include -I$libdrmpref/include/drm -I$x_includes" +CPPFLAGS="$CPPFLAGS $MDRIINC" +AC_CHECK_HEADER(xf86drm.h,,\ + [AC_MSG_ERROR(Could not find libdrm installation. Use --with-libdrm=)]) +AC_CHECK_HEADER(drm.h,,\ + [AC_MSG_ERROR(Could not find libdrm installation. Use --with-libdrm=)]) +CPPFLAGS="$savecpp" +LIBS="-L$libdrmpref/lib64 -L$libdrmpref/lib $LIBS" +AC_SUBST(MDRIINC) +AC_SYS_LARGEFILE +AM_INIT_AUTOMAKE(minidri,0.1.0) +AM_CONFIG_HEADER(config.h) +AC_OUTPUT([Makefile src/Makefile]) diff --git a/tests/ttmtest/reconf b/tests/ttmtest/reconf new file mode 100644 index 0000000..e64d00a --- /dev/null +++ b/tests/ttmtest/reconf @@ -0,0 +1,2 @@ +#!/bin/sh +autoreconf -v --install || exit 1 \ No newline at end of file diff --git a/tests/ttmtest/src/Makefile.am b/tests/ttmtest/src/Makefile.am new file mode 100644 index 0000000..b7ee829 --- /dev/null +++ b/tests/ttmtest/src/Makefile.am @@ -0,0 +1,8 @@ +INCLUDES = @MDRIINC@ +bin_PROGRAMS = ttmtest +ttmtest_SOURCES = \ + ttmtest.c \ + xf86dri.c \ + xf86dri.h \ + xf86dristr.h +ttmtest_LDADD = -ldrm -lXext -lX11 diff --git a/tests/ttmtest/src/ttmtest.c b/tests/ttmtest/src/ttmtest.c new file mode 100644 index 0000000..36df242 --- /dev/null +++ b/tests/ttmtest/src/ttmtest.c @@ -0,0 +1,430 @@ +/************************************************************************** + * + * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, TX., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * + **************************************************************************/ +/* + * Authors: Thomas Hellström + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include +#include "xf86dri.h" +#include "xf86drm.h" +#include "stdio.h" +#include "sys/types.h" +#include +#include +#include +#include +#include "sys/mman.h" + +typedef struct +{ + enum + { + haveNothing, + haveDisplay, + haveConnection, + haveDriverName, + haveDeviceInfo, + haveDRM, + haveContext + } + state; + + Display *display; + int screen; + drm_handle_t sAreaOffset; + char *curBusID; + char *driverName; + int drmFD; + XVisualInfo visualInfo; + XID id; + drm_context_t hwContext; + void *driPriv; + int driPrivSize; + int fbSize; + int fbOrigin; + int fbStride; + drm_handle_t fbHandle; + int ddxDriverMajor; + int ddxDriverMinor; + int ddxDriverPatch; +} TinyDRIContext; + +#ifndef __x86_64__ +static unsigned +fastrdtsc(void) +{ + unsigned eax; + __asm__ volatile ("\t" + "pushl %%ebx\n\t" + "cpuid\n\t" ".byte 0x0f, 0x31\n\t" "popl %%ebx\n":"=a" (eax) + :"0"(0) + :"ecx", "edx", "cc"); + + return eax; +} +#else +static unsigned +fastrdtsc(void) +{ + unsigned eax; + __asm__ volatile ("\t" "cpuid\n\t" ".byte 0x0f, 0x31\n\t":"=a" (eax) + :"0"(0) + :"ecx", "edx", "ebx", "cc"); + + return eax; +} +#endif + +void +bmError(int val, const char *file, const char *function, int line) +{ + fprintf(stderr, "Fatal video memory manager error \"%s\".\n" + "Check kernel logs or set the LIBGL_DEBUG\n" + "environment variable to \"verbose\" for more info.\n" + "Detected in file %s, line %d, function %s.\n", + strerror(-val), file, line, function); + abort(); +} + +#define BM_CKFATAL(val) \ + do{ \ + int tstVal = (val); \ + if (tstVal) \ + bmError(tstVal, __FILE__, __FUNCTION__, __LINE__); \ + } while(0); + +static unsigned +time_diff(unsigned t, unsigned t2) +{ + return ((t < t2) ? t2 - t : 0xFFFFFFFFU - (t - t2 - 1)); +} + +static int +releaseContext(TinyDRIContext * ctx) +{ + switch (ctx->state) { + case haveContext: + uniDRIDestroyContext(ctx->display, ctx->screen, ctx->id); + case haveDRM: + drmClose(ctx->drmFD); + case haveDeviceInfo: + XFree(ctx->driPriv); + case haveDriverName: + XFree(ctx->driverName); + case haveConnection: + XFree(ctx->curBusID); + uniDRICloseConnection(ctx->display, ctx->screen); + case haveDisplay: + XCloseDisplay(ctx->display); + default: + break; + } + return -1; +} + +static void +readBuf(void *buf, unsigned long size) +{ + volatile unsigned *buf32 = (unsigned *)buf; + unsigned *end = (unsigned *)buf32 + size / sizeof(*buf32); + + while (buf32 < end) { + (void)*buf32++; + } +} + +static int +benchmarkBuffer(TinyDRIContext * ctx, unsigned long size, + unsigned long *ticks) +{ + unsigned long curTime, oldTime; + int ret; + drmBO buf; + void *virtual; + + /* + * Test system memory objects. + */ + oldTime = fastrdtsc(); + BM_CKFATAL(drmBOCreate(ctx->drmFD, size, 0, NULL, + DRM_BO_FLAG_READ | + DRM_BO_FLAG_WRITE | + DRM_BO_FLAG_MEM_LOCAL, 0, &buf)); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + oldTime = fastrdtsc(); + BM_CKFATAL(drmBOMap(ctx->drmFD, &buf, + DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0, &virtual)); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + oldTime = fastrdtsc(); + memset(virtual, 0xF0, buf.size); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + oldTime = fastrdtsc(); + memset(virtual, 0x0F, buf.size); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + oldTime = fastrdtsc(); + readBuf(virtual, buf.size); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + oldTime = fastrdtsc(); + BM_CKFATAL(drmBOUnmap(ctx->drmFD, &buf)); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + /* + * Test TT bound buffer objects. + */ + + oldTime = fastrdtsc(); + BM_CKFATAL(drmBOSetStatus(ctx->drmFD, &buf, + DRM_BO_FLAG_MEM_TT, + DRM_BO_MASK_MEM, + 0,0,0)); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + oldTime = fastrdtsc(); + BM_CKFATAL(drmBOMap(ctx->drmFD, &buf, + DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0, &virtual)); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + oldTime = fastrdtsc(); + memset(virtual, 0xF0, buf.size); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + oldTime = fastrdtsc(); + memset(virtual, 0x0F, buf.size); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + oldTime = fastrdtsc(); + readBuf(virtual, buf.size); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + BM_CKFATAL(drmBOUnmap(ctx->drmFD, &buf)); + + oldTime = fastrdtsc(); + BM_CKFATAL(drmBOSetStatus(ctx->drmFD, &buf, + DRM_BO_FLAG_MEM_LOCAL, DRM_BO_MASK_MEM, 0, 0,0)); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + /* + * Test cached buffers objects. + */ + + oldTime = fastrdtsc(); + ret = drmBOSetStatus(ctx->drmFD, &buf, + DRM_BO_FLAG_MEM_TT | + DRM_BO_FLAG_CACHED | + DRM_BO_FLAG_FORCE_CACHING, + DRM_BO_MASK_MEMTYPE | + DRM_BO_FLAG_FORCE_CACHING, + 0, 0, 0); + curTime = fastrdtsc(); + + if (ret) { + printf("Couldn't bind cached. Probably no support\n"); + BM_CKFATAL(drmBOUnreference(ctx->drmFD, &buf)); + return 1; + } + *ticks++ = time_diff(oldTime, curTime); + + oldTime = fastrdtsc(); + BM_CKFATAL(drmBOMap(ctx->drmFD, &buf, + DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE, 0, &virtual)); + + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + oldTime = fastrdtsc(); + memset(virtual, 0xF0, buf.size); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + oldTime = fastrdtsc(); + memset(virtual, 0x0F, buf.size); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + oldTime = fastrdtsc(); + readBuf(virtual, buf.size); + curTime = fastrdtsc(); + *ticks++ = time_diff(oldTime, curTime); + + BM_CKFATAL(drmBOUnmap(ctx->drmFD, &buf)); + BM_CKFATAL(drmBOUnreference(ctx->drmFD, &buf)); + + return 0; +} + +static void +testAGP(TinyDRIContext * ctx) +{ + unsigned long ticks[128], *pTicks; + unsigned long size = 8 * 1024; + int ret; + + ret = benchmarkBuffer(ctx, size, ticks); + if (ret < 0) { + fprintf(stderr, "Buffer error %s\n", strerror(-ret)); + return; + } + pTicks = ticks; + + printf("Buffer size %d bytes\n", size); + printf("System memory timings ********************************\n"); + printf("Creation took %12lu ticks\n", *pTicks++); + printf("Mapping took %12lu ticks\n", *pTicks++); + printf("Writing took %12lu ticks\n", *pTicks++); + printf("Writing Again took %12lu ticks\n", *pTicks++); + printf("Reading took %12lu ticks\n", *pTicks++); + printf("Unmapping took %12lu ticks\n", *pTicks++); + + printf("\nTT Memory timings ************************************\n"); + printf("Moving to TT took %12lu ticks\n", *pTicks++); + printf("Mapping in TT took %12lu ticks\n", *pTicks++); + printf("Writing to TT took %12lu ticks\n", *pTicks++); + printf("Writing again to TT took %12lu ticks\n", *pTicks++); + printf("Reading from TT took %12lu ticks\n", *pTicks++); + printf("Moving to system took %12lu ticks\n", *pTicks++); + + if (ret == 1) + return; + + printf("\nCached TT Memory timings *****************************\n"); + printf("Moving to CTT took %12lu ticks\n", *pTicks++); + printf("Mapping in CTT took %12lu ticks\n", *pTicks++); + printf("Writing to CTT took %12lu ticks\n", *pTicks++); + printf("Re-writing to CTT took %12lu ticks\n", *pTicks++); + printf("Reading from CTT took %12lu ticks\n", *pTicks++); + printf("\n\n"); +} + +int +main() +{ + int ret, screen, isCapable; + char *displayName = ":0"; + TinyDRIContext ctx; + unsigned magic; + + ctx.screen = 0; + ctx.state = haveNothing; + ctx.display = XOpenDisplay(displayName); + if (!ctx.display) { + fprintf(stderr, "Could not open display\n"); + return releaseContext(&ctx); + } + ctx.state = haveDisplay; + + ret = + uniDRIQueryDirectRenderingCapable(ctx.display, ctx.screen, + &isCapable); + if (!ret || !isCapable) { + fprintf(stderr, "No DRI on this display:sceen\n"); + return releaseContext(&ctx); + } + + if (!uniDRIOpenConnection(ctx.display, ctx.screen, &ctx.sAreaOffset, + &ctx.curBusID)) { + fprintf(stderr, "Could not open DRI connection.\n"); + return releaseContext(&ctx); + } + ctx.state = haveConnection; + + if (!uniDRIGetClientDriverName(ctx.display, ctx.screen, + &ctx.ddxDriverMajor, &ctx.ddxDriverMinor, + &ctx.ddxDriverPatch, &ctx.driverName)) { + fprintf(stderr, "Could not get DRI driver name.\n"); + return releaseContext(&ctx); + } + ctx.state = haveDriverName; + + if (!uniDRIGetDeviceInfo(ctx.display, ctx.screen, + &ctx.fbHandle, &ctx.fbOrigin, &ctx.fbSize, + &ctx.fbStride, &ctx.driPrivSize, &ctx.driPriv)) { + fprintf(stderr, "Could not get DRI device info.\n"); + return releaseContext(&ctx); + } + ctx.state = haveDriverName; + + if ((ctx.drmFD = drmOpen(NULL, ctx.curBusID)) < 0) { + perror("DRM Device could not be opened"); + return releaseContext(&ctx); + } + ctx.state = haveDRM; + + drmGetMagic(ctx.drmFD, &magic); + if (!uniDRIAuthConnection(ctx.display, ctx.screen, magic)) { + fprintf(stderr, "Could not get X server to authenticate us.\n"); + return releaseContext(&ctx); + } + + ret = XMatchVisualInfo(ctx.display, ctx.screen, 24, TrueColor, + &ctx.visualInfo); + if (!ret) { + ret = XMatchVisualInfo(ctx.display, ctx.screen, 16, TrueColor, + &ctx.visualInfo); + if (!ret) { + fprintf(stderr, "Could not find a matching visual.\n"); + return releaseContext(&ctx); + } + } + + if (!uniDRICreateContext(ctx.display, ctx.screen, ctx.visualInfo.visual, + &ctx.id, &ctx.hwContext)) { + fprintf(stderr, "Could not create DRI context.\n"); + return releaseContext(&ctx); + } + ctx.state = haveContext; + + testAGP(&ctx); + + releaseContext(&ctx); + printf("Terminating normally\n"); + return 0; +} diff --git a/tests/ttmtest/src/xf86dri.c b/tests/ttmtest/src/xf86dri.c new file mode 100644 index 0000000..e6e0b89 --- /dev/null +++ b/tests/ttmtest/src/xf86dri.c @@ -0,0 +1,603 @@ +/* $XFree86: xc/lib/GL/dri/XF86dri.c,v 1.13 2002/10/30 12:51:25 alanh Exp $ */ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +Copyright 2000 VA Linux Systems, Inc. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin + * Jens Owen + * Rickard E. (Rik) Faith + * + */ + +/* THIS IS NOT AN X CONSORTIUM STANDARD */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include +#include +#include +#include +#include "xf86dristr.h" + +static XExtensionInfo _xf86dri_info_data; +static XExtensionInfo *xf86dri_info = &_xf86dri_info_data; +static char xf86dri_extension_name[] = XF86DRINAME; + +#define uniDRICheckExtension(dpy,i,val) \ + XextCheckExtension (dpy, i, xf86dri_extension_name, val) + +/***************************************************************************** + * * + * private utility routines * + * * + *****************************************************************************/ + +static int close_display(Display * dpy, XExtCodes * extCodes); +static /* const */ XExtensionHooks xf86dri_extension_hooks = { + NULL, /* create_gc */ + NULL, /* copy_gc */ + NULL, /* flush_gc */ + NULL, /* free_gc */ + NULL, /* create_font */ + NULL, /* free_font */ + close_display, /* close_display */ + NULL, /* wire_to_event */ + NULL, /* event_to_wire */ + NULL, /* error */ + NULL, /* error_string */ +}; + +static +XEXT_GENERATE_FIND_DISPLAY(find_display, xf86dri_info, + xf86dri_extension_name, &xf86dri_extension_hooks, 0, NULL) + + static XEXT_GENERATE_CLOSE_DISPLAY(close_display, xf86dri_info) + +/***************************************************************************** + * * + * public XFree86-DRI Extension routines * + * * + *****************************************************************************/ +#if 0 +#include +#define TRACE(msg) fprintf(stderr,"uniDRI%s\n", msg); +#else +#define TRACE(msg) +#endif + Bool uniDRIQueryExtension(dpy, event_basep, error_basep) + Display *dpy; + int *event_basep, *error_basep; +{ + XExtDisplayInfo *info = find_display(dpy); + + TRACE("QueryExtension..."); + if (XextHasExtension(info)) { + *event_basep = info->codes->first_event; + *error_basep = info->codes->first_error; + TRACE("QueryExtension... return True"); + return True; + } else { + TRACE("QueryExtension... return False"); + return False; + } +} + +Bool +uniDRIQueryVersion(dpy, majorVersion, minorVersion, patchVersion) + Display *dpy; + int *majorVersion; + int *minorVersion; + int *patchVersion; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIQueryVersionReply rep; + xXF86DRIQueryVersionReq *req; + + TRACE("QueryVersion..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIQueryVersion, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIQueryVersion; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("QueryVersion... return False"); + return False; + } + *majorVersion = rep.majorVersion; + *minorVersion = rep.minorVersion; + *patchVersion = rep.patchVersion; + UnlockDisplay(dpy); + SyncHandle(); + TRACE("QueryVersion... return True"); + return True; +} + +Bool +uniDRIQueryDirectRenderingCapable(dpy, screen, isCapable) + Display *dpy; + int screen; + Bool *isCapable; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIQueryDirectRenderingCapableReply rep; + xXF86DRIQueryDirectRenderingCapableReq *req; + + TRACE("QueryDirectRenderingCapable..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIQueryDirectRenderingCapable, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIQueryDirectRenderingCapable; + req->screen = screen; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("QueryDirectRenderingCapable... return False"); + return False; + } + *isCapable = rep.isCapable; + UnlockDisplay(dpy); + SyncHandle(); + TRACE("QueryDirectRenderingCapable... return True"); + return True; +} + +Bool +uniDRIOpenConnection(dpy, screen, hSAREA, busIdString) + Display *dpy; + int screen; + drm_handle_t *hSAREA; + char **busIdString; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIOpenConnectionReply rep; + xXF86DRIOpenConnectionReq *req; + + TRACE("OpenConnection..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIOpenConnection, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIOpenConnection; + req->screen = screen; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("OpenConnection... return False"); + return False; + } + + *hSAREA = rep.hSAREALow; +#ifdef LONG64 + if (sizeof(drm_handle_t) == 8) { + *hSAREA |= ((unsigned long)rep.hSAREAHigh) << 32; + } +#endif + if (rep.length) { + if (!(*busIdString = (char *)Xcalloc(rep.busIdStringLength + 1, 1))) { + _XEatData(dpy, ((rep.busIdStringLength + 3) & ~3)); + UnlockDisplay(dpy); + SyncHandle(); + TRACE("OpenConnection... return False"); + return False; + } + _XReadPad(dpy, *busIdString, rep.busIdStringLength); + } else { + *busIdString = NULL; + } + UnlockDisplay(dpy); + SyncHandle(); + TRACE("OpenConnection... return True"); + return True; +} + +Bool +uniDRIAuthConnection(dpy, screen, magic) + Display *dpy; + int screen; + drm_magic_t magic; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIAuthConnectionReq *req; + xXF86DRIAuthConnectionReply rep; + + TRACE("AuthConnection..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIAuthConnection, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIAuthConnection; + req->screen = screen; + req->magic = magic; + rep.authenticated = 0; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse) || !rep.authenticated) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("AuthConnection... return False"); + return False; + } + UnlockDisplay(dpy); + SyncHandle(); + TRACE("AuthConnection... return True"); + return True; +} + +Bool +uniDRICloseConnection(dpy, screen) + Display *dpy; + int screen; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRICloseConnectionReq *req; + + TRACE("CloseConnection..."); + + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRICloseConnection, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRICloseConnection; + req->screen = screen; + UnlockDisplay(dpy); + SyncHandle(); + TRACE("CloseConnection... return True"); + return True; +} + +Bool +uniDRIGetClientDriverName(dpy, screen, ddxDriverMajorVersion, + ddxDriverMinorVersion, ddxDriverPatchVersion, clientDriverName) + Display *dpy; + int screen; + int *ddxDriverMajorVersion; + int *ddxDriverMinorVersion; + int *ddxDriverPatchVersion; + char **clientDriverName; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIGetClientDriverNameReply rep; + xXF86DRIGetClientDriverNameReq *req; + + TRACE("GetClientDriverName..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIGetClientDriverName, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIGetClientDriverName; + req->screen = screen; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetClientDriverName... return False"); + return False; + } + + *ddxDriverMajorVersion = rep.ddxDriverMajorVersion; + *ddxDriverMinorVersion = rep.ddxDriverMinorVersion; + *ddxDriverPatchVersion = rep.ddxDriverPatchVersion; + + if (rep.length) { + if (!(*clientDriverName = + (char *)Xcalloc(rep.clientDriverNameLength + 1, 1))) { + _XEatData(dpy, ((rep.clientDriverNameLength + 3) & ~3)); + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetClientDriverName... return False"); + return False; + } + _XReadPad(dpy, *clientDriverName, rep.clientDriverNameLength); + } else { + *clientDriverName = NULL; + } + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetClientDriverName... return True"); + return True; +} + +Bool +uniDRICreateContextWithConfig(dpy, screen, configID, context, hHWContext) + Display *dpy; + int screen; + int configID; + XID *context; + drm_context_t *hHWContext; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRICreateContextReply rep; + xXF86DRICreateContextReq *req; + + TRACE("CreateContext..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRICreateContext, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRICreateContext; + req->visual = configID; + req->screen = screen; + *context = XAllocID(dpy); + req->context = *context; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("CreateContext... return False"); + return False; + } + *hHWContext = rep.hHWContext; + UnlockDisplay(dpy); + SyncHandle(); + TRACE("CreateContext... return True"); + return True; +} + +Bool +uniDRICreateContext(dpy, screen, visual, context, hHWContext) + Display *dpy; + int screen; + Visual *visual; + XID *context; + drm_context_t *hHWContext; +{ + return uniDRICreateContextWithConfig(dpy, screen, visual->visualid, + context, hHWContext); +} + +Bool +uniDRIDestroyContext(Display * ndpy, int screen, XID context) +{ + Display *const dpy = (Display *) ndpy; + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIDestroyContextReq *req; + + TRACE("DestroyContext..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIDestroyContext, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIDestroyContext; + req->screen = screen; + req->context = context; + UnlockDisplay(dpy); + SyncHandle(); + TRACE("DestroyContext... return True"); + return True; +} + +Bool +uniDRICreateDrawable(Display * ndpy, int screen, + Drawable drawable, drm_drawable_t * hHWDrawable) +{ + Display *const dpy = (Display *) ndpy; + XExtDisplayInfo *info = find_display(dpy); + xXF86DRICreateDrawableReply rep; + xXF86DRICreateDrawableReq *req; + + TRACE("CreateDrawable..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRICreateDrawable, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRICreateDrawable; + req->screen = screen; + req->drawable = drawable; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("CreateDrawable... return False"); + return False; + } + *hHWDrawable = rep.hHWDrawable; + UnlockDisplay(dpy); + SyncHandle(); + TRACE("CreateDrawable... return True"); + return True; +} + +Bool +uniDRIDestroyDrawable(Display * ndpy, int screen, Drawable drawable) +{ + Display *const dpy = (Display *) ndpy; + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIDestroyDrawableReq *req; + + TRACE("DestroyDrawable..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIDestroyDrawable, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIDestroyDrawable; + req->screen = screen; + req->drawable = drawable; + UnlockDisplay(dpy); + SyncHandle(); + TRACE("DestroyDrawable... return True"); + return True; +} + +Bool +uniDRIGetDrawableInfo(Display * dpy, int screen, Drawable drawable, + unsigned int *index, unsigned int *stamp, + int *X, int *Y, int *W, int *H, + int *numClipRects, drm_clip_rect_t ** pClipRects, + int *backX, int *backY, + int *numBackClipRects, drm_clip_rect_t ** pBackClipRects) +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIGetDrawableInfoReply rep; + xXF86DRIGetDrawableInfoReq *req; + int total_rects; + + TRACE("GetDrawableInfo..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIGetDrawableInfo, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIGetDrawableInfo; + req->screen = screen; + req->drawable = drawable; + + if (!_XReply(dpy, (xReply *) & rep, 1, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetDrawableInfo... return False"); + return False; + } + *index = rep.drawableTableIndex; + *stamp = rep.drawableTableStamp; + *X = (int)rep.drawableX; + *Y = (int)rep.drawableY; + *W = (int)rep.drawableWidth; + *H = (int)rep.drawableHeight; + *numClipRects = rep.numClipRects; + total_rects = *numClipRects; + + *backX = rep.backX; + *backY = rep.backY; + *numBackClipRects = rep.numBackClipRects; + total_rects += *numBackClipRects; + +#if 0 + /* Because of the fix in Xserver/GL/dri/xf86dri.c, this check breaks + * backwards compatibility (Because of the >> 2 shift) but the fix + * enables multi-threaded apps to work. + */ + if (rep.length != ((((SIZEOF(xXF86DRIGetDrawableInfoReply) - + SIZEOF(xGenericReply) + + total_rects * sizeof(drm_clip_rect_t)) + + 3) & ~3) >> 2)) { + _XEatData(dpy, rep.length); + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetDrawableInfo... return False"); + return False; + } +#endif + + if (*numClipRects) { + int len = sizeof(drm_clip_rect_t) * (*numClipRects); + + *pClipRects = (drm_clip_rect_t *) Xcalloc(len, 1); + if (*pClipRects) + _XRead(dpy, (char *)*pClipRects, len); + } else { + *pClipRects = NULL; + } + + if (*numBackClipRects) { + int len = sizeof(drm_clip_rect_t) * (*numBackClipRects); + + *pBackClipRects = (drm_clip_rect_t *) Xcalloc(len, 1); + if (*pBackClipRects) + _XRead(dpy, (char *)*pBackClipRects, len); + } else { + *pBackClipRects = NULL; + } + + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetDrawableInfo... return True"); + return True; +} + +Bool +uniDRIGetDeviceInfo(dpy, screen, hFrameBuffer, + fbOrigin, fbSize, fbStride, devPrivateSize, pDevPrivate) + Display *dpy; + int screen; + drm_handle_t *hFrameBuffer; + int *fbOrigin; + int *fbSize; + int *fbStride; + int *devPrivateSize; + void **pDevPrivate; +{ + XExtDisplayInfo *info = find_display(dpy); + xXF86DRIGetDeviceInfoReply rep; + xXF86DRIGetDeviceInfoReq *req; + + TRACE("GetDeviceInfo..."); + uniDRICheckExtension(dpy, info, False); + + LockDisplay(dpy); + GetReq(XF86DRIGetDeviceInfo, req); + req->reqType = info->codes->major_opcode; + req->driReqType = X_XF86DRIGetDeviceInfo; + req->screen = screen; + if (!_XReply(dpy, (xReply *) & rep, 0, xFalse)) { + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetDeviceInfo... return False"); + return False; + } + + *hFrameBuffer = rep.hFrameBufferLow; +#ifdef LONG64 + if (sizeof(drm_handle_t) == 8) { + *hFrameBuffer |= ((unsigned long)rep.hFrameBufferHigh) << 32; + } +#endif + + *fbOrigin = rep.framebufferOrigin; + *fbSize = rep.framebufferSize; + *fbStride = rep.framebufferStride; + *devPrivateSize = rep.devPrivateSize; + + if (rep.length) { + if (!(*pDevPrivate = (void *)Xcalloc(rep.devPrivateSize, 1))) { + _XEatData(dpy, ((rep.devPrivateSize + 3) & ~3)); + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetDeviceInfo... return False"); + return False; + } + _XRead(dpy, (char *)*pDevPrivate, rep.devPrivateSize); + } else { + *pDevPrivate = NULL; + } + + UnlockDisplay(dpy); + SyncHandle(); + TRACE("GetDeviceInfo... return True"); + return True; +} diff --git a/tests/ttmtest/src/xf86dri.h b/tests/ttmtest/src/xf86dri.h new file mode 100644 index 0000000..8fb7896 --- /dev/null +++ b/tests/ttmtest/src/xf86dri.h @@ -0,0 +1,116 @@ +/* $XFree86: xc/lib/GL/dri/xf86dri.h,v 1.8 2002/10/30 12:51:25 alanh Exp $ */ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +Copyright 2000 VA Linux Systems, Inc. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/** + * \file xf86dri.h + * Protocol numbers and function prototypes for DRI X protocol. + * + * \author Kevin E. Martin + * \author Jens Owen + * \author Rickard E. (Rik) Faith + */ + +#ifndef _XF86DRI_H_ +#define _XF86DRI_H_ + +#include +#include + +#define X_XF86DRIQueryVersion 0 +#define X_XF86DRIQueryDirectRenderingCapable 1 +#define X_XF86DRIOpenConnection 2 +#define X_XF86DRICloseConnection 3 +#define X_XF86DRIGetClientDriverName 4 +#define X_XF86DRICreateContext 5 +#define X_XF86DRIDestroyContext 6 +#define X_XF86DRICreateDrawable 7 +#define X_XF86DRIDestroyDrawable 8 +#define X_XF86DRIGetDrawableInfo 9 +#define X_XF86DRIGetDeviceInfo 10 +#define X_XF86DRIAuthConnection 11 +#define X_XF86DRIOpenFullScreen 12 /* Deprecated */ +#define X_XF86DRICloseFullScreen 13 /* Deprecated */ + +#define XF86DRINumberEvents 0 + +#define XF86DRIClientNotLocal 0 +#define XF86DRIOperationNotSupported 1 +#define XF86DRINumberErrors (XF86DRIOperationNotSupported + 1) + +#ifndef _XF86DRI_SERVER_ + +_XFUNCPROTOBEGIN + Bool uniDRIQueryExtension(Display * dpy, int *event_base, + int *error_base); + +Bool uniDRIQueryVersion(Display * dpy, int *majorVersion, int *minorVersion, + int *patchVersion); + +Bool uniDRIQueryDirectRenderingCapable(Display * dpy, int screen, + Bool * isCapable); + +Bool uniDRIOpenConnection(Display * dpy, int screen, drm_handle_t * hSAREA, + char **busIDString); + +Bool uniDRIAuthConnection(Display * dpy, int screen, drm_magic_t magic); + +Bool uniDRICloseConnection(Display * dpy, int screen); + +Bool uniDRIGetClientDriverName(Display * dpy, int screen, + int *ddxDriverMajorVersion, int *ddxDriverMinorVersion, + int *ddxDriverPatchVersion, char **clientDriverName); + +Bool uniDRICreateContext(Display * dpy, int screen, Visual * visual, + XID * ptr_to_returned_context_id, drm_context_t * hHWContext); + +Bool uniDRICreateContextWithConfig(Display * dpy, int screen, int configID, + XID * ptr_to_returned_context_id, drm_context_t * hHWContext); + +extern Bool uniDRIDestroyContext(Display * dpy, int screen, XID context_id); + +extern Bool uniDRICreateDrawable(Display * dpy, int screen, + Drawable drawable, drm_drawable_t * hHWDrawable); + +extern Bool uniDRIDestroyDrawable(Display * dpy, int screen, + Drawable drawable); + +Bool uniDRIGetDrawableInfo(Display * dpy, int screen, Drawable drawable, + unsigned int *index, unsigned int *stamp, + int *X, int *Y, int *W, int *H, + int *numClipRects, drm_clip_rect_t ** pClipRects, + int *backX, int *backY, + int *numBackClipRects, drm_clip_rect_t ** pBackClipRects); + +Bool uniDRIGetDeviceInfo(Display * dpy, int screen, + drm_handle_t * hFrameBuffer, int *fbOrigin, int *fbSize, + int *fbStride, int *devPrivateSize, void **pDevPrivate); + +_XFUNCPROTOEND +#endif /* _XF86DRI_SERVER_ */ +#endif /* _XF86DRI_H_ */ diff --git a/tests/ttmtest/src/xf86dristr.h b/tests/ttmtest/src/xf86dristr.h new file mode 100644 index 0000000..3b43438 --- /dev/null +++ b/tests/ttmtest/src/xf86dristr.h @@ -0,0 +1,390 @@ +/* $XFree86: xc/lib/GL/dri/xf86dristr.h,v 1.10 2002/10/30 12:51:25 alanh Exp $ */ +/************************************************************************** + +Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. +Copyright 2000 VA Linux Systems, Inc. +All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sub license, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice (including the +next paragraph) shall be included in all copies or substantial portions +of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. +IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR +ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE +SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +**************************************************************************/ + +/* + * Authors: + * Kevin E. Martin + * Jens Owen + * Rickard E. (Rik) Fiath + * + */ + +#ifndef _XF86DRISTR_H_ +#define _XF86DRISTR_H_ + +#include "xf86dri.h" + +#define XF86DRINAME "XFree86-DRI" + +/* The DRI version number. This was originally set to be the same of the + * XFree86 version number. However, this version is really indepedent of + * the XFree86 version. + * + * Version History: + * 4.0.0: Original + * 4.0.1: Patch to bump clipstamp when windows are destroyed, 28 May 02 + * 4.1.0: Add transition from single to multi in DRMInfo rec, 24 Jun 02 + */ +#define XF86DRI_MAJOR_VERSION 4 +#define XF86DRI_MINOR_VERSION 1 +#define XF86DRI_PATCH_VERSION 0 + +typedef struct _XF86DRIQueryVersion +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIQueryVersion */ + CARD16 length B16; +} xXF86DRIQueryVersionReq; + +#define sz_xXF86DRIQueryVersionReq 4 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD16 majorVersion B16; /* major version of DRI protocol */ + CARD16 minorVersion B16; /* minor version of DRI protocol */ + CARD32 patchVersion B32; /* patch version of DRI protocol */ + CARD32 pad3 B32; + CARD32 pad4 B32; + CARD32 pad5 B32; + CARD32 pad6 B32; +} xXF86DRIQueryVersionReply; + +#define sz_xXF86DRIQueryVersionReply 32 + +typedef struct _XF86DRIQueryDirectRenderingCapable +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* X_DRIQueryDirectRenderingCapable */ + CARD16 length B16; + CARD32 screen B32; +} xXF86DRIQueryDirectRenderingCapableReq; + +#define sz_xXF86DRIQueryDirectRenderingCapableReq 8 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + BOOL isCapable; + BOOL pad2; + BOOL pad3; + BOOL pad4; + CARD32 pad5 B32; + CARD32 pad6 B32; + CARD32 pad7 B32; + CARD32 pad8 B32; + CARD32 pad9 B32; +} xXF86DRIQueryDirectRenderingCapableReply; + +#define sz_xXF86DRIQueryDirectRenderingCapableReply 32 + +typedef struct _XF86DRIOpenConnection +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIOpenConnection */ + CARD16 length B16; + CARD32 screen B32; +} xXF86DRIOpenConnectionReq; + +#define sz_xXF86DRIOpenConnectionReq 8 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 hSAREALow B32; + CARD32 hSAREAHigh B32; + CARD32 busIdStringLength B32; + CARD32 pad6 B32; + CARD32 pad7 B32; + CARD32 pad8 B32; +} xXF86DRIOpenConnectionReply; + +#define sz_xXF86DRIOpenConnectionReply 32 + +typedef struct _XF86DRIAuthConnection +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRICloseConnection */ + CARD16 length B16; + CARD32 screen B32; + CARD32 magic B32; +} xXF86DRIAuthConnectionReq; + +#define sz_xXF86DRIAuthConnectionReq 12 + +typedef struct +{ + BYTE type; + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 authenticated B32; + CARD32 pad2 B32; + CARD32 pad3 B32; + CARD32 pad4 B32; + CARD32 pad5 B32; + CARD32 pad6 B32; +} xXF86DRIAuthConnectionReply; + +#define zx_xXF86DRIAuthConnectionReply 32 + +typedef struct _XF86DRICloseConnection +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRICloseConnection */ + CARD16 length B16; + CARD32 screen B32; +} xXF86DRICloseConnectionReq; + +#define sz_xXF86DRICloseConnectionReq 8 + +typedef struct _XF86DRIGetClientDriverName +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIGetClientDriverName */ + CARD16 length B16; + CARD32 screen B32; +} xXF86DRIGetClientDriverNameReq; + +#define sz_xXF86DRIGetClientDriverNameReq 8 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 ddxDriverMajorVersion B32; + CARD32 ddxDriverMinorVersion B32; + CARD32 ddxDriverPatchVersion B32; + CARD32 clientDriverNameLength B32; + CARD32 pad5 B32; + CARD32 pad6 B32; +} xXF86DRIGetClientDriverNameReply; + +#define sz_xXF86DRIGetClientDriverNameReply 32 + +typedef struct _XF86DRICreateContext +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRICreateContext */ + CARD16 length B16; + CARD32 screen B32; + CARD32 visual B32; + CARD32 context B32; +} xXF86DRICreateContextReq; + +#define sz_xXF86DRICreateContextReq 16 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 hHWContext B32; + CARD32 pad2 B32; + CARD32 pad3 B32; + CARD32 pad4 B32; + CARD32 pad5 B32; + CARD32 pad6 B32; +} xXF86DRICreateContextReply; + +#define sz_xXF86DRICreateContextReply 32 + +typedef struct _XF86DRIDestroyContext +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIDestroyContext */ + CARD16 length B16; + CARD32 screen B32; + CARD32 context B32; +} xXF86DRIDestroyContextReq; + +#define sz_xXF86DRIDestroyContextReq 12 + +typedef struct _XF86DRICreateDrawable +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRICreateDrawable */ + CARD16 length B16; + CARD32 screen B32; + CARD32 drawable B32; +} xXF86DRICreateDrawableReq; + +#define sz_xXF86DRICreateDrawableReq 12 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 hHWDrawable B32; + CARD32 pad2 B32; + CARD32 pad3 B32; + CARD32 pad4 B32; + CARD32 pad5 B32; + CARD32 pad6 B32; +} xXF86DRICreateDrawableReply; + +#define sz_xXF86DRICreateDrawableReply 32 + +typedef struct _XF86DRIDestroyDrawable +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIDestroyDrawable */ + CARD16 length B16; + CARD32 screen B32; + CARD32 drawable B32; +} xXF86DRIDestroyDrawableReq; + +#define sz_xXF86DRIDestroyDrawableReq 12 + +typedef struct _XF86DRIGetDrawableInfo +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIGetDrawableInfo */ + CARD16 length B16; + CARD32 screen B32; + CARD32 drawable B32; +} xXF86DRIGetDrawableInfoReq; + +#define sz_xXF86DRIGetDrawableInfoReq 12 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 drawableTableIndex B32; + CARD32 drawableTableStamp B32; + INT16 drawableX B16; + INT16 drawableY B16; + INT16 drawableWidth B16; + INT16 drawableHeight B16; + CARD32 numClipRects B32; + INT16 backX B16; + INT16 backY B16; + CARD32 numBackClipRects B32; +} xXF86DRIGetDrawableInfoReply; + +#define sz_xXF86DRIGetDrawableInfoReply 36 + +typedef struct _XF86DRIGetDeviceInfo +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIGetDeviceInfo */ + CARD16 length B16; + CARD32 screen B32; +} xXF86DRIGetDeviceInfoReq; + +#define sz_xXF86DRIGetDeviceInfoReq 8 + +typedef struct +{ + BYTE type; /* X_Reply */ + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 hFrameBufferLow B32; + CARD32 hFrameBufferHigh B32; + CARD32 framebufferOrigin B32; + CARD32 framebufferSize B32; + CARD32 framebufferStride B32; + CARD32 devPrivateSize B32; +} xXF86DRIGetDeviceInfoReply; + +#define sz_xXF86DRIGetDeviceInfoReply 32 + +typedef struct _XF86DRIOpenFullScreen +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRIOpenFullScreen */ + CARD16 length B16; + CARD32 screen B32; + CARD32 drawable B32; +} xXF86DRIOpenFullScreenReq; + +#define sz_xXF86DRIOpenFullScreenReq 12 + +typedef struct +{ + BYTE type; + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 isFullScreen B32; + CARD32 pad2 B32; + CARD32 pad3 B32; + CARD32 pad4 B32; + CARD32 pad5 B32; + CARD32 pad6 B32; +} xXF86DRIOpenFullScreenReply; + +#define sz_xXF86DRIOpenFullScreenReply 32 + +typedef struct _XF86DRICloseFullScreen +{ + CARD8 reqType; /* always DRIReqCode */ + CARD8 driReqType; /* always X_DRICloseFullScreen */ + CARD16 length B16; + CARD32 screen B32; + CARD32 drawable B32; +} xXF86DRICloseFullScreenReq; + +#define sz_xXF86DRICloseFullScreenReq 12 + +typedef struct +{ + BYTE type; + BOOL pad1; + CARD16 sequenceNumber B16; + CARD32 length B32; + CARD32 pad2 B32; + CARD32 pad3 B32; + CARD32 pad4 B32; + CARD32 pad5 B32; + CARD32 pad6 B32; + CARD32 pad7 B32; +} xXF86DRICloseFullScreenReply; + +#define sz_xXF86DRICloseFullScreenReply 32 + +#endif /* _XF86DRISTR_H_ */ diff --git a/tests/updatedraw.c b/tests/updatedraw.c new file mode 100644 index 0000000..a61eb15 --- /dev/null +++ b/tests/updatedraw.c @@ -0,0 +1,153 @@ +/* + * Copyright © 2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include "drmtest.h" + +static void +set_draw_cliprects_empty(int fd, int drawable) +{ + int ret; + struct drm_update_draw update; + + update.handle = drawable; + update.type = DRM_DRAWABLE_CLIPRECTS; + update.num = 0; + update.data = 0; + + ret = ioctl(fd, DRM_IOCTL_UPDATE_DRAW, &update); + assert(ret == 0); +} + +static void +set_draw_cliprects_empty_fail(int fd, int drawable) +{ + int ret; + struct drm_update_draw update; + + update.handle = drawable; + update.type = DRM_DRAWABLE_CLIPRECTS; + update.num = 0; + update.data = 0; + + ret = ioctl(fd, DRM_IOCTL_UPDATE_DRAW, &update); + assert(ret == -1 && errno == EINVAL); +} + +static void +set_draw_cliprects_2(int fd, int drawable) +{ + int ret; + struct drm_update_draw update; + drm_clip_rect_t rects[2]; + + rects[0].x1 = 0; + rects[0].y1 = 0; + rects[0].x2 = 10; + rects[0].y2 = 10; + + rects[1].x1 = 10; + rects[1].y1 = 10; + rects[1].x2 = 20; + rects[1].y2 = 20; + + update.handle = drawable; + update.type = DRM_DRAWABLE_CLIPRECTS; + update.num = 2; + update.data = (unsigned long long)(uintptr_t)&rects; + + ret = ioctl(fd, DRM_IOCTL_UPDATE_DRAW, &update); + assert(ret == 0); +} + +static int add_drawable(int fd) +{ + drm_draw_t drawarg; + int ret; + + /* Create a drawable. + * IOCTL_ADD_DRAW is RDWR, though it should really just be RD + */ + drawarg.handle = 0; + ret = ioctl(fd, DRM_IOCTL_ADD_DRAW, &drawarg); + assert(ret == 0); + return drawarg.handle; +} + +static int rm_drawable(int fd, int drawable, int fail) +{ + drm_draw_t drawarg; + int ret; + + /* Create a drawable. + * IOCTL_ADD_DRAW is RDWR, though it should really just be RD + */ + drawarg.handle = drawable; + ret = ioctl(fd, DRM_IOCTL_RM_DRAW, &drawarg); + if (!fail) + assert(ret == 0); + else + assert(ret == -1 && errno == EINVAL); + + return drawarg.handle; +} + +/** + * Tests drawable management: adding, removing, and updating the cliprects of + * drawables. + */ +int main(int argc, char **argv) +{ + int fd, ret, d1, d2; + + if (getuid() != 0) { + fprintf(stderr, "updatedraw test requires root, skipping\n"); + return 0; + } + + fd = drm_open_any_master(); + + d1 = add_drawable(fd); + d2 = add_drawable(fd); + /* Do a series of cliprect updates */ + set_draw_cliprects_empty(fd, d1); + set_draw_cliprects_empty(fd, d2); + set_draw_cliprects_2(fd, d1); + set_draw_cliprects_empty(fd, d1); + + /* Remove our drawables */ + rm_drawable(fd, d1, 0); + rm_drawable(fd, d2, 0); + + /* Check that removing an unknown drawable returns error */ + rm_drawable(fd, 0x7fffffff, 1); + + /* Attempt to set cliprects on a nonexistent drawable */ + set_draw_cliprects_empty_fail(fd, d1); + + close(fd); + return 0; +} diff --git a/tests/vbltest/Makefile.am b/tests/vbltest/Makefile.am new file mode 100644 index 0000000..77f9037 --- /dev/null +++ b/tests/vbltest/Makefile.am @@ -0,0 +1,11 @@ +AM_CFLAGS = \ + -I$(top_srcdir)/include/drm \ + -I$(top_srcdir) + +noinst_PROGRAMS = \ + vbltest + +vbltest_SOURCES = \ + vbltest.c +vbltest_LDADD = \ + $(top_builddir)/libdrm.la diff --git a/tests/vbltest/vbltest.c b/tests/vbltest/vbltest.c new file mode 100644 index 0000000..4fccd59 --- /dev/null +++ b/tests/vbltest/vbltest.c @@ -0,0 +1,200 @@ +/* + * DRM based mode setting test program + * Copyright 2008 Tungsten Graphics + * Jakob Bornecrantz + * Copyright 2008 Intel Corporation + * Jesse Barnes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +/* + * This fairly simple test program dumps output in a similar format to the + * "xrandr" tool everyone knows & loves. It's necessarily slightly different + * since the kernel separates outputs into encoder and connector structures, + * each with their own unique ID. The program also allows test testing of the + * memory management and mode setting APIs by allowing the user to specify a + * connector and mode to use for mode setting. If all works as expected, a + * blue background should be painted on the monitor attached to the specified + * connector after the selected mode is set. + * + * TODO: use cairo to write the mode info on the selected output once + * the mode has been programmed, along with possible test patterns. + */ +#include "config.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "xf86drm.h" +#include "xf86drmMode.h" + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +extern char *optarg; +extern int optind, opterr, optopt; +static char optstr[] = "s"; + +int secondary = 0; + +struct vbl_info { + unsigned int vbl_count; + struct timeval start; +}; + +static void vblank_handler(int fd, unsigned int frame, unsigned int sec, + unsigned int usec, void *data) +{ + drmVBlank vbl; + struct timeval end; + struct vbl_info *info = data; + double t; + + vbl.request.type = DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT; + if (secondary) + vbl.request.type |= DRM_VBLANK_SECONDARY; + vbl.request.sequence = 1; + vbl.request.signal = (unsigned long)data; + + drmWaitVBlank(fd, &vbl); + + info->vbl_count++; + + if (info->vbl_count == 60) { + gettimeofday(&end, NULL); + t = end.tv_sec + end.tv_usec * 1e-6 - + (info->start.tv_sec + info->start.tv_usec * 1e-6); + fprintf(stderr, "freq: %.02fHz\n", info->vbl_count / t); + info->vbl_count = 0; + info->start = end; + } +} + +static void usage(char *name) +{ + fprintf(stderr, "usage: %s [-s]\n", name); + fprintf(stderr, "\t-s\tuse secondary pipe\n"); + exit(0); +} + +int main(int argc, char **argv) +{ + int i, c, fd, ret; + char *modules[] = { "i915", "radeon", "nouveau", "vmwgfx", "exynos" }; + drmVBlank vbl; + drmEventContext evctx; + struct vbl_info handler_info; + + opterr = 0; + while ((c = getopt(argc, argv, optstr)) != -1) { + switch (c) { + case 's': + secondary = 1; + break; + default: + usage(argv[0]); + break; + } + } + + for (i = 0; i < ARRAY_SIZE(modules); i++) { + printf("trying to load module %s...", modules[i]); + fd = drmOpen(modules[i], NULL); + if (fd < 0) { + printf("failed.\n"); + } else { + printf("success.\n"); + break; + } + } + + if (i == ARRAY_SIZE(modules)) { + fprintf(stderr, "failed to load any modules, aborting.\n"); + return -1; + } + + /* Get current count first */ + vbl.request.type = DRM_VBLANK_RELATIVE; + if (secondary) + vbl.request.type |= DRM_VBLANK_SECONDARY; + vbl.request.sequence = 0; + ret = drmWaitVBlank(fd, &vbl); + if (ret != 0) { + printf("drmWaitVBlank (relative) failed ret: %i\n", ret); + return -1; + } + + printf("starting count: %d\n", vbl.request.sequence); + + handler_info.vbl_count = 0; + gettimeofday(&handler_info.start, NULL); + + /* Queue an event for frame + 1 */ + vbl.request.type = DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT; + if (secondary) + vbl.request.type |= DRM_VBLANK_SECONDARY; + vbl.request.sequence = 1; + vbl.request.signal = (unsigned long)&handler_info; + ret = drmWaitVBlank(fd, &vbl); + if (ret != 0) { + printf("drmWaitVBlank (relative, event) failed ret: %i\n", ret); + return -1; + } + + /* Set up our event handler */ + memset(&evctx, 0, sizeof evctx); + evctx.version = DRM_EVENT_CONTEXT_VERSION; + evctx.vblank_handler = vblank_handler; + evctx.page_flip_handler = NULL; + + /* Poll for events */ + while (1) { + struct timeval timeout = { .tv_sec = 3, .tv_usec = 0 }; + fd_set fds; + int ret; + + FD_ZERO(&fds); + FD_SET(0, &fds); + FD_SET(fd, &fds); + ret = select(fd + 1, &fds, NULL, NULL, &timeout); + + if (ret <= 0) { + fprintf(stderr, "select timed out or error (ret %d)\n", + ret); + continue; + } else if (FD_ISSET(0, &fds)) { + break; + } + + ret = drmHandleEvent(fd, &evctx); + if (ret != 0) { + printf("drmHandleEvent failed: %i\n", ret); + return -1; + } + } + + return 0; +} diff --git a/xf86atomic.h b/xf86atomic.h new file mode 100644 index 0000000..db2f619 --- /dev/null +++ b/xf86atomic.h @@ -0,0 +1,99 @@ +/* + * Copyright © 2009 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Chris Wilson + * + */ + +/** + * @file xf86atomics.h + * + * Private definitions for atomic operations + */ + +#ifndef LIBDRM_ATOMICS_H +#define LIBDRM_ATOMICS_H + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#if HAVE_LIBDRM_ATOMIC_PRIMITIVES + +#define HAS_ATOMIC_OPS 1 + +typedef struct { + int atomic; +} atomic_t; + +# define atomic_read(x) ((x)->atomic) +# define atomic_set(x, val) ((x)->atomic = (val)) +# define atomic_inc(x) ((void) __sync_fetch_and_add (&(x)->atomic, 1)) +# define atomic_dec_and_test(x) (__sync_fetch_and_add (&(x)->atomic, -1) == 1) +# define atomic_add(x, v) ((void) __sync_add_and_fetch(&(x)->atomic, (v))) +# define atomic_dec(x, v) ((void) __sync_sub_and_fetch(&(x)->atomic, (v))) +# define atomic_cmpxchg(x, oldv, newv) __sync_val_compare_and_swap (&(x)->atomic, oldv, newv) + +#endif + +#if HAVE_LIB_ATOMIC_OPS +#include + +#define HAS_ATOMIC_OPS 1 + +typedef struct { + AO_t atomic; +} atomic_t; + +# define atomic_read(x) AO_load_full(&(x)->atomic) +# define atomic_set(x, val) AO_store_full(&(x)->atomic, (val)) +# define atomic_inc(x) ((void) AO_fetch_and_add1_full(&(x)->atomic)) +# define atomic_add(x, v) ((void) AO_fetch_and_add_full(&(x)->atomic, (v))) +# define atomic_dec(x, v) ((void) AO_fetch_and_add_full(&(x)->atomic, -(v))) +# define atomic_dec_and_test(x) (AO_fetch_and_sub1_full(&(x)->atomic) == 1) +# define atomic_cmpxchg(x, oldv, newv) AO_compare_and_swap_full(&(x)->atomic, oldv, newv) + +#endif + +#if defined(__sun) && !defined(HAS_ATOMIC_OPS) /* Solaris & OpenSolaris */ + +#include +#define HAS_ATOMIC_OPS 1 + +typedef struct { uint_t atomic; } atomic_t; + +# define atomic_read(x) (int) ((x)->atomic) +# define atomic_set(x, val) ((x)->atomic = (uint_t)(val)) +# define atomic_inc(x) (atomic_inc_uint (&(x)->atomic)) +# define atomic_dec_and_test(x) (atomic_dec_uint_nv(&(x)->atomic) == 1) +# define atomic_add(x, v) (atomic_add_int(&(x)->atomic, (v))) +# define atomic_dec(x, v) (atomic_add_int(&(x)->atomic, -(v))) +# define atomic_cmpxchg(x, oldv, newv) atomic_cas_uint (&(x)->atomic, oldv, newv) + +#endif + +#if ! HAS_ATOMIC_OPS +#error libdrm requires atomic operations, please define them for your CPU/compiler. +#endif + +#endif diff --git a/xf86drm.c b/xf86drm.c new file mode 100644 index 0000000..6ea068f --- /dev/null +++ b/xf86drm.c @@ -0,0 +1,2544 @@ +/** + * \file xf86drm.c + * User-level interface to DRM device + * + * \author Rickard E. (Rik) Faith + * \author Kevin E. Martin + */ + +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifdef HAVE_CONFIG_H +# include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#define stat_t struct stat +#include +#include +#include +#include + +/* Not all systems have MAP_FAILED defined */ +#ifndef MAP_FAILED +#define MAP_FAILED ((void *)-1) +#endif + +#include "xf86drm.h" + +#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) +#define DRM_MAJOR 145 +#endif + +#ifdef __NetBSD__ +#define DRM_MAJOR 34 +#endif + +# ifdef __OpenBSD__ +# define DRM_MAJOR 81 +# endif + +#ifndef DRM_MAJOR +#define DRM_MAJOR 226 /* Linux */ +#endif + +/* + * This definition needs to be changed on some systems if dev_t is a structure. + * If there is a header file we can get it from, there would be best. + */ +#ifndef makedev +#define makedev(x,y) ((dev_t)(((x) << 8) | (y))) +#endif + +#define DRM_MSG_VERBOSITY 3 + +#define DRM_NODE_CONTROL 0 +#define DRM_NODE_RENDER 1 + +static drmServerInfoPtr drm_server_info; + +void drmSetServerInfo(drmServerInfoPtr info) +{ + drm_server_info = info; +} + +/** + * Output a message to stderr. + * + * \param format printf() like format string. + * + * \internal + * This function is a wrapper around vfprintf(). + */ + +static int drmDebugPrint(const char *format, va_list ap) +{ + return vfprintf(stderr, format, ap); +} + +static int (*drm_debug_print)(const char *format, va_list ap) = drmDebugPrint; + +void +drmMsg(const char *format, ...) +{ + va_list ap; + const char *env; + if (((env = getenv("LIBGL_DEBUG")) && strstr(env, "verbose")) || drm_server_info) + { + va_start(ap, format); + if (drm_server_info) { + drm_server_info->debug_print(format,ap); + } else { + drm_debug_print(format, ap); + } + va_end(ap); + } +} + +void +drmSetDebugMsgFunction(int (*debug_msg_ptr)(const char *format, va_list ap)) +{ + drm_debug_print = debug_msg_ptr; +} + +static void *drmHashTable = NULL; /* Context switch callbacks */ + +void *drmGetHashTable(void) +{ + return drmHashTable; +} + +void *drmMalloc(int size) +{ + void *pt; + if ((pt = malloc(size))) + memset(pt, 0, size); + return pt; +} + +void drmFree(void *pt) +{ + if (pt) + free(pt); +} + +/** + * Call ioctl, restarting if it is interupted + */ +int +drmIoctl(int fd, unsigned long request, void *arg) +{ + int ret; + + do { + ret = ioctl(fd, request, arg); + } while (ret == -1 && (errno == EINTR || errno == EAGAIN)); + return ret; +} + +static unsigned long drmGetKeyFromFd(int fd) +{ + stat_t st; + + st.st_rdev = 0; + fstat(fd, &st); + return st.st_rdev; +} + +drmHashEntry *drmGetEntry(int fd) +{ + unsigned long key = drmGetKeyFromFd(fd); + void *value; + drmHashEntry *entry; + + if (!drmHashTable) + drmHashTable = drmHashCreate(); + + if (drmHashLookup(drmHashTable, key, &value)) { + entry = drmMalloc(sizeof(*entry)); + entry->fd = fd; + entry->f = NULL; + entry->tagTable = drmHashCreate(); + drmHashInsert(drmHashTable, key, entry); + } else { + entry = value; + } + return entry; +} + +/** + * Compare two busid strings + * + * \param first + * \param second + * + * \return 1 if matched. + * + * \internal + * This function compares two bus ID strings. It understands the older + * PCI:b:d:f format and the newer pci:oooo:bb:dd.f format. In the format, o is + * domain, b is bus, d is device, f is function. + */ +static int drmMatchBusID(const char *id1, const char *id2, int pci_domain_ok) +{ + /* First, check if the IDs are exactly the same */ + if (strcasecmp(id1, id2) == 0) + return 1; + + /* Try to match old/new-style PCI bus IDs. */ + if (strncasecmp(id1, "pci", 3) == 0) { + unsigned int o1, b1, d1, f1; + unsigned int o2, b2, d2, f2; + int ret; + + ret = sscanf(id1, "pci:%04x:%02x:%02x.%u", &o1, &b1, &d1, &f1); + if (ret != 4) { + o1 = 0; + ret = sscanf(id1, "PCI:%u:%u:%u", &b1, &d1, &f1); + if (ret != 3) + return 0; + } + + ret = sscanf(id2, "pci:%04x:%02x:%02x.%u", &o2, &b2, &d2, &f2); + if (ret != 4) { + o2 = 0; + ret = sscanf(id2, "PCI:%u:%u:%u", &b2, &d2, &f2); + if (ret != 3) + return 0; + } + + /* If domains aren't properly supported by the kernel interface, + * just ignore them, which sucks less than picking a totally random + * card with "open by name" + */ + if (!pci_domain_ok) + o1 = o2 = 0; + + if ((o1 != o2) || (b1 != b2) || (d1 != d2) || (f1 != f2)) + return 0; + else + return 1; + } + return 0; +} + +/** + * Handles error checking for chown call. + * + * \param path to file. + * \param id of the new owner. + * \param id of the new group. + * + * \return zero if success or -1 if failure. + * + * \internal + * Checks for failure. If failure was caused by signal call chown again. + * If any other failure happened then it will output error mesage using + * drmMsg() call. + */ +static int chown_check_return(const char *path, uid_t owner, gid_t group) +{ + int rv; + + do { + rv = chown(path, owner, group); + } while (rv != 0 && errno == EINTR); + + if (rv == 0) + return 0; + + drmMsg("Failed to change owner or group for file %s! %d: %s\n", + path, errno, strerror(errno)); + return -1; +} + +/** + * Open the DRM device, creating it if necessary. + * + * \param dev major and minor numbers of the device. + * \param minor minor number of the device. + * + * \return a file descriptor on success, or a negative value on error. + * + * \internal + * Assembles the device name from \p minor and opens it, creating the device + * special file node with the major and minor numbers specified by \p dev and + * parent directory if necessary and was called by root. + */ +static int drmOpenDevice(long dev, int minor, int type) +{ + stat_t st; + char buf[64]; + int fd; + mode_t devmode = DRM_DEV_MODE, serv_mode; + int isroot = !geteuid(); + uid_t user = DRM_DEV_UID; + gid_t group = DRM_DEV_GID, serv_group; + + sprintf(buf, type ? DRM_DEV_NAME : DRM_CONTROL_DEV_NAME, DRM_DIR_NAME, minor); + drmMsg("drmOpenDevice: node name is %s\n", buf); + + if (drm_server_info) { + drm_server_info->get_perms(&serv_group, &serv_mode); + devmode = serv_mode ? serv_mode : DRM_DEV_MODE; + devmode &= ~(S_IXUSR|S_IXGRP|S_IXOTH); + group = (serv_group >= 0) ? serv_group : DRM_DEV_GID; + } + +#if !defined(UDEV) + if (stat(DRM_DIR_NAME, &st)) { + if (!isroot) + return DRM_ERR_NOT_ROOT; + mkdir(DRM_DIR_NAME, DRM_DEV_DIRMODE); + chown_check_return(DRM_DIR_NAME, 0, 0); /* root:root */ + chmod(DRM_DIR_NAME, DRM_DEV_DIRMODE); + } + + /* Check if the device node exists and create it if necessary. */ + if (stat(buf, &st)) { + if (!isroot) + return DRM_ERR_NOT_ROOT; + remove(buf); + mknod(buf, S_IFCHR | devmode, dev); + } + + if (drm_server_info) { + chown_check_return(buf, user, group); + chmod(buf, devmode); + } +#else + /* if we modprobed then wait for udev */ + { + int udev_count = 0; +wait_for_udev: + if (stat(DRM_DIR_NAME, &st)) { + usleep(20); + udev_count++; + + if (udev_count == 50) + return -1; + goto wait_for_udev; + } + + if (stat(buf, &st)) { + usleep(20); + udev_count++; + + if (udev_count == 50) + return -1; + goto wait_for_udev; + } + } +#endif + + fd = open(buf, O_RDWR, 0); + drmMsg("drmOpenDevice: open result is %d, (%s)\n", + fd, fd < 0 ? strerror(errno) : "OK"); + if (fd >= 0) + return fd; + +#if !defined(UDEV) + /* Check if the device node is not what we expect it to be, and recreate it + * and try again if so. + */ + if (st.st_rdev != dev) { + if (!isroot) + return DRM_ERR_NOT_ROOT; + remove(buf); + mknod(buf, S_IFCHR | devmode, dev); + if (drm_server_info) { + chown_check_return(buf, user, group); + chmod(buf, devmode); + } + } + fd = open(buf, O_RDWR, 0); + drmMsg("drmOpenDevice: open result is %d, (%s)\n", + fd, fd < 0 ? strerror(errno) : "OK"); + if (fd >= 0) + return fd; + + drmMsg("drmOpenDevice: Open failed\n"); + remove(buf); +#endif + return -errno; +} + + +/** + * Open the DRM device + * + * \param minor device minor number. + * \param create allow to create the device if set. + * + * \return a file descriptor on success, or a negative value on error. + * + * \internal + * Calls drmOpenDevice() if \p create is set, otherwise assembles the device + * name from \p minor and opens it. + */ +static int drmOpenMinor(int minor, int create, int type) +{ + int fd; + char buf[64]; + + if (create) + return drmOpenDevice(makedev(DRM_MAJOR, minor), minor, type); + + sprintf(buf, type ? DRM_DEV_NAME : DRM_CONTROL_DEV_NAME, DRM_DIR_NAME, minor); + if ((fd = open(buf, O_RDWR, 0)) >= 0) + return fd; + return -errno; +} + + +/** + * Determine whether the DRM kernel driver has been loaded. + * + * \return 1 if the DRM driver is loaded, 0 otherwise. + * + * \internal + * Determine the presence of the kernel driver by attempting to open the 0 + * minor and get version information. For backward compatibility with older + * Linux implementations, /proc/dri is also checked. + */ +int drmAvailable(void) +{ + drmVersionPtr version; + int retval = 0; + int fd; + + if ((fd = drmOpenMinor(0, 1, DRM_NODE_RENDER)) < 0) { +#ifdef __linux__ + /* Try proc for backward Linux compatibility */ + if (!access("/proc/dri/0", R_OK)) + return 1; +#endif + return 0; + } + + if ((version = drmGetVersion(fd))) { + retval = 1; + drmFreeVersion(version); + } + close(fd); + + return retval; +} + + +/** + * Open the device by bus ID. + * + * \param busid bus ID. + * + * \return a file descriptor on success, or a negative value on error. + * + * \internal + * This function attempts to open every possible minor (up to DRM_MAX_MINOR), + * comparing the device bus ID with the one supplied. + * + * \sa drmOpenMinor() and drmGetBusid(). + */ +static int drmOpenByBusid(const char *busid) +{ + int i, pci_domain_ok = 1; + int fd; + const char *buf; + drmSetVersion sv; + + drmMsg("drmOpenByBusid: Searching for BusID %s\n", busid); + for (i = 0; i < DRM_MAX_MINOR; i++) { + fd = drmOpenMinor(i, 1, DRM_NODE_RENDER); + drmMsg("drmOpenByBusid: drmOpenMinor returns %d\n", fd); + if (fd >= 0) { + /* We need to try for 1.4 first for proper PCI domain support + * and if that fails, we know the kernel is busted + */ + sv.drm_di_major = 1; + sv.drm_di_minor = 4; + sv.drm_dd_major = -1; /* Don't care */ + sv.drm_dd_minor = -1; /* Don't care */ + if (drmSetInterfaceVersion(fd, &sv)) { +#ifndef __alpha__ + pci_domain_ok = 0; +#endif + sv.drm_di_major = 1; + sv.drm_di_minor = 1; + sv.drm_dd_major = -1; /* Don't care */ + sv.drm_dd_minor = -1; /* Don't care */ + drmMsg("drmOpenByBusid: Interface 1.4 failed, trying 1.1\n",fd); + drmSetInterfaceVersion(fd, &sv); + } + buf = drmGetBusid(fd); + drmMsg("drmOpenByBusid: drmGetBusid reports %s\n", buf); + if (buf && drmMatchBusID(buf, busid, pci_domain_ok)) { + drmFreeBusid(buf); + return fd; + } + if (buf) + drmFreeBusid(buf); + close(fd); + } + } + return -1; +} + + +/** + * Open the device by name. + * + * \param name driver name. + * + * \return a file descriptor on success, or a negative value on error. + * + * \internal + * This function opens the first minor number that matches the driver name and + * isn't already in use. If it's in use it then it will already have a bus ID + * assigned. + * + * \sa drmOpenMinor(), drmGetVersion() and drmGetBusid(). + */ +static int drmOpenByName(const char *name) +{ + int i; + int fd; + drmVersionPtr version; + char * id; + + if (!drmAvailable()) { + if (!drm_server_info) { + return -1; + } + else { + /* try to load the kernel module now */ + if (!drm_server_info->load_module(name)) { + drmMsg("[drm] failed to load kernel module \"%s\"\n", name); + return -1; + } + } + } + + /* + * Open the first minor number that matches the driver name and isn't + * already in use. If it's in use it will have a busid assigned already. + */ + for (i = 0; i < DRM_MAX_MINOR; i++) { + if ((fd = drmOpenMinor(i, 1, DRM_NODE_RENDER)) >= 0) { + if ((version = drmGetVersion(fd))) { + if (!strcmp(version->name, name)) { + drmFreeVersion(version); + id = drmGetBusid(fd); + drmMsg("drmGetBusid returned '%s'\n", id ? id : "NULL"); + if (!id || !*id) { + if (id) + drmFreeBusid(id); + return fd; + } else { + drmFreeBusid(id); + } + } else { + drmFreeVersion(version); + } + } + close(fd); + } + } + +#ifdef __linux__ + /* Backward-compatibility /proc support */ + for (i = 0; i < 8; i++) { + char proc_name[64], buf[512]; + char *driver, *pt, *devstring; + int retcode; + + sprintf(proc_name, "/proc/dri/%d/name", i); + if ((fd = open(proc_name, 0, 0)) >= 0) { + retcode = read(fd, buf, sizeof(buf)-1); + close(fd); + if (retcode) { + buf[retcode-1] = '\0'; + for (driver = pt = buf; *pt && *pt != ' '; ++pt) + ; + if (*pt) { /* Device is next */ + *pt = '\0'; + if (!strcmp(driver, name)) { /* Match */ + for (devstring = ++pt; *pt && *pt != ' '; ++pt) + ; + if (*pt) { /* Found busid */ + return drmOpenByBusid(++pt); + } else { /* No busid */ + return drmOpenDevice(strtol(devstring, NULL, 0),i, DRM_NODE_RENDER); + } + } + } + } + } + } +#endif + + return -1; +} + + +/** + * Open the DRM device. + * + * Looks up the specified name and bus ID, and opens the device found. The + * entry in /dev/dri is created if necessary and if called by root. + * + * \param name driver name. Not referenced if bus ID is supplied. + * \param busid bus ID. Zero if not known. + * + * \return a file descriptor on success, or a negative value on error. + * + * \internal + * It calls drmOpenByBusid() if \p busid is specified or drmOpenByName() + * otherwise. + */ +int drmOpen(const char *name, const char *busid) +{ + if (!drmAvailable() && name != NULL && drm_server_info) { + /* try to load the kernel */ + if (!drm_server_info->load_module(name)) { + drmMsg("[drm] failed to load kernel module \"%s\"\n", name); + return -1; + } + } + + if (busid) { + int fd = drmOpenByBusid(busid); + if (fd >= 0) + return fd; + } + + if (name) + return drmOpenByName(name); + + return -1; +} + +int drmOpenControl(int minor) +{ + return drmOpenMinor(minor, 0, DRM_NODE_CONTROL); +} + +/** + * Free the version information returned by drmGetVersion(). + * + * \param v pointer to the version information. + * + * \internal + * It frees the memory pointed by \p %v as well as all the non-null strings + * pointers in it. + */ +void drmFreeVersion(drmVersionPtr v) +{ + if (!v) + return; + drmFree(v->name); + drmFree(v->date); + drmFree(v->desc); + drmFree(v); +} + + +/** + * Free the non-public version information returned by the kernel. + * + * \param v pointer to the version information. + * + * \internal + * Used by drmGetVersion() to free the memory pointed by \p %v as well as all + * the non-null strings pointers in it. + */ +static void drmFreeKernelVersion(drm_version_t *v) +{ + if (!v) + return; + drmFree(v->name); + drmFree(v->date); + drmFree(v->desc); + drmFree(v); +} + + +/** + * Copy version information. + * + * \param d destination pointer. + * \param s source pointer. + * + * \internal + * Used by drmGetVersion() to translate the information returned by the ioctl + * interface in a private structure into the public structure counterpart. + */ +static void drmCopyVersion(drmVersionPtr d, const drm_version_t *s) +{ + d->version_major = s->version_major; + d->version_minor = s->version_minor; + d->version_patchlevel = s->version_patchlevel; + d->name_len = s->name_len; + d->name = strdup(s->name); + d->date_len = s->date_len; + d->date = strdup(s->date); + d->desc_len = s->desc_len; + d->desc = strdup(s->desc); +} + + +/** + * Query the driver version information. + * + * \param fd file descriptor. + * + * \return pointer to a drmVersion structure which should be freed with + * drmFreeVersion(). + * + * \note Similar information is available via /proc/dri. + * + * \internal + * It gets the version information via successive DRM_IOCTL_VERSION ioctls, + * first with zeros to get the string lengths, and then the actually strings. + * It also null-terminates them since they might not be already. + */ +drmVersionPtr drmGetVersion(int fd) +{ + drmVersionPtr retval; + drm_version_t *version = drmMalloc(sizeof(*version)); + + version->name_len = 0; + version->name = NULL; + version->date_len = 0; + version->date = NULL; + version->desc_len = 0; + version->desc = NULL; + + if (drmIoctl(fd, DRM_IOCTL_VERSION, version)) { + drmFreeKernelVersion(version); + return NULL; + } + + if (version->name_len) + version->name = drmMalloc(version->name_len + 1); + if (version->date_len) + version->date = drmMalloc(version->date_len + 1); + if (version->desc_len) + version->desc = drmMalloc(version->desc_len + 1); + + if (drmIoctl(fd, DRM_IOCTL_VERSION, version)) { + drmMsg("DRM_IOCTL_VERSION: %s\n", strerror(errno)); + drmFreeKernelVersion(version); + return NULL; + } + + /* The results might not be null-terminated strings, so terminate them. */ + if (version->name_len) version->name[version->name_len] = '\0'; + if (version->date_len) version->date[version->date_len] = '\0'; + if (version->desc_len) version->desc[version->desc_len] = '\0'; + + retval = drmMalloc(sizeof(*retval)); + drmCopyVersion(retval, version); + drmFreeKernelVersion(version); + return retval; +} + + +/** + * Get version information for the DRM user space library. + * + * This version number is driver independent. + * + * \param fd file descriptor. + * + * \return version information. + * + * \internal + * This function allocates and fills a drm_version structure with a hard coded + * version number. + */ +drmVersionPtr drmGetLibVersion(int fd) +{ + drm_version_t *version = drmMalloc(sizeof(*version)); + + /* Version history: + * NOTE THIS MUST NOT GO ABOVE VERSION 1.X due to drivers needing it + * revision 1.0.x = original DRM interface with no drmGetLibVersion + * entry point and many drm extensions + * revision 1.1.x = added drmCommand entry points for device extensions + * added drmGetLibVersion to identify libdrm.a version + * revision 1.2.x = added drmSetInterfaceVersion + * modified drmOpen to handle both busid and name + * revision 1.3.x = added server + memory manager + */ + version->version_major = 1; + version->version_minor = 3; + version->version_patchlevel = 0; + + return (drmVersionPtr)version; +} + +int drmGetCap(int fd, uint64_t capability, uint64_t *value) +{ + struct drm_get_cap cap = { capability, 0 }; + int ret; + + ret = drmIoctl(fd, DRM_IOCTL_GET_CAP, &cap); + if (ret) + return ret; + + *value = cap.value; + return 0; +} + +/** + * Free the bus ID information. + * + * \param busid bus ID information string as given by drmGetBusid(). + * + * \internal + * This function is just frees the memory pointed by \p busid. + */ +void drmFreeBusid(const char *busid) +{ + drmFree((void *)busid); +} + + +/** + * Get the bus ID of the device. + * + * \param fd file descriptor. + * + * \return bus ID string. + * + * \internal + * This function gets the bus ID via successive DRM_IOCTL_GET_UNIQUE ioctls to + * get the string length and data, passing the arguments in a drm_unique + * structure. + */ +char *drmGetBusid(int fd) +{ + drm_unique_t u; + + u.unique_len = 0; + u.unique = NULL; + + if (drmIoctl(fd, DRM_IOCTL_GET_UNIQUE, &u)) + return NULL; + u.unique = drmMalloc(u.unique_len + 1); + if (drmIoctl(fd, DRM_IOCTL_GET_UNIQUE, &u)) + return NULL; + u.unique[u.unique_len] = '\0'; + + return u.unique; +} + + +/** + * Set the bus ID of the device. + * + * \param fd file descriptor. + * \param busid bus ID string. + * + * \return zero on success, negative on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_SET_UNIQUE ioctl, passing + * the arguments in a drm_unique structure. + */ +int drmSetBusid(int fd, const char *busid) +{ + drm_unique_t u; + + u.unique = (char *)busid; + u.unique_len = strlen(busid); + + if (drmIoctl(fd, DRM_IOCTL_SET_UNIQUE, &u)) { + return -errno; + } + return 0; +} + +int drmGetMagic(int fd, drm_magic_t * magic) +{ + drm_auth_t auth; + + *magic = 0; + if (drmIoctl(fd, DRM_IOCTL_GET_MAGIC, &auth)) + return -errno; + *magic = auth.magic; + return 0; +} + +int drmAuthMagic(int fd, drm_magic_t magic) +{ + drm_auth_t auth; + + auth.magic = magic; + if (drmIoctl(fd, DRM_IOCTL_AUTH_MAGIC, &auth)) + return -errno; + return 0; +} + +/** + * Specifies a range of memory that is available for mapping by a + * non-root process. + * + * \param fd file descriptor. + * \param offset usually the physical address. The actual meaning depends of + * the \p type parameter. See below. + * \param size of the memory in bytes. + * \param type type of the memory to be mapped. + * \param flags combination of several flags to modify the function actions. + * \param handle will be set to a value that may be used as the offset + * parameter for mmap(). + * + * \return zero on success or a negative value on error. + * + * \par Mapping the frame buffer + * For the frame buffer + * - \p offset will be the physical address of the start of the frame buffer, + * - \p size will be the size of the frame buffer in bytes, and + * - \p type will be DRM_FRAME_BUFFER. + * + * \par + * The area mapped will be uncached. If MTRR support is available in the + * kernel, the frame buffer area will be set to write combining. + * + * \par Mapping the MMIO register area + * For the MMIO register area, + * - \p offset will be the physical address of the start of the register area, + * - \p size will be the size of the register area bytes, and + * - \p type will be DRM_REGISTERS. + * \par + * The area mapped will be uncached. + * + * \par Mapping the SAREA + * For the SAREA, + * - \p offset will be ignored and should be set to zero, + * - \p size will be the desired size of the SAREA in bytes, + * - \p type will be DRM_SHM. + * + * \par + * A shared memory area of the requested size will be created and locked in + * kernel memory. This area may be mapped into client-space by using the handle + * returned. + * + * \note May only be called by root. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_ADD_MAP ioctl, passing + * the arguments in a drm_map structure. + */ +int drmAddMap(int fd, drm_handle_t offset, drmSize size, drmMapType type, + drmMapFlags flags, drm_handle_t *handle) +{ + drm_map_t map; + + map.offset = offset; + map.size = size; + map.handle = 0; + map.type = type; + map.flags = flags; + if (drmIoctl(fd, DRM_IOCTL_ADD_MAP, &map)) + return -errno; + if (handle) + *handle = (drm_handle_t)(uintptr_t)map.handle; + return 0; +} + +int drmRmMap(int fd, drm_handle_t handle) +{ + drm_map_t map; + + map.handle = (void *)(uintptr_t)handle; + + if(drmIoctl(fd, DRM_IOCTL_RM_MAP, &map)) + return -errno; + return 0; +} + +/** + * Make buffers available for DMA transfers. + * + * \param fd file descriptor. + * \param count number of buffers. + * \param size size of each buffer. + * \param flags buffer allocation flags. + * \param agp_offset offset in the AGP aperture + * + * \return number of buffers allocated, negative on error. + * + * \internal + * This function is a wrapper around DRM_IOCTL_ADD_BUFS ioctl. + * + * \sa drm_buf_desc. + */ +int drmAddBufs(int fd, int count, int size, drmBufDescFlags flags, + int agp_offset) +{ + drm_buf_desc_t request; + + request.count = count; + request.size = size; + request.low_mark = 0; + request.high_mark = 0; + request.flags = flags; + request.agp_start = agp_offset; + + if (drmIoctl(fd, DRM_IOCTL_ADD_BUFS, &request)) + return -errno; + return request.count; +} + +int drmMarkBufs(int fd, double low, double high) +{ + drm_buf_info_t info; + int i; + + info.count = 0; + info.list = NULL; + + if (drmIoctl(fd, DRM_IOCTL_INFO_BUFS, &info)) + return -EINVAL; + + if (!info.count) + return -EINVAL; + + if (!(info.list = drmMalloc(info.count * sizeof(*info.list)))) + return -ENOMEM; + + if (drmIoctl(fd, DRM_IOCTL_INFO_BUFS, &info)) { + int retval = -errno; + drmFree(info.list); + return retval; + } + + for (i = 0; i < info.count; i++) { + info.list[i].low_mark = low * info.list[i].count; + info.list[i].high_mark = high * info.list[i].count; + if (drmIoctl(fd, DRM_IOCTL_MARK_BUFS, &info.list[i])) { + int retval = -errno; + drmFree(info.list); + return retval; + } + } + drmFree(info.list); + + return 0; +} + +/** + * Free buffers. + * + * \param fd file descriptor. + * \param count number of buffers to free. + * \param list list of buffers to be freed. + * + * \return zero on success, or a negative value on failure. + * + * \note This function is primarily used for debugging. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_FREE_BUFS ioctl, passing + * the arguments in a drm_buf_free structure. + */ +int drmFreeBufs(int fd, int count, int *list) +{ + drm_buf_free_t request; + + request.count = count; + request.list = list; + if (drmIoctl(fd, DRM_IOCTL_FREE_BUFS, &request)) + return -errno; + return 0; +} + + +/** + * Close the device. + * + * \param fd file descriptor. + * + * \internal + * This function closes the file descriptor. + */ +int drmClose(int fd) +{ + unsigned long key = drmGetKeyFromFd(fd); + drmHashEntry *entry = drmGetEntry(fd); + + drmHashDestroy(entry->tagTable); + entry->fd = 0; + entry->f = NULL; + entry->tagTable = NULL; + + drmHashDelete(drmHashTable, key); + drmFree(entry); + + return close(fd); +} + + +/** + * Map a region of memory. + * + * \param fd file descriptor. + * \param handle handle returned by drmAddMap(). + * \param size size in bytes. Must match the size used by drmAddMap(). + * \param address will contain the user-space virtual address where the mapping + * begins. + * + * \return zero on success, or a negative value on failure. + * + * \internal + * This function is a wrapper for mmap(). + */ +int drmMap(int fd, drm_handle_t handle, drmSize size, drmAddressPtr address) +{ + static unsigned long pagesize_mask = 0; + + if (fd < 0) + return -EINVAL; + + if (!pagesize_mask) + pagesize_mask = getpagesize() - 1; + + size = (size + pagesize_mask) & ~pagesize_mask; + + *address = mmap(0, size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, handle); + if (*address == MAP_FAILED) + return -errno; + return 0; +} + + +/** + * Unmap mappings obtained with drmMap(). + * + * \param address address as given by drmMap(). + * \param size size in bytes. Must match the size used by drmMap(). + * + * \return zero on success, or a negative value on failure. + * + * \internal + * This function is a wrapper for munmap(). + */ +int drmUnmap(drmAddress address, drmSize size) +{ + return munmap(address, size); +} + +drmBufInfoPtr drmGetBufInfo(int fd) +{ + drm_buf_info_t info; + drmBufInfoPtr retval; + int i; + + info.count = 0; + info.list = NULL; + + if (drmIoctl(fd, DRM_IOCTL_INFO_BUFS, &info)) + return NULL; + + if (info.count) { + if (!(info.list = drmMalloc(info.count * sizeof(*info.list)))) + return NULL; + + if (drmIoctl(fd, DRM_IOCTL_INFO_BUFS, &info)) { + drmFree(info.list); + return NULL; + } + + retval = drmMalloc(sizeof(*retval)); + retval->count = info.count; + retval->list = drmMalloc(info.count * sizeof(*retval->list)); + for (i = 0; i < info.count; i++) { + retval->list[i].count = info.list[i].count; + retval->list[i].size = info.list[i].size; + retval->list[i].low_mark = info.list[i].low_mark; + retval->list[i].high_mark = info.list[i].high_mark; + } + drmFree(info.list); + return retval; + } + return NULL; +} + +/** + * Map all DMA buffers into client-virtual space. + * + * \param fd file descriptor. + * + * \return a pointer to a ::drmBufMap structure. + * + * \note The client may not use these buffers until obtaining buffer indices + * with drmDMA(). + * + * \internal + * This function calls the DRM_IOCTL_MAP_BUFS ioctl and copies the returned + * information about the buffers in a drm_buf_map structure into the + * client-visible data structures. + */ +drmBufMapPtr drmMapBufs(int fd) +{ + drm_buf_map_t bufs; + drmBufMapPtr retval; + int i; + + bufs.count = 0; + bufs.list = NULL; + bufs.virtual = NULL; + if (drmIoctl(fd, DRM_IOCTL_MAP_BUFS, &bufs)) + return NULL; + + if (!bufs.count) + return NULL; + + if (!(bufs.list = drmMalloc(bufs.count * sizeof(*bufs.list)))) + return NULL; + + if (drmIoctl(fd, DRM_IOCTL_MAP_BUFS, &bufs)) { + drmFree(bufs.list); + return NULL; + } + + retval = drmMalloc(sizeof(*retval)); + retval->count = bufs.count; + retval->list = drmMalloc(bufs.count * sizeof(*retval->list)); + for (i = 0; i < bufs.count; i++) { + retval->list[i].idx = bufs.list[i].idx; + retval->list[i].total = bufs.list[i].total; + retval->list[i].used = 0; + retval->list[i].address = bufs.list[i].address; + } + + drmFree(bufs.list); + + return retval; +} + + +/** + * Unmap buffers allocated with drmMapBufs(). + * + * \return zero on success, or negative value on failure. + * + * \internal + * Calls munmap() for every buffer stored in \p bufs and frees the + * memory allocated by drmMapBufs(). + */ +int drmUnmapBufs(drmBufMapPtr bufs) +{ + int i; + + for (i = 0; i < bufs->count; i++) { + munmap(bufs->list[i].address, bufs->list[i].total); + } + + drmFree(bufs->list); + drmFree(bufs); + + return 0; +} + + +#define DRM_DMA_RETRY 16 + +/** + * Reserve DMA buffers. + * + * \param fd file descriptor. + * \param request + * + * \return zero on success, or a negative value on failure. + * + * \internal + * Assemble the arguments into a drm_dma structure and keeps issuing the + * DRM_IOCTL_DMA ioctl until success or until maximum number of retries. + */ +int drmDMA(int fd, drmDMAReqPtr request) +{ + drm_dma_t dma; + int ret, i = 0; + + dma.context = request->context; + dma.send_count = request->send_count; + dma.send_indices = request->send_list; + dma.send_sizes = request->send_sizes; + dma.flags = request->flags; + dma.request_count = request->request_count; + dma.request_size = request->request_size; + dma.request_indices = request->request_list; + dma.request_sizes = request->request_sizes; + dma.granted_count = 0; + + do { + ret = ioctl( fd, DRM_IOCTL_DMA, &dma ); + } while ( ret && errno == EAGAIN && i++ < DRM_DMA_RETRY ); + + if ( ret == 0 ) { + request->granted_count = dma.granted_count; + return 0; + } else { + return -errno; + } +} + + +/** + * Obtain heavyweight hardware lock. + * + * \param fd file descriptor. + * \param context context. + * \param flags flags that determine the sate of the hardware when the function + * returns. + * + * \return always zero. + * + * \internal + * This function translates the arguments into a drm_lock structure and issue + * the DRM_IOCTL_LOCK ioctl until the lock is successfully acquired. + */ +int drmGetLock(int fd, drm_context_t context, drmLockFlags flags) +{ + drm_lock_t lock; + + lock.context = context; + lock.flags = 0; + if (flags & DRM_LOCK_READY) lock.flags |= _DRM_LOCK_READY; + if (flags & DRM_LOCK_QUIESCENT) lock.flags |= _DRM_LOCK_QUIESCENT; + if (flags & DRM_LOCK_FLUSH) lock.flags |= _DRM_LOCK_FLUSH; + if (flags & DRM_LOCK_FLUSH_ALL) lock.flags |= _DRM_LOCK_FLUSH_ALL; + if (flags & DRM_HALT_ALL_QUEUES) lock.flags |= _DRM_HALT_ALL_QUEUES; + if (flags & DRM_HALT_CUR_QUEUES) lock.flags |= _DRM_HALT_CUR_QUEUES; + + while (drmIoctl(fd, DRM_IOCTL_LOCK, &lock)) + ; + return 0; +} + +/** + * Release the hardware lock. + * + * \param fd file descriptor. + * \param context context. + * + * \return zero on success, or a negative value on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_UNLOCK ioctl, passing the + * argument in a drm_lock structure. + */ +int drmUnlock(int fd, drm_context_t context) +{ + drm_lock_t lock; + + lock.context = context; + lock.flags = 0; + return drmIoctl(fd, DRM_IOCTL_UNLOCK, &lock); +} + +drm_context_t *drmGetReservedContextList(int fd, int *count) +{ + drm_ctx_res_t res; + drm_ctx_t *list; + drm_context_t * retval; + int i; + + res.count = 0; + res.contexts = NULL; + if (drmIoctl(fd, DRM_IOCTL_RES_CTX, &res)) + return NULL; + + if (!res.count) + return NULL; + + if (!(list = drmMalloc(res.count * sizeof(*list)))) + return NULL; + if (!(retval = drmMalloc(res.count * sizeof(*retval)))) { + drmFree(list); + return NULL; + } + + res.contexts = list; + if (drmIoctl(fd, DRM_IOCTL_RES_CTX, &res)) + return NULL; + + for (i = 0; i < res.count; i++) + retval[i] = list[i].handle; + drmFree(list); + + *count = res.count; + return retval; +} + +void drmFreeReservedContextList(drm_context_t *pt) +{ + drmFree(pt); +} + +/** + * Create context. + * + * Used by the X server during GLXContext initialization. This causes + * per-context kernel-level resources to be allocated. + * + * \param fd file descriptor. + * \param handle is set on success. To be used by the client when requesting DMA + * dispatch with drmDMA(). + * + * \return zero on success, or a negative value on failure. + * + * \note May only be called by root. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_ADD_CTX ioctl, passing the + * argument in a drm_ctx structure. + */ +int drmCreateContext(int fd, drm_context_t *handle) +{ + drm_ctx_t ctx; + + ctx.flags = 0; /* Modified with functions below */ + if (drmIoctl(fd, DRM_IOCTL_ADD_CTX, &ctx)) + return -errno; + *handle = ctx.handle; + return 0; +} + +int drmSwitchToContext(int fd, drm_context_t context) +{ + drm_ctx_t ctx; + + ctx.handle = context; + if (drmIoctl(fd, DRM_IOCTL_SWITCH_CTX, &ctx)) + return -errno; + return 0; +} + +int drmSetContextFlags(int fd, drm_context_t context, drm_context_tFlags flags) +{ + drm_ctx_t ctx; + + /* + * Context preserving means that no context switches are done between DMA + * buffers from one context and the next. This is suitable for use in the + * X server (which promises to maintain hardware context), or in the + * client-side library when buffers are swapped on behalf of two threads. + */ + ctx.handle = context; + ctx.flags = 0; + if (flags & DRM_CONTEXT_PRESERVED) + ctx.flags |= _DRM_CONTEXT_PRESERVED; + if (flags & DRM_CONTEXT_2DONLY) + ctx.flags |= _DRM_CONTEXT_2DONLY; + if (drmIoctl(fd, DRM_IOCTL_MOD_CTX, &ctx)) + return -errno; + return 0; +} + +int drmGetContextFlags(int fd, drm_context_t context, + drm_context_tFlagsPtr flags) +{ + drm_ctx_t ctx; + + ctx.handle = context; + if (drmIoctl(fd, DRM_IOCTL_GET_CTX, &ctx)) + return -errno; + *flags = 0; + if (ctx.flags & _DRM_CONTEXT_PRESERVED) + *flags |= DRM_CONTEXT_PRESERVED; + if (ctx.flags & _DRM_CONTEXT_2DONLY) + *flags |= DRM_CONTEXT_2DONLY; + return 0; +} + +/** + * Destroy context. + * + * Free any kernel-level resources allocated with drmCreateContext() associated + * with the context. + * + * \param fd file descriptor. + * \param handle handle given by drmCreateContext(). + * + * \return zero on success, or a negative value on failure. + * + * \note May only be called by root. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_RM_CTX ioctl, passing the + * argument in a drm_ctx structure. + */ +int drmDestroyContext(int fd, drm_context_t handle) +{ + drm_ctx_t ctx; + ctx.handle = handle; + if (drmIoctl(fd, DRM_IOCTL_RM_CTX, &ctx)) + return -errno; + return 0; +} + +int drmCreateDrawable(int fd, drm_drawable_t *handle) +{ + drm_draw_t draw; + if (drmIoctl(fd, DRM_IOCTL_ADD_DRAW, &draw)) + return -errno; + *handle = draw.handle; + return 0; +} + +int drmDestroyDrawable(int fd, drm_drawable_t handle) +{ + drm_draw_t draw; + draw.handle = handle; + if (drmIoctl(fd, DRM_IOCTL_RM_DRAW, &draw)) + return -errno; + return 0; +} + +int drmUpdateDrawableInfo(int fd, drm_drawable_t handle, + drm_drawable_info_type_t type, unsigned int num, + void *data) +{ + drm_update_draw_t update; + + update.handle = handle; + update.type = type; + update.num = num; + update.data = (unsigned long long)(unsigned long)data; + + if (drmIoctl(fd, DRM_IOCTL_UPDATE_DRAW, &update)) + return -errno; + + return 0; +} + +/** + * Acquire the AGP device. + * + * Must be called before any of the other AGP related calls. + * + * \param fd file descriptor. + * + * \return zero on success, or a negative value on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_ACQUIRE ioctl. + */ +int drmAgpAcquire(int fd) +{ + if (drmIoctl(fd, DRM_IOCTL_AGP_ACQUIRE, NULL)) + return -errno; + return 0; +} + + +/** + * Release the AGP device. + * + * \param fd file descriptor. + * + * \return zero on success, or a negative value on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_RELEASE ioctl. + */ +int drmAgpRelease(int fd) +{ + if (drmIoctl(fd, DRM_IOCTL_AGP_RELEASE, NULL)) + return -errno; + return 0; +} + + +/** + * Set the AGP mode. + * + * \param fd file descriptor. + * \param mode AGP mode. + * + * \return zero on success, or a negative value on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_ENABLE ioctl, passing the + * argument in a drm_agp_mode structure. + */ +int drmAgpEnable(int fd, unsigned long mode) +{ + drm_agp_mode_t m; + + m.mode = mode; + if (drmIoctl(fd, DRM_IOCTL_AGP_ENABLE, &m)) + return -errno; + return 0; +} + + +/** + * Allocate a chunk of AGP memory. + * + * \param fd file descriptor. + * \param size requested memory size in bytes. Will be rounded to page boundary. + * \param type type of memory to allocate. + * \param address if not zero, will be set to the physical address of the + * allocated memory. + * \param handle on success will be set to a handle of the allocated memory. + * + * \return zero on success, or a negative value on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_ALLOC ioctl, passing the + * arguments in a drm_agp_buffer structure. + */ +int drmAgpAlloc(int fd, unsigned long size, unsigned long type, + unsigned long *address, drm_handle_t *handle) +{ + drm_agp_buffer_t b; + + *handle = DRM_AGP_NO_HANDLE; + b.size = size; + b.handle = 0; + b.type = type; + if (drmIoctl(fd, DRM_IOCTL_AGP_ALLOC, &b)) + return -errno; + if (address != 0UL) + *address = b.physical; + *handle = b.handle; + return 0; +} + + +/** + * Free a chunk of AGP memory. + * + * \param fd file descriptor. + * \param handle handle to the allocated memory, as given by drmAgpAllocate(). + * + * \return zero on success, or a negative value on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_FREE ioctl, passing the + * argument in a drm_agp_buffer structure. + */ +int drmAgpFree(int fd, drm_handle_t handle) +{ + drm_agp_buffer_t b; + + b.size = 0; + b.handle = handle; + if (drmIoctl(fd, DRM_IOCTL_AGP_FREE, &b)) + return -errno; + return 0; +} + + +/** + * Bind a chunk of AGP memory. + * + * \param fd file descriptor. + * \param handle handle to the allocated memory, as given by drmAgpAllocate(). + * \param offset offset in bytes. It will round to page boundary. + * + * \return zero on success, or a negative value on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_BIND ioctl, passing the + * argument in a drm_agp_binding structure. + */ +int drmAgpBind(int fd, drm_handle_t handle, unsigned long offset) +{ + drm_agp_binding_t b; + + b.handle = handle; + b.offset = offset; + if (drmIoctl(fd, DRM_IOCTL_AGP_BIND, &b)) + return -errno; + return 0; +} + + +/** + * Unbind a chunk of AGP memory. + * + * \param fd file descriptor. + * \param handle handle to the allocated memory, as given by drmAgpAllocate(). + * + * \return zero on success, or a negative value on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_UNBIND ioctl, passing + * the argument in a drm_agp_binding structure. + */ +int drmAgpUnbind(int fd, drm_handle_t handle) +{ + drm_agp_binding_t b; + + b.handle = handle; + b.offset = 0; + if (drmIoctl(fd, DRM_IOCTL_AGP_UNBIND, &b)) + return -errno; + return 0; +} + + +/** + * Get AGP driver major version number. + * + * \param fd file descriptor. + * + * \return major version number on success, or a negative value on failure.. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the + * necessary information in a drm_agp_info structure. + */ +int drmAgpVersionMajor(int fd) +{ + drm_agp_info_t i; + + if (drmIoctl(fd, DRM_IOCTL_AGP_INFO, &i)) + return -errno; + return i.agp_version_major; +} + + +/** + * Get AGP driver minor version number. + * + * \param fd file descriptor. + * + * \return minor version number on success, or a negative value on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the + * necessary information in a drm_agp_info structure. + */ +int drmAgpVersionMinor(int fd) +{ + drm_agp_info_t i; + + if (drmIoctl(fd, DRM_IOCTL_AGP_INFO, &i)) + return -errno; + return i.agp_version_minor; +} + + +/** + * Get AGP mode. + * + * \param fd file descriptor. + * + * \return mode on success, or zero on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the + * necessary information in a drm_agp_info structure. + */ +unsigned long drmAgpGetMode(int fd) +{ + drm_agp_info_t i; + + if (drmIoctl(fd, DRM_IOCTL_AGP_INFO, &i)) + return 0; + return i.mode; +} + + +/** + * Get AGP aperture base. + * + * \param fd file descriptor. + * + * \return aperture base on success, zero on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the + * necessary information in a drm_agp_info structure. + */ +unsigned long drmAgpBase(int fd) +{ + drm_agp_info_t i; + + if (drmIoctl(fd, DRM_IOCTL_AGP_INFO, &i)) + return 0; + return i.aperture_base; +} + + +/** + * Get AGP aperture size. + * + * \param fd file descriptor. + * + * \return aperture size on success, zero on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the + * necessary information in a drm_agp_info structure. + */ +unsigned long drmAgpSize(int fd) +{ + drm_agp_info_t i; + + if (drmIoctl(fd, DRM_IOCTL_AGP_INFO, &i)) + return 0; + return i.aperture_size; +} + + +/** + * Get used AGP memory. + * + * \param fd file descriptor. + * + * \return memory used on success, or zero on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the + * necessary information in a drm_agp_info structure. + */ +unsigned long drmAgpMemoryUsed(int fd) +{ + drm_agp_info_t i; + + if (drmIoctl(fd, DRM_IOCTL_AGP_INFO, &i)) + return 0; + return i.memory_used; +} + + +/** + * Get available AGP memory. + * + * \param fd file descriptor. + * + * \return memory available on success, or zero on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the + * necessary information in a drm_agp_info structure. + */ +unsigned long drmAgpMemoryAvail(int fd) +{ + drm_agp_info_t i; + + if (drmIoctl(fd, DRM_IOCTL_AGP_INFO, &i)) + return 0; + return i.memory_allowed; +} + + +/** + * Get hardware vendor ID. + * + * \param fd file descriptor. + * + * \return vendor ID on success, or zero on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the + * necessary information in a drm_agp_info structure. + */ +unsigned int drmAgpVendorId(int fd) +{ + drm_agp_info_t i; + + if (drmIoctl(fd, DRM_IOCTL_AGP_INFO, &i)) + return 0; + return i.id_vendor; +} + + +/** + * Get hardware device ID. + * + * \param fd file descriptor. + * + * \return zero on success, or zero on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_AGP_INFO ioctl, getting the + * necessary information in a drm_agp_info structure. + */ +unsigned int drmAgpDeviceId(int fd) +{ + drm_agp_info_t i; + + if (drmIoctl(fd, DRM_IOCTL_AGP_INFO, &i)) + return 0; + return i.id_device; +} + +int drmScatterGatherAlloc(int fd, unsigned long size, drm_handle_t *handle) +{ + drm_scatter_gather_t sg; + + *handle = 0; + sg.size = size; + sg.handle = 0; + if (drmIoctl(fd, DRM_IOCTL_SG_ALLOC, &sg)) + return -errno; + *handle = sg.handle; + return 0; +} + +int drmScatterGatherFree(int fd, drm_handle_t handle) +{ + drm_scatter_gather_t sg; + + sg.size = 0; + sg.handle = handle; + if (drmIoctl(fd, DRM_IOCTL_SG_FREE, &sg)) + return -errno; + return 0; +} + +/** + * Wait for VBLANK. + * + * \param fd file descriptor. + * \param vbl pointer to a drmVBlank structure. + * + * \return zero on success, or a negative value on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_WAIT_VBLANK ioctl. + */ +int drmWaitVBlank(int fd, drmVBlankPtr vbl) +{ + struct timespec timeout, cur; + int ret; + + ret = clock_gettime(CLOCK_MONOTONIC, &timeout); + if (ret < 0) { + fprintf(stderr, "clock_gettime failed: %s\n", strerror(ret)); + goto out; + } + timeout.tv_sec++; + + do { + ret = ioctl(fd, DRM_IOCTL_WAIT_VBLANK, vbl); + vbl->request.type &= ~DRM_VBLANK_RELATIVE; + if (ret && errno == EINTR) { + clock_gettime(CLOCK_MONOTONIC, &cur); + /* Timeout after 1s */ + if (cur.tv_sec > timeout.tv_sec + 1 || + (cur.tv_sec == timeout.tv_sec && cur.tv_nsec >= + timeout.tv_nsec)) { + errno = EBUSY; + ret = -1; + break; + } + } + } while (ret && errno == EINTR); + +out: + return ret; +} + +int drmError(int err, const char *label) +{ + switch (err) { + case DRM_ERR_NO_DEVICE: + fprintf(stderr, "%s: no device\n", label); + break; + case DRM_ERR_NO_ACCESS: + fprintf(stderr, "%s: no access\n", label); + break; + case DRM_ERR_NOT_ROOT: + fprintf(stderr, "%s: not root\n", label); + break; + case DRM_ERR_INVALID: + fprintf(stderr, "%s: invalid args\n", label); + break; + default: + if (err < 0) + err = -err; + fprintf( stderr, "%s: error %d (%s)\n", label, err, strerror(err) ); + break; + } + + return 1; +} + +/** + * Install IRQ handler. + * + * \param fd file descriptor. + * \param irq IRQ number. + * + * \return zero on success, or a negative value on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_CONTROL ioctl, passing the + * argument in a drm_control structure. + */ +int drmCtlInstHandler(int fd, int irq) +{ + drm_control_t ctl; + + ctl.func = DRM_INST_HANDLER; + ctl.irq = irq; + if (drmIoctl(fd, DRM_IOCTL_CONTROL, &ctl)) + return -errno; + return 0; +} + + +/** + * Uninstall IRQ handler. + * + * \param fd file descriptor. + * + * \return zero on success, or a negative value on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_CONTROL ioctl, passing the + * argument in a drm_control structure. + */ +int drmCtlUninstHandler(int fd) +{ + drm_control_t ctl; + + ctl.func = DRM_UNINST_HANDLER; + ctl.irq = 0; + if (drmIoctl(fd, DRM_IOCTL_CONTROL, &ctl)) + return -errno; + return 0; +} + +int drmFinish(int fd, int context, drmLockFlags flags) +{ + drm_lock_t lock; + + lock.context = context; + lock.flags = 0; + if (flags & DRM_LOCK_READY) lock.flags |= _DRM_LOCK_READY; + if (flags & DRM_LOCK_QUIESCENT) lock.flags |= _DRM_LOCK_QUIESCENT; + if (flags & DRM_LOCK_FLUSH) lock.flags |= _DRM_LOCK_FLUSH; + if (flags & DRM_LOCK_FLUSH_ALL) lock.flags |= _DRM_LOCK_FLUSH_ALL; + if (flags & DRM_HALT_ALL_QUEUES) lock.flags |= _DRM_HALT_ALL_QUEUES; + if (flags & DRM_HALT_CUR_QUEUES) lock.flags |= _DRM_HALT_CUR_QUEUES; + if (drmIoctl(fd, DRM_IOCTL_FINISH, &lock)) + return -errno; + return 0; +} + +/** + * Get IRQ from bus ID. + * + * \param fd file descriptor. + * \param busnum bus number. + * \param devnum device number. + * \param funcnum function number. + * + * \return IRQ number on success, or a negative value on failure. + * + * \internal + * This function is a wrapper around the DRM_IOCTL_IRQ_BUSID ioctl, passing the + * arguments in a drm_irq_busid structure. + */ +int drmGetInterruptFromBusID(int fd, int busnum, int devnum, int funcnum) +{ + drm_irq_busid_t p; + + p.busnum = busnum; + p.devnum = devnum; + p.funcnum = funcnum; + if (drmIoctl(fd, DRM_IOCTL_IRQ_BUSID, &p)) + return -errno; + return p.irq; +} + +int drmAddContextTag(int fd, drm_context_t context, void *tag) +{ + drmHashEntry *entry = drmGetEntry(fd); + + if (drmHashInsert(entry->tagTable, context, tag)) { + drmHashDelete(entry->tagTable, context); + drmHashInsert(entry->tagTable, context, tag); + } + return 0; +} + +int drmDelContextTag(int fd, drm_context_t context) +{ + drmHashEntry *entry = drmGetEntry(fd); + + return drmHashDelete(entry->tagTable, context); +} + +void *drmGetContextTag(int fd, drm_context_t context) +{ + drmHashEntry *entry = drmGetEntry(fd); + void *value; + + if (drmHashLookup(entry->tagTable, context, &value)) + return NULL; + + return value; +} + +int drmAddContextPrivateMapping(int fd, drm_context_t ctx_id, + drm_handle_t handle) +{ + drm_ctx_priv_map_t map; + + map.ctx_id = ctx_id; + map.handle = (void *)(uintptr_t)handle; + + if (drmIoctl(fd, DRM_IOCTL_SET_SAREA_CTX, &map)) + return -errno; + return 0; +} + +int drmGetContextPrivateMapping(int fd, drm_context_t ctx_id, + drm_handle_t *handle) +{ + drm_ctx_priv_map_t map; + + map.ctx_id = ctx_id; + + if (drmIoctl(fd, DRM_IOCTL_GET_SAREA_CTX, &map)) + return -errno; + if (handle) + *handle = (drm_handle_t)(uintptr_t)map.handle; + + return 0; +} + +int drmGetMap(int fd, int idx, drm_handle_t *offset, drmSize *size, + drmMapType *type, drmMapFlags *flags, drm_handle_t *handle, + int *mtrr) +{ + drm_map_t map; + + map.offset = idx; + if (drmIoctl(fd, DRM_IOCTL_GET_MAP, &map)) + return -errno; + *offset = map.offset; + *size = map.size; + *type = map.type; + *flags = map.flags; + *handle = (unsigned long)map.handle; + *mtrr = map.mtrr; + return 0; +} + +int drmGetClient(int fd, int idx, int *auth, int *pid, int *uid, + unsigned long *magic, unsigned long *iocs) +{ + drm_client_t client; + + client.idx = idx; + if (drmIoctl(fd, DRM_IOCTL_GET_CLIENT, &client)) + return -errno; + *auth = client.auth; + *pid = client.pid; + *uid = client.uid; + *magic = client.magic; + *iocs = client.iocs; + return 0; +} + +int drmGetStats(int fd, drmStatsT *stats) +{ + drm_stats_t s; + int i; + + if (drmIoctl(fd, DRM_IOCTL_GET_STATS, &s)) + return -errno; + + stats->count = 0; + memset(stats, 0, sizeof(*stats)); + if (s.count > sizeof(stats->data)/sizeof(stats->data[0])) + return -1; + +#define SET_VALUE \ + stats->data[i].long_format = "%-20.20s"; \ + stats->data[i].rate_format = "%8.8s"; \ + stats->data[i].isvalue = 1; \ + stats->data[i].verbose = 0 + +#define SET_COUNT \ + stats->data[i].long_format = "%-20.20s"; \ + stats->data[i].rate_format = "%5.5s"; \ + stats->data[i].isvalue = 0; \ + stats->data[i].mult_names = "kgm"; \ + stats->data[i].mult = 1000; \ + stats->data[i].verbose = 0 + +#define SET_BYTE \ + stats->data[i].long_format = "%-20.20s"; \ + stats->data[i].rate_format = "%5.5s"; \ + stats->data[i].isvalue = 0; \ + stats->data[i].mult_names = "KGM"; \ + stats->data[i].mult = 1024; \ + stats->data[i].verbose = 0 + + + stats->count = s.count; + for (i = 0; i < s.count; i++) { + stats->data[i].value = s.data[i].value; + switch (s.data[i].type) { + case _DRM_STAT_LOCK: + stats->data[i].long_name = "Lock"; + stats->data[i].rate_name = "Lock"; + SET_VALUE; + break; + case _DRM_STAT_OPENS: + stats->data[i].long_name = "Opens"; + stats->data[i].rate_name = "O"; + SET_COUNT; + stats->data[i].verbose = 1; + break; + case _DRM_STAT_CLOSES: + stats->data[i].long_name = "Closes"; + stats->data[i].rate_name = "Lock"; + SET_COUNT; + stats->data[i].verbose = 1; + break; + case _DRM_STAT_IOCTLS: + stats->data[i].long_name = "Ioctls"; + stats->data[i].rate_name = "Ioc/s"; + SET_COUNT; + break; + case _DRM_STAT_LOCKS: + stats->data[i].long_name = "Locks"; + stats->data[i].rate_name = "Lck/s"; + SET_COUNT; + break; + case _DRM_STAT_UNLOCKS: + stats->data[i].long_name = "Unlocks"; + stats->data[i].rate_name = "Unl/s"; + SET_COUNT; + break; + case _DRM_STAT_IRQ: + stats->data[i].long_name = "IRQs"; + stats->data[i].rate_name = "IRQ/s"; + SET_COUNT; + break; + case _DRM_STAT_PRIMARY: + stats->data[i].long_name = "Primary Bytes"; + stats->data[i].rate_name = "PB/s"; + SET_BYTE; + break; + case _DRM_STAT_SECONDARY: + stats->data[i].long_name = "Secondary Bytes"; + stats->data[i].rate_name = "SB/s"; + SET_BYTE; + break; + case _DRM_STAT_DMA: + stats->data[i].long_name = "DMA"; + stats->data[i].rate_name = "DMA/s"; + SET_COUNT; + break; + case _DRM_STAT_SPECIAL: + stats->data[i].long_name = "Special DMA"; + stats->data[i].rate_name = "dma/s"; + SET_COUNT; + break; + case _DRM_STAT_MISSED: + stats->data[i].long_name = "Miss"; + stats->data[i].rate_name = "Ms/s"; + SET_COUNT; + break; + case _DRM_STAT_VALUE: + stats->data[i].long_name = "Value"; + stats->data[i].rate_name = "Value"; + SET_VALUE; + break; + case _DRM_STAT_BYTE: + stats->data[i].long_name = "Bytes"; + stats->data[i].rate_name = "B/s"; + SET_BYTE; + break; + case _DRM_STAT_COUNT: + default: + stats->data[i].long_name = "Count"; + stats->data[i].rate_name = "Cnt/s"; + SET_COUNT; + break; + } + } + return 0; +} + +/** + * Issue a set-version ioctl. + * + * \param fd file descriptor. + * \param drmCommandIndex command index + * \param data source pointer of the data to be read and written. + * \param size size of the data to be read and written. + * + * \return zero on success, or a negative value on failure. + * + * \internal + * It issues a read-write ioctl given by + * \code DRM_COMMAND_BASE + drmCommandIndex \endcode. + */ +int drmSetInterfaceVersion(int fd, drmSetVersion *version) +{ + int retcode = 0; + drm_set_version_t sv; + + sv.drm_di_major = version->drm_di_major; + sv.drm_di_minor = version->drm_di_minor; + sv.drm_dd_major = version->drm_dd_major; + sv.drm_dd_minor = version->drm_dd_minor; + + if (drmIoctl(fd, DRM_IOCTL_SET_VERSION, &sv)) { + retcode = -errno; + } + + version->drm_di_major = sv.drm_di_major; + version->drm_di_minor = sv.drm_di_minor; + version->drm_dd_major = sv.drm_dd_major; + version->drm_dd_minor = sv.drm_dd_minor; + + return retcode; +} + +/** + * Send a device-specific command. + * + * \param fd file descriptor. + * \param drmCommandIndex command index + * + * \return zero on success, or a negative value on failure. + * + * \internal + * It issues a ioctl given by + * \code DRM_COMMAND_BASE + drmCommandIndex \endcode. + */ +int drmCommandNone(int fd, unsigned long drmCommandIndex) +{ + void *data = NULL; /* dummy */ + unsigned long request; + + request = DRM_IO( DRM_COMMAND_BASE + drmCommandIndex); + + if (drmIoctl(fd, request, data)) { + return -errno; + } + return 0; +} + + +/** + * Send a device-specific read command. + * + * \param fd file descriptor. + * \param drmCommandIndex command index + * \param data destination pointer of the data to be read. + * \param size size of the data to be read. + * + * \return zero on success, or a negative value on failure. + * + * \internal + * It issues a read ioctl given by + * \code DRM_COMMAND_BASE + drmCommandIndex \endcode. + */ +int drmCommandRead(int fd, unsigned long drmCommandIndex, void *data, + unsigned long size) +{ + unsigned long request; + + request = DRM_IOC( DRM_IOC_READ, DRM_IOCTL_BASE, + DRM_COMMAND_BASE + drmCommandIndex, size); + + if (drmIoctl(fd, request, data)) { + return -errno; + } + return 0; +} + + +/** + * Send a device-specific write command. + * + * \param fd file descriptor. + * \param drmCommandIndex command index + * \param data source pointer of the data to be written. + * \param size size of the data to be written. + * + * \return zero on success, or a negative value on failure. + * + * \internal + * It issues a write ioctl given by + * \code DRM_COMMAND_BASE + drmCommandIndex \endcode. + */ +int drmCommandWrite(int fd, unsigned long drmCommandIndex, void *data, + unsigned long size) +{ + unsigned long request; + + request = DRM_IOC( DRM_IOC_WRITE, DRM_IOCTL_BASE, + DRM_COMMAND_BASE + drmCommandIndex, size); + + if (drmIoctl(fd, request, data)) { + return -errno; + } + return 0; +} + + +/** + * Send a device-specific read-write command. + * + * \param fd file descriptor. + * \param drmCommandIndex command index + * \param data source pointer of the data to be read and written. + * \param size size of the data to be read and written. + * + * \return zero on success, or a negative value on failure. + * + * \internal + * It issues a read-write ioctl given by + * \code DRM_COMMAND_BASE + drmCommandIndex \endcode. + */ +int drmCommandWriteRead(int fd, unsigned long drmCommandIndex, void *data, + unsigned long size) +{ + unsigned long request; + + request = DRM_IOC( DRM_IOC_READ|DRM_IOC_WRITE, DRM_IOCTL_BASE, + DRM_COMMAND_BASE + drmCommandIndex, size); + + if (drmIoctl(fd, request, data)) + return -errno; + return 0; +} + +#define DRM_MAX_FDS 16 +static struct { + char *BusID; + int fd; + int refcount; +} connection[DRM_MAX_FDS]; + +static int nr_fds = 0; + +int drmOpenOnce(void *unused, + const char *BusID, + int *newlyopened) +{ + int i; + int fd; + + for (i = 0; i < nr_fds; i++) + if (strcmp(BusID, connection[i].BusID) == 0) { + connection[i].refcount++; + *newlyopened = 0; + return connection[i].fd; + } + + fd = drmOpen(unused, BusID); + if (fd <= 0 || nr_fds == DRM_MAX_FDS) + return fd; + + connection[nr_fds].BusID = strdup(BusID); + connection[nr_fds].fd = fd; + connection[nr_fds].refcount = 1; + *newlyopened = 1; + + if (0) + fprintf(stderr, "saved connection %d for %s %d\n", + nr_fds, connection[nr_fds].BusID, + strcmp(BusID, connection[nr_fds].BusID)); + + nr_fds++; + + return fd; +} + +void drmCloseOnce(int fd) +{ + int i; + + for (i = 0; i < nr_fds; i++) { + if (fd == connection[i].fd) { + if (--connection[i].refcount == 0) { + drmClose(connection[i].fd); + free(connection[i].BusID); + + if (i < --nr_fds) + connection[i] = connection[nr_fds]; + + return; + } + } + } +} + +int drmSetMaster(int fd) +{ + return ioctl(fd, DRM_IOCTL_SET_MASTER, 0); +} + +int drmDropMaster(int fd) +{ + return ioctl(fd, DRM_IOCTL_DROP_MASTER, 0); +} + +char *drmGetDeviceNameFromFd(int fd) +{ + char name[128]; + struct stat sbuf; + dev_t d; + int i; + + /* The whole drmOpen thing is a fiasco and we need to find a way + * back to just using open(2). For now, however, lets just make + * things worse with even more ad hoc directory walking code to + * discover the device file name. */ + + fstat(fd, &sbuf); + d = sbuf.st_rdev; + + for (i = 0; i < DRM_MAX_MINOR; i++) { + snprintf(name, sizeof name, DRM_DEV_NAME, DRM_DIR_NAME, i); + if (stat(name, &sbuf) == 0 && sbuf.st_rdev == d) + break; + } + if (i == DRM_MAX_MINOR) + return NULL; + + return strdup(name); +} diff --git a/xf86drm.h b/xf86drm.h new file mode 100644 index 0000000..76eb94e --- /dev/null +++ b/xf86drm.h @@ -0,0 +1,734 @@ +/** + * \file xf86drm.h + * OS-independent header for DRM user-level library interface. + * + * \author Rickard E. (Rik) Faith + */ + +/* + * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _XF86DRM_H_ +#define _XF86DRM_H_ + +#include +#include +#include +#include + +#if defined(__cplusplus) || defined(c_plusplus) +extern "C" { +#endif + +#ifndef DRM_MAX_MINOR +#define DRM_MAX_MINOR 16 +#endif + +#if defined(__linux__) + +#define DRM_IOCTL_NR(n) _IOC_NR(n) +#define DRM_IOC_VOID _IOC_NONE +#define DRM_IOC_READ _IOC_READ +#define DRM_IOC_WRITE _IOC_WRITE +#define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE +#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) + +#else /* One of the *BSDs */ + +#include +#define DRM_IOCTL_NR(n) ((n) & 0xff) +#define DRM_IOC_VOID IOC_VOID +#define DRM_IOC_READ IOC_OUT +#define DRM_IOC_WRITE IOC_IN +#define DRM_IOC_READWRITE IOC_INOUT +#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) + +#endif + + /* Defaults, if nothing set in xf86config */ +#define DRM_DEV_UID 0 +#define DRM_DEV_GID 0 +/* Default /dev/dri directory permissions 0755 */ +#define DRM_DEV_DIRMODE \ + (S_IRUSR|S_IWUSR|S_IXUSR|S_IRGRP|S_IXGRP|S_IROTH|S_IXOTH) +#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) + +#define DRM_DIR_NAME "/dev/dri" +#define DRM_DEV_NAME "%s/card%d" +#define DRM_CONTROL_DEV_NAME "%s/controlD%d" +#define DRM_PROC_NAME "/proc/dri/" /* For backward Linux compatibility */ + +#define DRM_ERR_NO_DEVICE (-1001) +#define DRM_ERR_NO_ACCESS (-1002) +#define DRM_ERR_NOT_ROOT (-1003) +#define DRM_ERR_INVALID (-1004) +#define DRM_ERR_NO_FD (-1005) + +#define DRM_AGP_NO_HANDLE 0 + +typedef unsigned int drmSize, *drmSizePtr; /**< For mapped regions */ +typedef void *drmAddress, **drmAddressPtr; /**< For mapped regions */ + +typedef struct _drmServerInfo { + int (*debug_print)(const char *format, va_list ap); + int (*load_module)(const char *name); + void (*get_perms)(gid_t *, mode_t *); +} drmServerInfo, *drmServerInfoPtr; + +typedef struct drmHashEntry { + int fd; + void (*f)(int, void *, void *); + void *tagTable; +} drmHashEntry; + +extern int drmIoctl(int fd, unsigned long request, void *arg); +extern void *drmGetHashTable(void); +extern drmHashEntry *drmGetEntry(int fd); + +/** + * Driver version information. + * + * \sa drmGetVersion() and drmSetVersion(). + */ +typedef struct _drmVersion { + int version_major; /**< Major version */ + int version_minor; /**< Minor version */ + int version_patchlevel; /**< Patch level */ + int name_len; /**< Length of name buffer */ + char *name; /**< Name of driver */ + int date_len; /**< Length of date buffer */ + char *date; /**< User-space buffer to hold date */ + int desc_len; /**< Length of desc buffer */ + char *desc; /**< User-space buffer to hold desc */ +} drmVersion, *drmVersionPtr; + +typedef struct _drmStats { + unsigned long count; /**< Number of data */ + struct { + unsigned long value; /**< Value from kernel */ + const char *long_format; /**< Suggested format for long_name */ + const char *long_name; /**< Long name for value */ + const char *rate_format; /**< Suggested format for rate_name */ + const char *rate_name; /**< Short name for value per second */ + int isvalue; /**< True if value (vs. counter) */ + const char *mult_names; /**< Multiplier names (e.g., "KGM") */ + int mult; /**< Multiplier value (e.g., 1024) */ + int verbose; /**< Suggest only in verbose output */ + } data[15]; +} drmStatsT; + + + /* All of these enums *MUST* match with the + kernel implementation -- so do *NOT* + change them! (The drmlib implementation + will just copy the flags instead of + translating them.) */ +typedef enum { + DRM_FRAME_BUFFER = 0, /**< WC, no caching, no core dump */ + DRM_REGISTERS = 1, /**< no caching, no core dump */ + DRM_SHM = 2, /**< shared, cached */ + DRM_AGP = 3, /**< AGP/GART */ + DRM_SCATTER_GATHER = 4, /**< PCI scatter/gather */ + DRM_CONSISTENT = 5 /**< PCI consistent */ +} drmMapType; + +typedef enum { + DRM_RESTRICTED = 0x0001, /**< Cannot be mapped to client-virtual */ + DRM_READ_ONLY = 0x0002, /**< Read-only in client-virtual */ + DRM_LOCKED = 0x0004, /**< Physical pages locked */ + DRM_KERNEL = 0x0008, /**< Kernel requires access */ + DRM_WRITE_COMBINING = 0x0010, /**< Use write-combining, if available */ + DRM_CONTAINS_LOCK = 0x0020, /**< SHM page that contains lock */ + DRM_REMOVABLE = 0x0040 /**< Removable mapping */ +} drmMapFlags; + +/** + * \warning These values *MUST* match drm.h + */ +typedef enum { + /** \name Flags for DMA buffer dispatch */ + /*@{*/ + DRM_DMA_BLOCK = 0x01, /**< + * Block until buffer dispatched. + * + * \note the buffer may not yet have been + * processed by the hardware -- getting a + * hardware lock with the hardware quiescent + * will ensure that the buffer has been + * processed. + */ + DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ + DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ + /*@}*/ + + /** \name Flags for DMA buffer request */ + /*@{*/ + DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ + DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ + DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ + /*@}*/ +} drmDMAFlags; + +typedef enum { + DRM_PAGE_ALIGN = 0x01, + DRM_AGP_BUFFER = 0x02, + DRM_SG_BUFFER = 0x04, + DRM_FB_BUFFER = 0x08, + DRM_PCI_BUFFER_RO = 0x10 +} drmBufDescFlags; + +typedef enum { + DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ + DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ + DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ + DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ + /* These *HALT* flags aren't supported yet + -- they will be used to support the + full-screen DGA-like mode. */ + DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ + DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ +} drmLockFlags; + +typedef enum { + DRM_CONTEXT_PRESERVED = 0x01, /**< This context is preserved and + never swapped. */ + DRM_CONTEXT_2DONLY = 0x02 /**< This context is for 2D rendering only. */ +} drm_context_tFlags, *drm_context_tFlagsPtr; + +typedef struct _drmBufDesc { + int count; /**< Number of buffers of this size */ + int size; /**< Size in bytes */ + int low_mark; /**< Low water mark */ + int high_mark; /**< High water mark */ +} drmBufDesc, *drmBufDescPtr; + +typedef struct _drmBufInfo { + int count; /**< Number of buffers described in list */ + drmBufDescPtr list; /**< List of buffer descriptions */ +} drmBufInfo, *drmBufInfoPtr; + +typedef struct _drmBuf { + int idx; /**< Index into the master buffer list */ + int total; /**< Buffer size */ + int used; /**< Amount of buffer in use (for DMA) */ + drmAddress address; /**< Address */ +} drmBuf, *drmBufPtr; + +/** + * Buffer mapping information. + * + * Used by drmMapBufs() and drmUnmapBufs() to store information about the + * mapped buffers. + */ +typedef struct _drmBufMap { + int count; /**< Number of buffers mapped */ + drmBufPtr list; /**< Buffers */ +} drmBufMap, *drmBufMapPtr; + +typedef struct _drmLock { + volatile unsigned int lock; + char padding[60]; + /* This is big enough for most current (and future?) architectures: + DEC Alpha: 32 bytes + Intel Merced: ? + Intel P5/PPro/PII/PIII: 32 bytes + Intel StrongARM: 32 bytes + Intel i386/i486: 16 bytes + MIPS: 32 bytes (?) + Motorola 68k: 16 bytes + Motorola PowerPC: 32 bytes + Sun SPARC: 32 bytes + */ +} drmLock, *drmLockPtr; + +/** + * Indices here refer to the offset into + * list in drmBufInfo + */ +typedef struct _drmDMAReq { + drm_context_t context; /**< Context handle */ + int send_count; /**< Number of buffers to send */ + int *send_list; /**< List of handles to buffers */ + int *send_sizes; /**< Lengths of data to send, in bytes */ + drmDMAFlags flags; /**< Flags */ + int request_count; /**< Number of buffers requested */ + int request_size; /**< Desired size of buffers requested */ + int *request_list; /**< Buffer information */ + int *request_sizes; /**< Minimum acceptable sizes */ + int granted_count; /**< Number of buffers granted at this size */ +} drmDMAReq, *drmDMAReqPtr; + +typedef struct _drmRegion { + drm_handle_t handle; + unsigned int offset; + drmSize size; + drmAddress map; +} drmRegion, *drmRegionPtr; + +typedef struct _drmTextureRegion { + unsigned char next; + unsigned char prev; + unsigned char in_use; + unsigned char padding; /**< Explicitly pad this out */ + unsigned int age; +} drmTextureRegion, *drmTextureRegionPtr; + + +typedef enum { + DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ + DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ + /* bits 1-6 are reserved for high crtcs */ + DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, + DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ + DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ + DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ + DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ + DRM_VBLANK_SIGNAL = 0x40000000 /* Send signal instead of blocking */ +} drmVBlankSeqType; +#define DRM_VBLANK_HIGH_CRTC_SHIFT 1 + +typedef struct _drmVBlankReq { + drmVBlankSeqType type; + unsigned int sequence; + unsigned long signal; +} drmVBlankReq, *drmVBlankReqPtr; + +typedef struct _drmVBlankReply { + drmVBlankSeqType type; + unsigned int sequence; + long tval_sec; + long tval_usec; +} drmVBlankReply, *drmVBlankReplyPtr; + +typedef union _drmVBlank { + drmVBlankReq request; + drmVBlankReply reply; +} drmVBlank, *drmVBlankPtr; + +typedef struct _drmSetVersion { + int drm_di_major; + int drm_di_minor; + int drm_dd_major; + int drm_dd_minor; +} drmSetVersion, *drmSetVersionPtr; + +#define __drm_dummy_lock(lock) (*(__volatile__ unsigned int *)lock) + +#define DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ +#define DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ + +#if defined(__GNUC__) && (__GNUC__ >= 2) +# if defined(__i386) || defined(__AMD64__) || defined(__x86_64__) || defined(__amd64__) + /* Reflect changes here to drmP.h */ +#define DRM_CAS(lock,old,new,__ret) \ + do { \ + int __dummy; /* Can't mark eax as clobbered */ \ + __asm__ __volatile__( \ + "lock ; cmpxchg %4,%1\n\t" \ + "setnz %0" \ + : "=d" (__ret), \ + "=m" (__drm_dummy_lock(lock)), \ + "=a" (__dummy) \ + : "2" (old), \ + "r" (new)); \ + } while (0) + +#elif defined(__alpha__) + +#define DRM_CAS(lock, old, new, ret) \ + do { \ + int tmp, old32; \ + __asm__ __volatile__( \ + " addl $31, %5, %3\n" \ + "1: ldl_l %0, %2\n" \ + " cmpeq %0, %3, %1\n" \ + " beq %1, 2f\n" \ + " mov %4, %0\n" \ + " stl_c %0, %2\n" \ + " beq %0, 3f\n" \ + " mb\n" \ + "2: cmpeq %1, 0, %1\n" \ + ".subsection 2\n" \ + "3: br 1b\n" \ + ".previous" \ + : "=&r"(tmp), "=&r"(ret), \ + "=m"(__drm_dummy_lock(lock)), \ + "=&r"(old32) \ + : "r"(new), "r"(old) \ + : "memory"); \ + } while (0) + +#elif defined(__sparc__) + +#define DRM_CAS(lock,old,new,__ret) \ +do { register unsigned int __old __asm("o0"); \ + register unsigned int __new __asm("o1"); \ + register volatile unsigned int *__lock __asm("o2"); \ + __old = old; \ + __new = new; \ + __lock = (volatile unsigned int *)lock; \ + __asm__ __volatile__( \ + /*"cas [%2], %3, %0"*/ \ + ".word 0xd3e29008\n\t" \ + /*"membar #StoreStore | #StoreLoad"*/ \ + ".word 0x8143e00a" \ + : "=&r" (__new) \ + : "0" (__new), \ + "r" (__lock), \ + "r" (__old) \ + : "memory"); \ + __ret = (__new != __old); \ +} while(0) + +#elif defined(__ia64__) + +#ifdef __INTEL_COMPILER +/* this currently generates bad code (missing stop bits)... */ +#include + +#define DRM_CAS(lock,old,new,__ret) \ + do { \ + unsigned long __result, __old = (old) & 0xffffffff; \ + __mf(); \ + __result = _InterlockedCompareExchange_acq(&__drm_dummy_lock(lock), (new), __old);\ + __ret = (__result) != (__old); \ +/* __ret = (__sync_val_compare_and_swap(&__drm_dummy_lock(lock), \ + (old), (new)) \ + != (old)); */\ + } while (0) + +#else +#define DRM_CAS(lock,old,new,__ret) \ + do { \ + unsigned int __result, __old = (old); \ + __asm__ __volatile__( \ + "mf\n" \ + "mov ar.ccv=%2\n" \ + ";;\n" \ + "cmpxchg4.acq %0=%1,%3,ar.ccv" \ + : "=r" (__result), "=m" (__drm_dummy_lock(lock)) \ + : "r" ((unsigned long)__old), "r" (new) \ + : "memory"); \ + __ret = (__result) != (__old); \ + } while (0) + +#endif + +#elif defined(__powerpc__) + +#define DRM_CAS(lock,old,new,__ret) \ + do { \ + __asm__ __volatile__( \ + "sync;" \ + "0: lwarx %0,0,%1;" \ + " xor. %0,%3,%0;" \ + " bne 1f;" \ + " stwcx. %2,0,%1;" \ + " bne- 0b;" \ + "1: " \ + "sync;" \ + : "=&r"(__ret) \ + : "r"(lock), "r"(new), "r"(old) \ + : "cr0", "memory"); \ + } while (0) + +#endif /* architecture */ +#endif /* __GNUC__ >= 2 */ + +#ifndef DRM_CAS +#define DRM_CAS(lock,old,new,ret) do { ret=1; } while (0) /* FAST LOCK FAILS */ +#endif + +#if defined(__alpha__) +#define DRM_CAS_RESULT(_result) long _result +#elif defined(__powerpc__) +#define DRM_CAS_RESULT(_result) int _result +#else +#define DRM_CAS_RESULT(_result) char _result +#endif + +#define DRM_LIGHT_LOCK(fd,lock,context) \ + do { \ + DRM_CAS_RESULT(__ret); \ + DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); \ + if (__ret) drmGetLock(fd,context,0); \ + } while(0) + + /* This one counts fast locks -- for + benchmarking only. */ +#define DRM_LIGHT_LOCK_COUNT(fd,lock,context,count) \ + do { \ + DRM_CAS_RESULT(__ret); \ + DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); \ + if (__ret) drmGetLock(fd,context,0); \ + else ++count; \ + } while(0) + +#define DRM_LOCK(fd,lock,context,flags) \ + do { \ + if (flags) drmGetLock(fd,context,flags); \ + else DRM_LIGHT_LOCK(fd,lock,context); \ + } while(0) + +#define DRM_UNLOCK(fd,lock,context) \ + do { \ + DRM_CAS_RESULT(__ret); \ + DRM_CAS(lock,DRM_LOCK_HELD|context,context,__ret); \ + if (__ret) drmUnlock(fd,context); \ + } while(0) + + /* Simple spin locks */ +#define DRM_SPINLOCK(spin,val) \ + do { \ + DRM_CAS_RESULT(__ret); \ + do { \ + DRM_CAS(spin,0,val,__ret); \ + if (__ret) while ((spin)->lock); \ + } while (__ret); \ + } while(0) + +#define DRM_SPINLOCK_TAKE(spin,val) \ + do { \ + DRM_CAS_RESULT(__ret); \ + int cur; \ + do { \ + cur = (*spin).lock; \ + DRM_CAS(spin,cur,val,__ret); \ + } while (__ret); \ + } while(0) + +#define DRM_SPINLOCK_COUNT(spin,val,count,__ret) \ + do { \ + int __i; \ + __ret = 1; \ + for (__i = 0; __ret && __i < count; __i++) { \ + DRM_CAS(spin,0,val,__ret); \ + if (__ret) for (;__i < count && (spin)->lock; __i++); \ + } \ + } while(0) + +#define DRM_SPINUNLOCK(spin,val) \ + do { \ + DRM_CAS_RESULT(__ret); \ + if ((*spin).lock == val) { /* else server stole lock */ \ + do { \ + DRM_CAS(spin,val,0,__ret); \ + } while (__ret); \ + } \ + } while(0) + + + +/* General user-level programmer's API: unprivileged */ +extern int drmAvailable(void); +extern int drmOpen(const char *name, const char *busid); +extern int drmOpenControl(int minor); +extern int drmClose(int fd); +extern drmVersionPtr drmGetVersion(int fd); +extern drmVersionPtr drmGetLibVersion(int fd); +extern int drmGetCap(int fd, uint64_t capability, uint64_t *value); +extern void drmFreeVersion(drmVersionPtr); +extern int drmGetMagic(int fd, drm_magic_t * magic); +extern char *drmGetBusid(int fd); +extern int drmGetInterruptFromBusID(int fd, int busnum, int devnum, + int funcnum); +extern int drmGetMap(int fd, int idx, drm_handle_t *offset, + drmSize *size, drmMapType *type, + drmMapFlags *flags, drm_handle_t *handle, + int *mtrr); +extern int drmGetClient(int fd, int idx, int *auth, int *pid, + int *uid, unsigned long *magic, + unsigned long *iocs); +extern int drmGetStats(int fd, drmStatsT *stats); +extern int drmSetInterfaceVersion(int fd, drmSetVersion *version); +extern int drmCommandNone(int fd, unsigned long drmCommandIndex); +extern int drmCommandRead(int fd, unsigned long drmCommandIndex, + void *data, unsigned long size); +extern int drmCommandWrite(int fd, unsigned long drmCommandIndex, + void *data, unsigned long size); +extern int drmCommandWriteRead(int fd, unsigned long drmCommandIndex, + void *data, unsigned long size); + +/* General user-level programmer's API: X server (root) only */ +extern void drmFreeBusid(const char *busid); +extern int drmSetBusid(int fd, const char *busid); +extern int drmAuthMagic(int fd, drm_magic_t magic); +extern int drmAddMap(int fd, + drm_handle_t offset, + drmSize size, + drmMapType type, + drmMapFlags flags, + drm_handle_t * handle); +extern int drmRmMap(int fd, drm_handle_t handle); +extern int drmAddContextPrivateMapping(int fd, drm_context_t ctx_id, + drm_handle_t handle); + +extern int drmAddBufs(int fd, int count, int size, + drmBufDescFlags flags, + int agp_offset); +extern int drmMarkBufs(int fd, double low, double high); +extern int drmCreateContext(int fd, drm_context_t * handle); +extern int drmSetContextFlags(int fd, drm_context_t context, + drm_context_tFlags flags); +extern int drmGetContextFlags(int fd, drm_context_t context, + drm_context_tFlagsPtr flags); +extern int drmAddContextTag(int fd, drm_context_t context, void *tag); +extern int drmDelContextTag(int fd, drm_context_t context); +extern void *drmGetContextTag(int fd, drm_context_t context); +extern drm_context_t * drmGetReservedContextList(int fd, int *count); +extern void drmFreeReservedContextList(drm_context_t *); +extern int drmSwitchToContext(int fd, drm_context_t context); +extern int drmDestroyContext(int fd, drm_context_t handle); +extern int drmCreateDrawable(int fd, drm_drawable_t * handle); +extern int drmDestroyDrawable(int fd, drm_drawable_t handle); +extern int drmUpdateDrawableInfo(int fd, drm_drawable_t handle, + drm_drawable_info_type_t type, + unsigned int num, void *data); +extern int drmCtlInstHandler(int fd, int irq); +extern int drmCtlUninstHandler(int fd); + +/* General user-level programmer's API: authenticated client and/or X */ +extern int drmMap(int fd, + drm_handle_t handle, + drmSize size, + drmAddressPtr address); +extern int drmUnmap(drmAddress address, drmSize size); +extern drmBufInfoPtr drmGetBufInfo(int fd); +extern drmBufMapPtr drmMapBufs(int fd); +extern int drmUnmapBufs(drmBufMapPtr bufs); +extern int drmDMA(int fd, drmDMAReqPtr request); +extern int drmFreeBufs(int fd, int count, int *list); +extern int drmGetLock(int fd, + drm_context_t context, + drmLockFlags flags); +extern int drmUnlock(int fd, drm_context_t context); +extern int drmFinish(int fd, int context, drmLockFlags flags); +extern int drmGetContextPrivateMapping(int fd, drm_context_t ctx_id, + drm_handle_t * handle); + +/* AGP/GART support: X server (root) only */ +extern int drmAgpAcquire(int fd); +extern int drmAgpRelease(int fd); +extern int drmAgpEnable(int fd, unsigned long mode); +extern int drmAgpAlloc(int fd, unsigned long size, + unsigned long type, unsigned long *address, + drm_handle_t *handle); +extern int drmAgpFree(int fd, drm_handle_t handle); +extern int drmAgpBind(int fd, drm_handle_t handle, + unsigned long offset); +extern int drmAgpUnbind(int fd, drm_handle_t handle); + +/* AGP/GART info: authenticated client and/or X */ +extern int drmAgpVersionMajor(int fd); +extern int drmAgpVersionMinor(int fd); +extern unsigned long drmAgpGetMode(int fd); +extern unsigned long drmAgpBase(int fd); /* Physical location */ +extern unsigned long drmAgpSize(int fd); /* Bytes */ +extern unsigned long drmAgpMemoryUsed(int fd); +extern unsigned long drmAgpMemoryAvail(int fd); +extern unsigned int drmAgpVendorId(int fd); +extern unsigned int drmAgpDeviceId(int fd); + +/* PCI scatter/gather support: X server (root) only */ +extern int drmScatterGatherAlloc(int fd, unsigned long size, + drm_handle_t *handle); +extern int drmScatterGatherFree(int fd, drm_handle_t handle); + +extern int drmWaitVBlank(int fd, drmVBlankPtr vbl); + +/* Support routines */ +extern void drmSetServerInfo(drmServerInfoPtr info); +extern int drmError(int err, const char *label); +extern void *drmMalloc(int size); +extern void drmFree(void *pt); + +/* Hash table routines */ +extern void *drmHashCreate(void); +extern int drmHashDestroy(void *t); +extern int drmHashLookup(void *t, unsigned long key, void **value); +extern int drmHashInsert(void *t, unsigned long key, void *value); +extern int drmHashDelete(void *t, unsigned long key); +extern int drmHashFirst(void *t, unsigned long *key, void **value); +extern int drmHashNext(void *t, unsigned long *key, void **value); + +/* PRNG routines */ +extern void *drmRandomCreate(unsigned long seed); +extern int drmRandomDestroy(void *state); +extern unsigned long drmRandom(void *state); +extern double drmRandomDouble(void *state); + +/* Skip list routines */ + +extern void *drmSLCreate(void); +extern int drmSLDestroy(void *l); +extern int drmSLLookup(void *l, unsigned long key, void **value); +extern int drmSLInsert(void *l, unsigned long key, void *value); +extern int drmSLDelete(void *l, unsigned long key); +extern int drmSLNext(void *l, unsigned long *key, void **value); +extern int drmSLFirst(void *l, unsigned long *key, void **value); +extern void drmSLDump(void *l); +extern int drmSLLookupNeighbors(void *l, unsigned long key, + unsigned long *prev_key, void **prev_value, + unsigned long *next_key, void **next_value); + +extern int drmOpenOnce(void *unused, const char *BusID, int *newlyopened); +extern void drmCloseOnce(int fd); +extern void drmMsg(const char *format, ...); + +extern int drmSetMaster(int fd); +extern int drmDropMaster(int fd); + +#define DRM_EVENT_CONTEXT_VERSION 2 + +typedef struct _drmEventContext { + + /* This struct is versioned so we can add more pointers if we + * add more events. */ + int version; + + void (*vblank_handler)(int fd, + unsigned int sequence, + unsigned int tv_sec, + unsigned int tv_usec, + void *user_data); + + void (*page_flip_handler)(int fd, + unsigned int sequence, + unsigned int tv_sec, + unsigned int tv_usec, + void *user_data); + +} drmEventContext, *drmEventContextPtr; + +extern int drmHandleEvent(int fd, drmEventContextPtr evctx); + +extern char *drmGetDeviceNameFromFd(int fd); + +#if defined(__cplusplus) || defined(c_plusplus) +} +#endif + +#endif diff --git a/xf86drmHash.c b/xf86drmHash.c new file mode 100644 index 0000000..82cbc2a --- /dev/null +++ b/xf86drmHash.c @@ -0,0 +1,428 @@ +/* xf86drmHash.c -- Small hash table support for integer -> integer mapping + * Created: Sun Apr 18 09:35:45 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * + * DESCRIPTION + * + * This file contains a straightforward implementation of a fixed-sized + * hash table using self-organizing linked lists [Knuth73, pp. 398-399] for + * collision resolution. There are two potentially interesting things + * about this implementation: + * + * 1) The table is power-of-two sized. Prime sized tables are more + * traditional, but do not have a significant advantage over power-of-two + * sized table, especially when double hashing is not used for collision + * resolution. + * + * 2) The hash computation uses a table of random integers [Hanson97, + * pp. 39-41]. + * + * FUTURE ENHANCEMENTS + * + * With a table size of 512, the current implementation is sufficient for a + * few hundred keys. Since this is well above the expected size of the + * tables for which this implementation was designed, the implementation of + * dynamic hash tables was postponed until the need arises. A common (and + * naive) approach to dynamic hash table implementation simply creates a + * new hash table when necessary, rehashes all the data into the new table, + * and destroys the old table. The approach in [Larson88] is superior in + * two ways: 1) only a portion of the table is expanded when needed, + * distributing the expansion cost over several insertions, and 2) portions + * of the table can be locked, enabling a scalable thread-safe + * implementation. + * + * REFERENCES + * + * [Hanson97] David R. Hanson. C Interfaces and Implementations: + * Techniques for Creating Reusable Software. Reading, Massachusetts: + * Addison-Wesley, 1997. + * + * [Knuth73] Donald E. Knuth. The Art of Computer Programming. Volume 3: + * Sorting and Searching. Reading, Massachusetts: Addison-Wesley, 1973. + * + * [Larson88] Per-Ake Larson. "Dynamic Hash Tables". CACM 31(4), April + * 1988, pp. 446-457. + * + */ + +#include +#include + +#define HASH_MAIN 0 + +#if !HASH_MAIN +# include "xf86drm.h" +#endif + +#define HASH_MAGIC 0xdeadbeef +#define HASH_DEBUG 0 +#define HASH_SIZE 512 /* Good for about 100 entries */ + /* If you change this value, you probably + have to change the HashHash hashing + function! */ + +#if HASH_MAIN +#define HASH_ALLOC malloc +#define HASH_FREE free +#define HASH_RANDOM_DECL +#define HASH_RANDOM_INIT(seed) srandom(seed) +#define HASH_RANDOM random() +#define HASH_RANDOM_DESTROY +#else +#define HASH_ALLOC drmMalloc +#define HASH_FREE drmFree +#define HASH_RANDOM_DECL void *state +#define HASH_RANDOM_INIT(seed) state = drmRandomCreate(seed) +#define HASH_RANDOM drmRandom(state) +#define HASH_RANDOM_DESTROY drmRandomDestroy(state) + +#endif + +typedef struct HashBucket { + unsigned long key; + void *value; + struct HashBucket *next; +} HashBucket, *HashBucketPtr; + +typedef struct HashTable { + unsigned long magic; + unsigned long entries; + unsigned long hits; /* At top of linked list */ + unsigned long partials; /* Not at top of linked list */ + unsigned long misses; /* Not in table */ + HashBucketPtr buckets[HASH_SIZE]; + int p0; + HashBucketPtr p1; +} HashTable, *HashTablePtr; + +#if HASH_MAIN +extern void *drmHashCreate(void); +extern int drmHashDestroy(void *t); +extern int drmHashLookup(void *t, unsigned long key, unsigned long *value); +extern int drmHashInsert(void *t, unsigned long key, unsigned long value); +extern int drmHashDelete(void *t, unsigned long key); +#endif + +static unsigned long HashHash(unsigned long key) +{ + unsigned long hash = 0; + unsigned long tmp = key; + static int init = 0; + static unsigned long scatter[256]; + int i; + + if (!init) { + HASH_RANDOM_DECL; + HASH_RANDOM_INIT(37); + for (i = 0; i < 256; i++) scatter[i] = HASH_RANDOM; + HASH_RANDOM_DESTROY; + ++init; + } + + while (tmp) { + hash = (hash << 1) + scatter[tmp & 0xff]; + tmp >>= 8; + } + + hash %= HASH_SIZE; +#if HASH_DEBUG + printf( "Hash(%d) = %d\n", key, hash); +#endif + return hash; +} + +void *drmHashCreate(void) +{ + HashTablePtr table; + int i; + + table = HASH_ALLOC(sizeof(*table)); + if (!table) return NULL; + table->magic = HASH_MAGIC; + table->entries = 0; + table->hits = 0; + table->partials = 0; + table->misses = 0; + + for (i = 0; i < HASH_SIZE; i++) table->buckets[i] = NULL; + return table; +} + +int drmHashDestroy(void *t) +{ + HashTablePtr table = (HashTablePtr)t; + HashBucketPtr bucket; + HashBucketPtr next; + int i; + + if (table->magic != HASH_MAGIC) return -1; /* Bad magic */ + + for (i = 0; i < HASH_SIZE; i++) { + for (bucket = table->buckets[i]; bucket;) { + next = bucket->next; + HASH_FREE(bucket); + bucket = next; + } + } + HASH_FREE(table); + return 0; +} + +/* Find the bucket and organize the list so that this bucket is at the + top. */ + +static HashBucketPtr HashFind(HashTablePtr table, + unsigned long key, unsigned long *h) +{ + unsigned long hash = HashHash(key); + HashBucketPtr prev = NULL; + HashBucketPtr bucket; + + if (h) *h = hash; + + for (bucket = table->buckets[hash]; bucket; bucket = bucket->next) { + if (bucket->key == key) { + if (prev) { + /* Organize */ + prev->next = bucket->next; + bucket->next = table->buckets[hash]; + table->buckets[hash] = bucket; + ++table->partials; + } else { + ++table->hits; + } + return bucket; + } + prev = bucket; + } + ++table->misses; + return NULL; +} + +int drmHashLookup(void *t, unsigned long key, void **value) +{ + HashTablePtr table = (HashTablePtr)t; + HashBucketPtr bucket; + + if (!table || table->magic != HASH_MAGIC) return -1; /* Bad magic */ + + bucket = HashFind(table, key, NULL); + if (!bucket) return 1; /* Not found */ + *value = bucket->value; + return 0; /* Found */ +} + +int drmHashInsert(void *t, unsigned long key, void *value) +{ + HashTablePtr table = (HashTablePtr)t; + HashBucketPtr bucket; + unsigned long hash; + + if (table->magic != HASH_MAGIC) return -1; /* Bad magic */ + + if (HashFind(table, key, &hash)) return 1; /* Already in table */ + + bucket = HASH_ALLOC(sizeof(*bucket)); + if (!bucket) return -1; /* Error */ + bucket->key = key; + bucket->value = value; + bucket->next = table->buckets[hash]; + table->buckets[hash] = bucket; +#if HASH_DEBUG + printf("Inserted %d at %d/%p\n", key, hash, bucket); +#endif + return 0; /* Added to table */ +} + +int drmHashDelete(void *t, unsigned long key) +{ + HashTablePtr table = (HashTablePtr)t; + unsigned long hash; + HashBucketPtr bucket; + + if (table->magic != HASH_MAGIC) return -1; /* Bad magic */ + + bucket = HashFind(table, key, &hash); + + if (!bucket) return 1; /* Not found */ + + table->buckets[hash] = bucket->next; + HASH_FREE(bucket); + return 0; +} + +int drmHashNext(void *t, unsigned long *key, void **value) +{ + HashTablePtr table = (HashTablePtr)t; + + while (table->p0 < HASH_SIZE) { + if (table->p1) { + *key = table->p1->key; + *value = table->p1->value; + table->p1 = table->p1->next; + return 1; + } + table->p1 = table->buckets[table->p0]; + ++table->p0; + } + return 0; +} + +int drmHashFirst(void *t, unsigned long *key, void **value) +{ + HashTablePtr table = (HashTablePtr)t; + + if (table->magic != HASH_MAGIC) return -1; /* Bad magic */ + + table->p0 = 0; + table->p1 = table->buckets[0]; + return drmHashNext(table, key, value); +} + +#if HASH_MAIN +#define DIST_LIMIT 10 +static int dist[DIST_LIMIT]; + +static void clear_dist(void) { + int i; + + for (i = 0; i < DIST_LIMIT; i++) dist[i] = 0; +} + +static int count_entries(HashBucketPtr bucket) +{ + int count = 0; + + for (; bucket; bucket = bucket->next) ++count; + return count; +} + +static void update_dist(int count) +{ + if (count >= DIST_LIMIT) ++dist[DIST_LIMIT-1]; + else ++dist[count]; +} + +static void compute_dist(HashTablePtr table) +{ + int i; + HashBucketPtr bucket; + + printf("Entries = %ld, hits = %ld, partials = %ld, misses = %ld\n", + table->entries, table->hits, table->partials, table->misses); + clear_dist(); + for (i = 0; i < HASH_SIZE; i++) { + bucket = table->buckets[i]; + update_dist(count_entries(bucket)); + } + for (i = 0; i < DIST_LIMIT; i++) { + if (i != DIST_LIMIT-1) printf("%5d %10d\n", i, dist[i]); + else printf("other %10d\n", dist[i]); + } +} + +static void check_table(HashTablePtr table, + unsigned long key, unsigned long value) +{ + unsigned long retval = 0; + int retcode = drmHashLookup(table, key, &retval); + + switch (retcode) { + case -1: + printf("Bad magic = 0x%08lx:" + " key = %lu, expected = %lu, returned = %lu\n", + table->magic, key, value, retval); + break; + case 1: + printf("Not found: key = %lu, expected = %lu returned = %lu\n", + key, value, retval); + break; + case 0: + if (value != retval) + printf("Bad value: key = %lu, expected = %lu, returned = %lu\n", + key, value, retval); + break; + default: + printf("Bad retcode = %d: key = %lu, expected = %lu, returned = %lu\n", + retcode, key, value, retval); + break; + } +} + +int main(void) +{ + HashTablePtr table; + int i; + + printf("\n***** 256 consecutive integers ****\n"); + table = drmHashCreate(); + for (i = 0; i < 256; i++) drmHashInsert(table, i, i); + for (i = 0; i < 256; i++) check_table(table, i, i); + for (i = 256; i >= 0; i--) check_table(table, i, i); + compute_dist(table); + drmHashDestroy(table); + + printf("\n***** 1024 consecutive integers ****\n"); + table = drmHashCreate(); + for (i = 0; i < 1024; i++) drmHashInsert(table, i, i); + for (i = 0; i < 1024; i++) check_table(table, i, i); + for (i = 1024; i >= 0; i--) check_table(table, i, i); + compute_dist(table); + drmHashDestroy(table); + + printf("\n***** 1024 consecutive page addresses (4k pages) ****\n"); + table = drmHashCreate(); + for (i = 0; i < 1024; i++) drmHashInsert(table, i*4096, i); + for (i = 0; i < 1024; i++) check_table(table, i*4096, i); + for (i = 1024; i >= 0; i--) check_table(table, i*4096, i); + compute_dist(table); + drmHashDestroy(table); + + printf("\n***** 1024 random integers ****\n"); + table = drmHashCreate(); + srandom(0xbeefbeef); + for (i = 0; i < 1024; i++) drmHashInsert(table, random(), i); + srandom(0xbeefbeef); + for (i = 0; i < 1024; i++) check_table(table, random(), i); + srandom(0xbeefbeef); + for (i = 0; i < 1024; i++) check_table(table, random(), i); + compute_dist(table); + drmHashDestroy(table); + + printf("\n***** 5000 random integers ****\n"); + table = drmHashCreate(); + srandom(0xbeefbeef); + for (i = 0; i < 5000; i++) drmHashInsert(table, random(), i); + srandom(0xbeefbeef); + for (i = 0; i < 5000; i++) check_table(table, random(), i); + srandom(0xbeefbeef); + for (i = 0; i < 5000; i++) check_table(table, random(), i); + compute_dist(table); + drmHashDestroy(table); + + return 0; +} +#endif diff --git a/xf86drmMode.c b/xf86drmMode.c new file mode 100644 index 0000000..04fdf1f --- /dev/null +++ b/xf86drmMode.c @@ -0,0 +1,1059 @@ +/* + * \file xf86drmMode.c + * Header for DRM modesetting interface. + * + * \author Jakob Bornecrantz + * + * \par Acknowledgements: + * Feb 2007, Dave Airlie + */ + +/* + * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas. + * Copyright (c) 2007-2008 Dave Airlie + * Copyright (c) 2007-2008 Jakob Bornecrantz + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* + * TODO the types we are after are defined in diffrent headers on diffrent + * platforms find which headers to include to get uint32_t + */ +#include +#include +#include + +#include "xf86drmMode.h" +#include "xf86drm.h" +#include +#include +#include +#include +#include + +#define U642VOID(x) ((void *)(unsigned long)(x)) +#define VOID2U64(x) ((uint64_t)(unsigned long)(x)) + +static inline int DRM_IOCTL(int fd, unsigned long cmd, void *arg) +{ + int ret = drmIoctl(fd, cmd, arg); + return ret < 0 ? -errno : ret; +} + +/* + * Util functions + */ + +void* drmAllocCpy(void *array, int count, int entry_size) +{ + char *r; + int i; + + if (!count || !array || !entry_size) + return 0; + + if (!(r = drmMalloc(count*entry_size))) + return 0; + + for (i = 0; i < count; i++) + memcpy(r+(entry_size*i), array+(entry_size*i), entry_size); + + return r; +} + +/* + * A couple of free functions. + */ + +void drmModeFreeModeInfo(drmModeModeInfoPtr ptr) +{ + if (!ptr) + return; + + drmFree(ptr); +} + +void drmModeFreeResources(drmModeResPtr ptr) +{ + if (!ptr) + return; + + drmFree(ptr->fbs); + drmFree(ptr->crtcs); + drmFree(ptr->connectors); + drmFree(ptr->encoders); + drmFree(ptr); + +} + +void drmModeFreeFB(drmModeFBPtr ptr) +{ + if (!ptr) + return; + + /* we might add more frees later. */ + drmFree(ptr); +} + +void drmModeFreeCrtc(drmModeCrtcPtr ptr) +{ + if (!ptr) + return; + + drmFree(ptr); + +} + +void drmModeFreeConnector(drmModeConnectorPtr ptr) +{ + if (!ptr) + return; + + drmFree(ptr->encoders); + drmFree(ptr->prop_values); + drmFree(ptr->props); + drmFree(ptr->modes); + drmFree(ptr); + +} + +void drmModeFreeEncoder(drmModeEncoderPtr ptr) +{ + drmFree(ptr); +} + +/* + * ModeSetting functions. + */ + +drmModeResPtr drmModeGetResources(int fd) +{ + struct drm_mode_card_res res, counts; + drmModeResPtr r = 0; + +retry: + memset(&res, 0, sizeof(struct drm_mode_card_res)); + if (drmIoctl(fd, DRM_IOCTL_MODE_GETRESOURCES, &res)) + return 0; + + counts = res; + + if (res.count_fbs) { + res.fb_id_ptr = VOID2U64(drmMalloc(res.count_fbs*sizeof(uint32_t))); + if (!res.fb_id_ptr) + goto err_allocs; + } + if (res.count_crtcs) { + res.crtc_id_ptr = VOID2U64(drmMalloc(res.count_crtcs*sizeof(uint32_t))); + if (!res.crtc_id_ptr) + goto err_allocs; + } + if (res.count_connectors) { + res.connector_id_ptr = VOID2U64(drmMalloc(res.count_connectors*sizeof(uint32_t))); + if (!res.connector_id_ptr) + goto err_allocs; + } + if (res.count_encoders) { + res.encoder_id_ptr = VOID2U64(drmMalloc(res.count_encoders*sizeof(uint32_t))); + if (!res.encoder_id_ptr) + goto err_allocs; + } + + if (drmIoctl(fd, DRM_IOCTL_MODE_GETRESOURCES, &res)) + goto err_allocs; + + /* The number of available connectors and etc may have changed with a + * hotplug event in between the ioctls, in which case the field is + * silently ignored by the kernel. + */ + if (counts.count_fbs < res.count_fbs || + counts.count_crtcs < res.count_crtcs || + counts.count_connectors < res.count_connectors || + counts.count_encoders < res.count_encoders) + { + drmFree(U642VOID(res.fb_id_ptr)); + drmFree(U642VOID(res.crtc_id_ptr)); + drmFree(U642VOID(res.connector_id_ptr)); + drmFree(U642VOID(res.encoder_id_ptr)); + + goto retry; + } + + /* + * return + */ + if (!(r = drmMalloc(sizeof(*r)))) + goto err_allocs; + + r->min_width = res.min_width; + r->max_width = res.max_width; + r->min_height = res.min_height; + r->max_height = res.max_height; + r->count_fbs = res.count_fbs; + r->count_crtcs = res.count_crtcs; + r->count_connectors = res.count_connectors; + r->count_encoders = res.count_encoders; + + r->fbs = drmAllocCpy(U642VOID(res.fb_id_ptr), res.count_fbs, sizeof(uint32_t)); + r->crtcs = drmAllocCpy(U642VOID(res.crtc_id_ptr), res.count_crtcs, sizeof(uint32_t)); + r->connectors = drmAllocCpy(U642VOID(res.connector_id_ptr), res.count_connectors, sizeof(uint32_t)); + r->encoders = drmAllocCpy(U642VOID(res.encoder_id_ptr), res.count_encoders, sizeof(uint32_t)); + if ((res.count_fbs && !r->fbs) || + (res.count_crtcs && !r->crtcs) || + (res.count_connectors && !r->connectors) || + (res.count_encoders && !r->encoders)) + { + drmFree(r->fbs); + drmFree(r->crtcs); + drmFree(r->connectors); + drmFree(r->encoders); + drmFree(r); + r = 0; + } + +err_allocs: + drmFree(U642VOID(res.fb_id_ptr)); + drmFree(U642VOID(res.crtc_id_ptr)); + drmFree(U642VOID(res.connector_id_ptr)); + drmFree(U642VOID(res.encoder_id_ptr)); + + return r; +} + +int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth, + uint8_t bpp, uint32_t pitch, uint32_t bo_handle, + uint32_t *buf_id) +{ + struct drm_mode_fb_cmd f; + int ret; + + f.width = width; + f.height = height; + f.pitch = pitch; + f.bpp = bpp; + f.depth = depth; + f.handle = bo_handle; + + if ((ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_ADDFB, &f))) + return ret; + + *buf_id = f.fb_id; + return 0; +} + +int drmModeAddFB2(int fd, uint32_t width, uint32_t height, + uint32_t pixel_format, uint32_t bo_handles[4], + uint32_t pitches[4], uint32_t offsets[4], + uint32_t *buf_id, uint32_t flags) +{ + struct drm_mode_fb_cmd2 f; + int ret; + + f.width = width; + f.height = height; + f.pixel_format = pixel_format; + f.flags = flags; + memcpy(f.handles, bo_handles, 4 * sizeof(bo_handles[0])); + memcpy(f.pitches, pitches, 4 * sizeof(pitches[0])); + memcpy(f.offsets, offsets, 4 * sizeof(offsets[0])); + + if ((ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_ADDFB2, &f))) + return ret; + + *buf_id = f.fb_id; + return 0; +} + +int drmModeRmFB(int fd, uint32_t bufferId) +{ + return DRM_IOCTL(fd, DRM_IOCTL_MODE_RMFB, &bufferId); + + +} + +drmModeFBPtr drmModeGetFB(int fd, uint32_t buf) +{ + struct drm_mode_fb_cmd info; + drmModeFBPtr r; + + info.fb_id = buf; + + if (drmIoctl(fd, DRM_IOCTL_MODE_GETFB, &info)) + return NULL; + + if (!(r = drmMalloc(sizeof(*r)))) + return NULL; + + r->fb_id = info.fb_id; + r->width = info.width; + r->height = info.height; + r->pitch = info.pitch; + r->bpp = info.bpp; + r->handle = info.handle; + r->depth = info.depth; + + return r; +} + +int drmModeDirtyFB(int fd, uint32_t bufferId, + drmModeClipPtr clips, uint32_t num_clips) +{ + struct drm_mode_fb_dirty_cmd dirty = { 0 }; + + dirty.fb_id = bufferId; + dirty.clips_ptr = VOID2U64(clips); + dirty.num_clips = num_clips; + + return DRM_IOCTL(fd, DRM_IOCTL_MODE_DIRTYFB, &dirty); +} + + +/* + * Crtc functions + */ + +drmModeCrtcPtr drmModeGetCrtc(int fd, uint32_t crtcId) +{ + struct drm_mode_crtc crtc; + drmModeCrtcPtr r; + + crtc.crtc_id = crtcId; + + if (drmIoctl(fd, DRM_IOCTL_MODE_GETCRTC, &crtc)) + return 0; + + /* + * return + */ + + if (!(r = drmMalloc(sizeof(*r)))) + return 0; + + r->crtc_id = crtc.crtc_id; + r->x = crtc.x; + r->y = crtc.y; + r->mode_valid = crtc.mode_valid; + if (r->mode_valid) + memcpy(&r->mode, &crtc.mode, sizeof(struct drm_mode_modeinfo)); + r->buffer_id = crtc.fb_id; + r->gamma_size = crtc.gamma_size; + return r; +} + + +int drmModeSetCrtc(int fd, uint32_t crtcId, uint32_t bufferId, + uint32_t x, uint32_t y, uint32_t *connectors, int count, + drmModeModeInfoPtr mode) +{ + struct drm_mode_crtc crtc; + + crtc.x = x; + crtc.y = y; + crtc.crtc_id = crtcId; + crtc.fb_id = bufferId; + crtc.set_connectors_ptr = VOID2U64(connectors); + crtc.count_connectors = count; + if (mode) { + memcpy(&crtc.mode, mode, sizeof(struct drm_mode_modeinfo)); + crtc.mode_valid = 1; + } else + crtc.mode_valid = 0; + + return DRM_IOCTL(fd, DRM_IOCTL_MODE_SETCRTC, &crtc); +} + +/* + * Cursor manipulation + */ + +int drmModeSetCursor(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width, uint32_t height) +{ + struct drm_mode_cursor arg; + + arg.flags = DRM_MODE_CURSOR_BO; + arg.crtc_id = crtcId; + arg.width = width; + arg.height = height; + arg.handle = bo_handle; + + return DRM_IOCTL(fd, DRM_IOCTL_MODE_CURSOR, &arg); +} + +int drmModeMoveCursor(int fd, uint32_t crtcId, int x, int y) +{ + struct drm_mode_cursor arg; + + arg.flags = DRM_MODE_CURSOR_MOVE; + arg.crtc_id = crtcId; + arg.x = x; + arg.y = y; + + return DRM_IOCTL(fd, DRM_IOCTL_MODE_CURSOR, &arg); +} + +/* + * Encoder get + */ +drmModeEncoderPtr drmModeGetEncoder(int fd, uint32_t encoder_id) +{ + struct drm_mode_get_encoder enc; + drmModeEncoderPtr r = NULL; + + enc.encoder_id = encoder_id; + enc.encoder_type = 0; + enc.possible_crtcs = 0; + enc.possible_clones = 0; + + if (drmIoctl(fd, DRM_IOCTL_MODE_GETENCODER, &enc)) + return 0; + + if (!(r = drmMalloc(sizeof(*r)))) + return 0; + + r->encoder_id = enc.encoder_id; + r->crtc_id = enc.crtc_id; + r->encoder_type = enc.encoder_type; + r->possible_crtcs = enc.possible_crtcs; + r->possible_clones = enc.possible_clones; + + return r; +} + +/* + * Connector manipulation + */ + +drmModeConnectorPtr drmModeGetConnector(int fd, uint32_t connector_id) +{ + struct drm_mode_get_connector conn, counts; + drmModeConnectorPtr r = NULL; + +retry: + memset(&conn, 0, sizeof(struct drm_mode_get_connector)); + conn.connector_id = connector_id; + + if (drmIoctl(fd, DRM_IOCTL_MODE_GETCONNECTOR, &conn)) + return 0; + + counts = conn; + + if (conn.count_props) { + conn.props_ptr = VOID2U64(drmMalloc(conn.count_props*sizeof(uint32_t))); + if (!conn.props_ptr) + goto err_allocs; + conn.prop_values_ptr = VOID2U64(drmMalloc(conn.count_props*sizeof(uint64_t))); + if (!conn.prop_values_ptr) + goto err_allocs; + } + + if (conn.count_modes) { + conn.modes_ptr = VOID2U64(drmMalloc(conn.count_modes*sizeof(struct drm_mode_modeinfo))); + if (!conn.modes_ptr) + goto err_allocs; + } + + if (conn.count_encoders) { + conn.encoders_ptr = VOID2U64(drmMalloc(conn.count_encoders*sizeof(uint32_t))); + if (!conn.encoders_ptr) + goto err_allocs; + } + + if (drmIoctl(fd, DRM_IOCTL_MODE_GETCONNECTOR, &conn)) + goto err_allocs; + + /* The number of available connectors and etc may have changed with a + * hotplug event in between the ioctls, in which case the field is + * silently ignored by the kernel. + */ + if (counts.count_props < conn.count_props || + counts.count_modes < conn.count_modes || + counts.count_encoders < conn.count_encoders) { + drmFree(U642VOID(conn.props_ptr)); + drmFree(U642VOID(conn.prop_values_ptr)); + drmFree(U642VOID(conn.modes_ptr)); + drmFree(U642VOID(conn.encoders_ptr)); + + goto retry; + } + + if(!(r = drmMalloc(sizeof(*r)))) { + goto err_allocs; + } + + r->connector_id = conn.connector_id; + r->encoder_id = conn.encoder_id; + r->connection = conn.connection; + r->mmWidth = conn.mm_width; + r->mmHeight = conn.mm_height; + /* convert subpixel from kernel to userspace */ + r->subpixel = conn.subpixel + 1; + r->count_modes = conn.count_modes; + r->count_props = conn.count_props; + r->props = drmAllocCpy(U642VOID(conn.props_ptr), conn.count_props, sizeof(uint32_t)); + r->prop_values = drmAllocCpy(U642VOID(conn.prop_values_ptr), conn.count_props, sizeof(uint64_t)); + r->modes = drmAllocCpy(U642VOID(conn.modes_ptr), conn.count_modes, sizeof(struct drm_mode_modeinfo)); + r->count_encoders = conn.count_encoders; + r->encoders = drmAllocCpy(U642VOID(conn.encoders_ptr), conn.count_encoders, sizeof(uint32_t)); + r->connector_type = conn.connector_type; + r->connector_type_id = conn.connector_type_id; + + if ((r->count_props && !r->props) || + (r->count_props && !r->prop_values) || + (r->count_modes && !r->modes) || + (r->count_encoders && !r->encoders)) { + drmFree(r->props); + drmFree(r->prop_values); + drmFree(r->modes); + drmFree(r->encoders); + drmFree(r); + r = 0; + } + +err_allocs: + drmFree(U642VOID(conn.prop_values_ptr)); + drmFree(U642VOID(conn.props_ptr)); + drmFree(U642VOID(conn.modes_ptr)); + drmFree(U642VOID(conn.encoders_ptr)); + + return r; +} + +int drmModeAttachMode(int fd, uint32_t connector_id, drmModeModeInfoPtr mode_info) +{ + struct drm_mode_mode_cmd res; + + memcpy(&res.mode, mode_info, sizeof(struct drm_mode_modeinfo)); + res.connector_id = connector_id; + + return DRM_IOCTL(fd, DRM_IOCTL_MODE_ATTACHMODE, &res); +} + +int drmModeDetachMode(int fd, uint32_t connector_id, drmModeModeInfoPtr mode_info) +{ + struct drm_mode_mode_cmd res; + + memcpy(&res.mode, mode_info, sizeof(struct drm_mode_modeinfo)); + res.connector_id = connector_id; + + return DRM_IOCTL(fd, DRM_IOCTL_MODE_DETACHMODE, &res); +} + + +drmModePropertyPtr drmModeGetProperty(int fd, uint32_t property_id) +{ + struct drm_mode_get_property prop; + drmModePropertyPtr r; + + prop.prop_id = property_id; + prop.count_enum_blobs = 0; + prop.count_values = 0; + prop.flags = 0; + prop.enum_blob_ptr = 0; + prop.values_ptr = 0; + + if (drmIoctl(fd, DRM_IOCTL_MODE_GETPROPERTY, &prop)) + return 0; + + if (prop.count_values) + prop.values_ptr = VOID2U64(drmMalloc(prop.count_values * sizeof(uint64_t))); + + if (prop.count_enum_blobs && (prop.flags & (DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BITMASK))) + prop.enum_blob_ptr = VOID2U64(drmMalloc(prop.count_enum_blobs * sizeof(struct drm_mode_property_enum))); + + if (prop.count_enum_blobs && (prop.flags & DRM_MODE_PROP_BLOB)) { + prop.values_ptr = VOID2U64(drmMalloc(prop.count_enum_blobs * sizeof(uint32_t))); + prop.enum_blob_ptr = VOID2U64(drmMalloc(prop.count_enum_blobs * sizeof(uint32_t))); + } + + if (drmIoctl(fd, DRM_IOCTL_MODE_GETPROPERTY, &prop)) { + r = NULL; + goto err_allocs; + } + + if (!(r = drmMalloc(sizeof(*r)))) + return NULL; + + r->prop_id = prop.prop_id; + r->count_values = prop.count_values; + + r->flags = prop.flags; + if (prop.count_values) + r->values = drmAllocCpy(U642VOID(prop.values_ptr), prop.count_values, sizeof(uint64_t)); + if (prop.flags & (DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BITMASK)) { + r->count_enums = prop.count_enum_blobs; + r->enums = drmAllocCpy(U642VOID(prop.enum_blob_ptr), prop.count_enum_blobs, sizeof(struct drm_mode_property_enum)); + } else if (prop.flags & DRM_MODE_PROP_BLOB) { + r->values = drmAllocCpy(U642VOID(prop.values_ptr), prop.count_enum_blobs, sizeof(uint32_t)); + r->blob_ids = drmAllocCpy(U642VOID(prop.enum_blob_ptr), prop.count_enum_blobs, sizeof(uint32_t)); + r->count_blobs = prop.count_enum_blobs; + } + strncpy(r->name, prop.name, DRM_PROP_NAME_LEN); + r->name[DRM_PROP_NAME_LEN-1] = 0; + +err_allocs: + drmFree(U642VOID(prop.values_ptr)); + drmFree(U642VOID(prop.enum_blob_ptr)); + + return r; +} + +void drmModeFreeProperty(drmModePropertyPtr ptr) +{ + if (!ptr) + return; + + drmFree(ptr->values); + drmFree(ptr->enums); + drmFree(ptr); +} + +drmModePropertyBlobPtr drmModeGetPropertyBlob(int fd, uint32_t blob_id) +{ + struct drm_mode_get_blob blob; + drmModePropertyBlobPtr r; + + blob.length = 0; + blob.data = 0; + blob.blob_id = blob_id; + + if (drmIoctl(fd, DRM_IOCTL_MODE_GETPROPBLOB, &blob)) + return NULL; + + if (blob.length) + blob.data = VOID2U64(drmMalloc(blob.length)); + + if (drmIoctl(fd, DRM_IOCTL_MODE_GETPROPBLOB, &blob)) { + r = NULL; + goto err_allocs; + } + + if (!(r = drmMalloc(sizeof(*r)))) + goto err_allocs; + + r->id = blob.blob_id; + r->length = blob.length; + r->data = drmAllocCpy(U642VOID(blob.data), 1, blob.length); + +err_allocs: + drmFree(U642VOID(blob.data)); + return r; +} + +void drmModeFreePropertyBlob(drmModePropertyBlobPtr ptr) +{ + if (!ptr) + return; + + drmFree(ptr->data); + drmFree(ptr); +} + +int drmModeConnectorSetProperty(int fd, uint32_t connector_id, uint32_t property_id, + uint64_t value) +{ + struct drm_mode_connector_set_property osp; + + osp.connector_id = connector_id; + osp.prop_id = property_id; + osp.value = value; + + return DRM_IOCTL(fd, DRM_IOCTL_MODE_SETPROPERTY, &osp); +} + +/* + * checks if a modesetting capable driver has attached to the pci id + * returns 0 if modesetting supported. + * -EINVAL or invalid bus id + * -ENOSYS if no modesetting support +*/ +int drmCheckModesettingSupported(const char *busid) +{ +#ifdef __linux__ + char pci_dev_dir[1024]; + int domain, bus, dev, func; + DIR *sysdir; + struct dirent *dent; + int found = 0, ret; + + ret = sscanf(busid, "pci:%04x:%02x:%02x.%d", &domain, &bus, &dev, &func); + if (ret != 4) + return -EINVAL; + + sprintf(pci_dev_dir, "/sys/bus/pci/devices/%04x:%02x:%02x.%d/drm", + domain, bus, dev, func); + + sysdir = opendir(pci_dev_dir); + if (sysdir) { + dent = readdir(sysdir); + while (dent) { + if (!strncmp(dent->d_name, "controlD", 8)) { + found = 1; + break; + } + + dent = readdir(sysdir); + } + closedir(sysdir); + if (found) + return 0; + } + + sprintf(pci_dev_dir, "/sys/bus/pci/devices/%04x:%02x:%02x.%d/", + domain, bus, dev, func); + + sysdir = opendir(pci_dev_dir); + if (!sysdir) + return -EINVAL; + + dent = readdir(sysdir); + while (dent) { + if (!strncmp(dent->d_name, "drm:controlD", 12)) { + found = 1; + break; + } + + dent = readdir(sysdir); + } + + closedir(sysdir); + if (found) + return 0; +#endif + return -ENOSYS; + +} + +int drmModeCrtcGetGamma(int fd, uint32_t crtc_id, uint32_t size, + uint16_t *red, uint16_t *green, uint16_t *blue) +{ + struct drm_mode_crtc_lut l; + + l.crtc_id = crtc_id; + l.gamma_size = size; + l.red = VOID2U64(red); + l.green = VOID2U64(green); + l.blue = VOID2U64(blue); + + return DRM_IOCTL(fd, DRM_IOCTL_MODE_GETGAMMA, &l); +} + +int drmModeCrtcSetGamma(int fd, uint32_t crtc_id, uint32_t size, + uint16_t *red, uint16_t *green, uint16_t *blue) +{ + struct drm_mode_crtc_lut l; + + l.crtc_id = crtc_id; + l.gamma_size = size; + l.red = VOID2U64(red); + l.green = VOID2U64(green); + l.blue = VOID2U64(blue); + + return DRM_IOCTL(fd, DRM_IOCTL_MODE_SETGAMMA, &l); +} + +int drmHandleEvent(int fd, drmEventContextPtr evctx) +{ + char buffer[1024]; + int len, i; + struct drm_event *e; + struct drm_event_vblank *vblank; + + /* The DRM read semantics guarantees that we always get only + * complete events. */ + + len = read(fd, buffer, sizeof buffer); + if (len == 0) + return 0; + if (len < sizeof *e) + return -1; + + i = 0; + while (i < len) { + e = (struct drm_event *) &buffer[i]; + switch (e->type) { + case DRM_EVENT_VBLANK: + if (evctx->version < 1 || + evctx->vblank_handler == NULL) + break; + vblank = (struct drm_event_vblank *) e; + evctx->vblank_handler(fd, + vblank->sequence, + vblank->tv_sec, + vblank->tv_usec, + U642VOID (vblank->user_data)); + break; + case DRM_EVENT_FLIP_COMPLETE: + if (evctx->version < 2 || + evctx->page_flip_handler == NULL) + break; + vblank = (struct drm_event_vblank *) e; + evctx->page_flip_handler(fd, + vblank->sequence, + vblank->tv_sec, + vblank->tv_usec, + U642VOID (vblank->user_data)); + break; + default: + break; + } + i += e->length; + } + + return 0; +} + +int drmModePageFlip(int fd, uint32_t crtc_id, uint32_t fb_id, + uint32_t flags, void *user_data) +{ + struct drm_mode_crtc_page_flip flip; + + flip.fb_id = fb_id; + flip.crtc_id = crtc_id; + flip.user_data = VOID2U64(user_data); + flip.flags = flags; + flip.reserved = 0; + + return DRM_IOCTL(fd, DRM_IOCTL_MODE_PAGE_FLIP, &flip); +} + +int drmModeSetPlane(int fd, uint32_t plane_id, uint32_t crtc_id, + uint32_t fb_id, uint32_t flags, + uint32_t crtc_x, uint32_t crtc_y, + uint32_t crtc_w, uint32_t crtc_h, + uint32_t src_x, uint32_t src_y, + uint32_t src_w, uint32_t src_h) + +{ + struct drm_mode_set_plane s; + + s.plane_id = plane_id; + s.crtc_id = crtc_id; + s.fb_id = fb_id; + s.flags = flags; + s.crtc_x = crtc_x; + s.crtc_y = crtc_y; + s.crtc_w = crtc_w; + s.crtc_h = crtc_h; + s.src_x = src_x; + s.src_y = src_y; + s.src_w = src_w; + s.src_h = src_h; + + return DRM_IOCTL(fd, DRM_IOCTL_MODE_SETPLANE, &s); +} + + +drmModePlanePtr drmModeGetPlane(int fd, uint32_t plane_id) +{ + struct drm_mode_get_plane ovr, counts; + drmModePlanePtr r = 0; + +retry: + memset(&ovr, 0, sizeof(struct drm_mode_get_plane)); + ovr.plane_id = plane_id; + if (drmIoctl(fd, DRM_IOCTL_MODE_GETPLANE, &ovr)) + return 0; + + counts = ovr; + + if (ovr.count_format_types) { + ovr.format_type_ptr = VOID2U64(drmMalloc(ovr.count_format_types * + sizeof(uint32_t))); + if (!ovr.format_type_ptr) + goto err_allocs; + } + + if (drmIoctl(fd, DRM_IOCTL_MODE_GETPLANE, &ovr)) + goto err_allocs; + + if (counts.count_format_types < ovr.count_format_types) { + drmFree(U642VOID(ovr.format_type_ptr)); + goto retry; + } + + if (!(r = drmMalloc(sizeof(*r)))) + goto err_allocs; + + r->count_formats = ovr.count_format_types; + r->plane_id = ovr.plane_id; + r->crtc_id = ovr.crtc_id; + r->fb_id = ovr.fb_id; + r->possible_crtcs = ovr.possible_crtcs; + r->gamma_size = ovr.gamma_size; + r->formats = drmAllocCpy(U642VOID(ovr.format_type_ptr), + ovr.count_format_types, sizeof(uint32_t)); + if (ovr.count_format_types && !r->formats) { + drmFree(r->formats); + drmFree(r); + r = 0; + } + +err_allocs: + drmFree(U642VOID(ovr.format_type_ptr)); + + return r; +} + +void drmModeFreePlane(drmModePlanePtr ptr) +{ + if (!ptr) + return; + + drmFree(ptr->formats); + drmFree(ptr); +} + +drmModePlaneResPtr drmModeGetPlaneResources(int fd) +{ + struct drm_mode_get_plane_res res, counts; + drmModePlaneResPtr r = 0; + +retry: + memset(&res, 0, sizeof(struct drm_mode_get_plane_res)); + if (drmIoctl(fd, DRM_IOCTL_MODE_GETPLANERESOURCES, &res)) + return 0; + + counts = res; + + if (res.count_planes) { + res.plane_id_ptr = VOID2U64(drmMalloc(res.count_planes * + sizeof(uint32_t))); + if (!res.plane_id_ptr) + goto err_allocs; + } + + if (drmIoctl(fd, DRM_IOCTL_MODE_GETPLANERESOURCES, &res)) + goto err_allocs; + + if (counts.count_planes < res.count_planes) { + drmFree(U642VOID(res.plane_id_ptr)); + goto retry; + } + + if (!(r = drmMalloc(sizeof(*r)))) + goto err_allocs; + + r->count_planes = res.count_planes; + r->planes = drmAllocCpy(U642VOID(res.plane_id_ptr), + res.count_planes, sizeof(uint32_t)); + if (res.count_planes && !r->planes) { + drmFree(r->planes); + drmFree(r); + r = 0; + } + +err_allocs: + drmFree(U642VOID(res.plane_id_ptr)); + + return r; +} + +void drmModeFreePlaneResources(drmModePlaneResPtr ptr) +{ + if (!ptr) + return; + + drmFree(ptr->planes); + drmFree(ptr); +} + +drmModeObjectPropertiesPtr drmModeObjectGetProperties(int fd, + uint32_t object_id, + uint32_t object_type) +{ + struct drm_mode_obj_get_properties properties; + drmModeObjectPropertiesPtr ret = NULL; + uint32_t count; + +retry: + memset(&properties, 0, sizeof(struct drm_mode_obj_get_properties)); + properties.obj_id = object_id; + properties.obj_type = object_type; + + if (drmIoctl(fd, DRM_IOCTL_MODE_OBJ_GETPROPERTIES, &properties)) + return 0; + + count = properties.count_props; + + if (count) { + properties.props_ptr = VOID2U64(drmMalloc(count * + sizeof(uint32_t))); + if (!properties.props_ptr) + goto err_allocs; + properties.prop_values_ptr = VOID2U64(drmMalloc(count * + sizeof(uint64_t))); + if (!properties.prop_values_ptr) + goto err_allocs; + } + + if (drmIoctl(fd, DRM_IOCTL_MODE_OBJ_GETPROPERTIES, &properties)) + goto err_allocs; + + if (count < properties.count_props) { + drmFree(U642VOID(properties.props_ptr)); + drmFree(U642VOID(properties.prop_values_ptr)); + goto retry; + } + count = properties.count_props; + + ret = drmMalloc(sizeof(*ret)); + if (!ret) + goto err_allocs; + + ret->count_props = count; + ret->props = drmAllocCpy(U642VOID(properties.props_ptr), + count, sizeof(uint32_t)); + ret->prop_values = drmAllocCpy(U642VOID(properties.prop_values_ptr), + count, sizeof(uint64_t)); + if (ret->count_props && (!ret->props || !ret->prop_values)) { + drmFree(ret->props); + drmFree(ret->prop_values); + drmFree(ret); + ret = NULL; + } + +err_allocs: + drmFree(U642VOID(properties.props_ptr)); + drmFree(U642VOID(properties.prop_values_ptr)); + return ret; +} + +void drmModeFreeObjectProperties(drmModeObjectPropertiesPtr ptr) +{ + if (!ptr) + return; + drmFree(ptr->props); + drmFree(ptr->prop_values); + drmFree(ptr); +} + +int drmModeObjectSetProperty(int fd, uint32_t object_id, uint32_t object_type, + uint32_t property_id, uint64_t value) +{ + struct drm_mode_obj_set_property prop; + + prop.value = value; + prop.prop_id = property_id; + prop.obj_id = object_id; + prop.obj_type = object_type; + + return DRM_IOCTL(fd, DRM_IOCTL_MODE_OBJ_SETPROPERTY, &prop); +} diff --git a/xf86drmMode.h b/xf86drmMode.h new file mode 100644 index 0000000..4f49362 --- /dev/null +++ b/xf86drmMode.h @@ -0,0 +1,451 @@ +/* + * \file xf86drmMode.h + * Header for DRM modesetting interface. + * + * \author Jakob Bornecrantz + * + * \par Acknowledgements: + * Feb 2007, Dave Airlie + */ + +/* + * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, Texas. + * Copyright (c) 2007-2008 Dave Airlie + * Copyright (c) 2007-2008 Jakob Bornecrantz + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#ifndef _XF86DRMMODE_H_ +#define _XF86DRMMODE_H_ + +#if defined(__cplusplus) || defined(c_plusplus) +extern "C" { +#endif + +#include + +/* + * This is the interface for modesetting for drm. + * + * In order to use this interface you must include either or another + * header defining uint32_t, int32_t and uint16_t. + * + * It aims to provide a randr1.2 compatible interface for modesettings in the + * kernel, the interface is also ment to be used by libraries like EGL. + * + * More information can be found in randrproto.txt which can be found here: + * http://gitweb.freedesktop.org/?p=xorg/proto/randrproto.git + * + * There are some major diffrences to be noted. Unlike the randr1.2 proto you + * need to create the memory object of the framebuffer yourself with the ttm + * buffer object interface. This object needs to be pinned. + */ + +/* + * If we pickup an old version of drm.h which doesn't include drm_mode.h + * we should redefine defines. This is so that builds doesn't breaks with + * new libdrm on old kernels. + */ +#ifndef _DRM_MODE_H + +#define DRM_DISPLAY_INFO_LEN 32 +#define DRM_CONNECTOR_NAME_LEN 32 +#define DRM_DISPLAY_MODE_LEN 32 +#define DRM_PROP_NAME_LEN 32 + +#define DRM_MODE_TYPE_BUILTIN (1<<0) +#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) +#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) +#define DRM_MODE_TYPE_PREFERRED (1<<3) +#define DRM_MODE_TYPE_DEFAULT (1<<4) +#define DRM_MODE_TYPE_USERDEF (1<<5) +#define DRM_MODE_TYPE_DRIVER (1<<6) + +/* Video mode flags */ +/* bit compatible with the xorg definitions. */ +#define DRM_MODE_FLAG_PHSYNC (1<<0) +#define DRM_MODE_FLAG_NHSYNC (1<<1) +#define DRM_MODE_FLAG_PVSYNC (1<<2) +#define DRM_MODE_FLAG_NVSYNC (1<<3) +#define DRM_MODE_FLAG_INTERLACE (1<<4) +#define DRM_MODE_FLAG_DBLSCAN (1<<5) +#define DRM_MODE_FLAG_CSYNC (1<<6) +#define DRM_MODE_FLAG_PCSYNC (1<<7) +#define DRM_MODE_FLAG_NCSYNC (1<<8) +#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ +#define DRM_MODE_FLAG_BCAST (1<<10) +#define DRM_MODE_FLAG_PIXMUX (1<<11) +#define DRM_MODE_FLAG_DBLCLK (1<<12) +#define DRM_MODE_FLAG_CLKDIV2 (1<<13) + +/* DPMS flags */ +/* bit compatible with the xorg definitions. */ +#define DRM_MODE_DPMS_ON 0 +#define DRM_MODE_DPMS_STANDBY 1 +#define DRM_MODE_DPMS_SUSPEND 2 +#define DRM_MODE_DPMS_OFF 3 + +/* Scaling mode options */ +#define DRM_MODE_SCALE_NON_GPU 0 +#define DRM_MODE_SCALE_FULLSCREEN 1 +#define DRM_MODE_SCALE_NO_SCALE 2 +#define DRM_MODE_SCALE_ASPECT 3 + +/* Dithering mode options */ +#define DRM_MODE_DITHERING_OFF 0 +#define DRM_MODE_DITHERING_ON 1 + +#define DRM_MODE_ENCODER_NONE 0 +#define DRM_MODE_ENCODER_DAC 1 +#define DRM_MODE_ENCODER_TMDS 2 +#define DRM_MODE_ENCODER_LVDS 3 +#define DRM_MODE_ENCODER_TVDAC 4 +#define DRM_MODE_ENCODER_VIRTUAL 5 + +#define DRM_MODE_SUBCONNECTOR_Automatic 0 +#define DRM_MODE_SUBCONNECTOR_Unknown 0 +#define DRM_MODE_SUBCONNECTOR_DVID 3 +#define DRM_MODE_SUBCONNECTOR_DVIA 4 +#define DRM_MODE_SUBCONNECTOR_Composite 5 +#define DRM_MODE_SUBCONNECTOR_SVIDEO 6 +#define DRM_MODE_SUBCONNECTOR_Component 8 + +#define DRM_MODE_CONNECTOR_Unknown 0 +#define DRM_MODE_CONNECTOR_VGA 1 +#define DRM_MODE_CONNECTOR_DVII 2 +#define DRM_MODE_CONNECTOR_DVID 3 +#define DRM_MODE_CONNECTOR_DVIA 4 +#define DRM_MODE_CONNECTOR_Composite 5 +#define DRM_MODE_CONNECTOR_SVIDEO 6 +#define DRM_MODE_CONNECTOR_LVDS 7 +#define DRM_MODE_CONNECTOR_Component 8 +#define DRM_MODE_CONNECTOR_9PinDIN 9 +#define DRM_MODE_CONNECTOR_DisplayPort 10 +#define DRM_MODE_CONNECTOR_HDMIA 11 +#define DRM_MODE_CONNECTOR_HDMIB 12 +#define DRM_MODE_CONNECTOR_TV 13 +#define DRM_MODE_CONNECTOR_eDP 14 +#define DRM_MODE_CONNECTOR_VIRTUAL 15 + +#define DRM_MODE_PROP_PENDING (1<<0) +#define DRM_MODE_PROP_RANGE (1<<1) +#define DRM_MODE_PROP_IMMUTABLE (1<<2) +#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ +#define DRM_MODE_PROP_BLOB (1<<4) + +#define DRM_MODE_CURSOR_BO (1<<0) +#define DRM_MODE_CURSOR_MOVE (1<<1) + +#endif /* _DRM_MODE_H */ + + +/* + * Feature defines + * + * Just because these are defined doesn't mean that the kernel + * can do that feature, its just for new code vs old libdrm. + */ +#define DRM_MODE_FEATURE_KMS 1 +#define DRM_MODE_FEATURE_DIRTYFB 1 + + +typedef struct _drmModeRes { + + int count_fbs; + uint32_t *fbs; + + int count_crtcs; + uint32_t *crtcs; + + int count_connectors; + uint32_t *connectors; + + int count_encoders; + uint32_t *encoders; + + uint32_t min_width, max_width; + uint32_t min_height, max_height; +} drmModeRes, *drmModeResPtr; + +typedef struct _drmModeModeInfo { + uint32_t clock; + uint16_t hdisplay, hsync_start, hsync_end, htotal, hskew; + uint16_t vdisplay, vsync_start, vsync_end, vtotal, vscan; + + uint32_t vrefresh; + + uint32_t flags; + uint32_t type; + char name[DRM_DISPLAY_MODE_LEN]; +} drmModeModeInfo, *drmModeModeInfoPtr; + +typedef struct _drmModeFB { + uint32_t fb_id; + uint32_t width, height; + uint32_t pitch; + uint32_t bpp; + uint32_t depth; + /* driver specific handle */ + uint32_t handle; +} drmModeFB, *drmModeFBPtr; + +typedef struct drm_clip_rect drmModeClip, *drmModeClipPtr; + +typedef struct _drmModePropertyBlob { + uint32_t id; + uint32_t length; + void *data; +} drmModePropertyBlobRes, *drmModePropertyBlobPtr; + +typedef struct _drmModeProperty { + uint32_t prop_id; + uint32_t flags; + char name[DRM_PROP_NAME_LEN]; + int count_values; + uint64_t *values; // store the blob lengths + int count_enums; + struct drm_mode_property_enum *enums; + int count_blobs; + uint32_t *blob_ids; // store the blob IDs +} drmModePropertyRes, *drmModePropertyPtr; + +typedef struct _drmModeCrtc { + uint32_t crtc_id; + uint32_t buffer_id; /**< FB id to connect to 0 = disconnect */ + + uint32_t x, y; /**< Position on the framebuffer */ + uint32_t width, height; + int mode_valid; + drmModeModeInfo mode; + + int gamma_size; /**< Number of gamma stops */ + +} drmModeCrtc, *drmModeCrtcPtr; + +typedef struct _drmModeEncoder { + uint32_t encoder_id; + uint32_t encoder_type; + uint32_t crtc_id; + uint32_t possible_crtcs; + uint32_t possible_clones; +} drmModeEncoder, *drmModeEncoderPtr; + +typedef enum { + DRM_MODE_CONNECTED = 1, + DRM_MODE_DISCONNECTED = 2, + DRM_MODE_UNKNOWNCONNECTION = 3 +} drmModeConnection; + +typedef enum { + DRM_MODE_SUBPIXEL_UNKNOWN = 1, + DRM_MODE_SUBPIXEL_HORIZONTAL_RGB = 2, + DRM_MODE_SUBPIXEL_HORIZONTAL_BGR = 3, + DRM_MODE_SUBPIXEL_VERTICAL_RGB = 4, + DRM_MODE_SUBPIXEL_VERTICAL_BGR = 5, + DRM_MODE_SUBPIXEL_NONE = 6 +} drmModeSubPixel; + +typedef struct _drmModeConnector { + uint32_t connector_id; + uint32_t encoder_id; /**< Encoder currently connected to */ + uint32_t connector_type; + uint32_t connector_type_id; + drmModeConnection connection; + uint32_t mmWidth, mmHeight; /**< HxW in millimeters */ + drmModeSubPixel subpixel; + + int count_modes; + drmModeModeInfoPtr modes; + + int count_props; + uint32_t *props; /**< List of property ids */ + uint64_t *prop_values; /**< List of property values */ + + int count_encoders; + uint32_t *encoders; /**< List of encoder ids */ +} drmModeConnector, *drmModeConnectorPtr; + +typedef struct _drmModeObjectProperties { + uint32_t count_props; + uint32_t *props; + uint64_t *prop_values; +} drmModeObjectProperties, *drmModeObjectPropertiesPtr; + +typedef struct _drmModePlane { + uint32_t count_formats; + uint32_t *formats; + uint32_t plane_id; + + uint32_t crtc_id; + uint32_t fb_id; + + uint32_t crtc_x, crtc_y; + uint32_t x, y; + + uint32_t possible_crtcs; + uint32_t gamma_size; +} drmModePlane, *drmModePlanePtr; + +typedef struct _drmModePlaneRes { + uint32_t count_planes; + uint32_t *planes; +} drmModePlaneRes, *drmModePlaneResPtr; + +extern void drmModeFreeModeInfo( drmModeModeInfoPtr ptr ); +extern void drmModeFreeResources( drmModeResPtr ptr ); +extern void drmModeFreeFB( drmModeFBPtr ptr ); +extern void drmModeFreeCrtc( drmModeCrtcPtr ptr ); +extern void drmModeFreeConnector( drmModeConnectorPtr ptr ); +extern void drmModeFreeEncoder( drmModeEncoderPtr ptr ); +extern void drmModeFreePlane( drmModePlanePtr ptr ); +extern void drmModeFreePlaneResources(drmModePlaneResPtr ptr); + +/** + * Retrives all of the resources associated with a card. + */ +extern drmModeResPtr drmModeGetResources(int fd); + +/* + * FrameBuffer manipulation. + */ + +/** + * Retrive information about framebuffer bufferId + */ +extern drmModeFBPtr drmModeGetFB(int fd, uint32_t bufferId); + +/** + * Creates a new framebuffer with an buffer object as its scanout buffer. + */ +extern int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth, + uint8_t bpp, uint32_t pitch, uint32_t bo_handle, + uint32_t *buf_id); +/* ...with a specific pixel format */ +extern int drmModeAddFB2(int fd, uint32_t width, uint32_t height, + uint32_t pixel_format, uint32_t bo_handles[4], + uint32_t pitches[4], uint32_t offsets[4], + uint32_t *buf_id, uint32_t flags); +/** + * Destroies the given framebuffer. + */ +extern int drmModeRmFB(int fd, uint32_t bufferId); + +/** + * Mark a region of a framebuffer as dirty. + */ +extern int drmModeDirtyFB(int fd, uint32_t bufferId, + drmModeClipPtr clips, uint32_t num_clips); + + +/* + * Crtc functions + */ + +/** + * Retrive information about the ctrt crtcId + */ +extern drmModeCrtcPtr drmModeGetCrtc(int fd, uint32_t crtcId); + +/** + * Set the mode on a crtc crtcId with the given mode modeId. + */ +int drmModeSetCrtc(int fd, uint32_t crtcId, uint32_t bufferId, + uint32_t x, uint32_t y, uint32_t *connectors, int count, + drmModeModeInfoPtr mode); + +/* + * Cursor functions + */ + +/** + * Set the cursor on crtc + */ +int drmModeSetCursor(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width, uint32_t height); + +/** + * Move the cursor on crtc + */ +int drmModeMoveCursor(int fd, uint32_t crtcId, int x, int y); + +/** + * Encoder functions + */ +drmModeEncoderPtr drmModeGetEncoder(int fd, uint32_t encoder_id); + +/* + * Connector manipulation + */ + +/** + * Retrive information about the connector connectorId. + */ +extern drmModeConnectorPtr drmModeGetConnector(int fd, + uint32_t connectorId); + +/** + * Attaches the given mode to an connector. + */ +extern int drmModeAttachMode(int fd, uint32_t connectorId, drmModeModeInfoPtr mode_info); + +/** + * Detaches a mode from the connector + * must be unused, by the given mode. + */ +extern int drmModeDetachMode(int fd, uint32_t connectorId, drmModeModeInfoPtr mode_info); + +extern drmModePropertyPtr drmModeGetProperty(int fd, uint32_t propertyId); +extern void drmModeFreeProperty(drmModePropertyPtr ptr); + +extern drmModePropertyBlobPtr drmModeGetPropertyBlob(int fd, uint32_t blob_id); +extern void drmModeFreePropertyBlob(drmModePropertyBlobPtr ptr); +extern int drmModeConnectorSetProperty(int fd, uint32_t connector_id, uint32_t property_id, + uint64_t value); +extern int drmCheckModesettingSupported(const char *busid); + +extern int drmModeCrtcSetGamma(int fd, uint32_t crtc_id, uint32_t size, + uint16_t *red, uint16_t *green, uint16_t *blue); +extern int drmModeCrtcGetGamma(int fd, uint32_t crtc_id, uint32_t size, + uint16_t *red, uint16_t *green, uint16_t *blue); +extern int drmModePageFlip(int fd, uint32_t crtc_id, uint32_t fb_id, + uint32_t flags, void *user_data); + +extern drmModePlaneResPtr drmModeGetPlaneResources(int fd); +extern drmModePlanePtr drmModeGetPlane(int fd, uint32_t plane_id); +extern int drmModeSetPlane(int fd, uint32_t plane_id, uint32_t crtc_id, + uint32_t fb_id, uint32_t flags, + uint32_t crtc_x, uint32_t crtc_y, + uint32_t crtc_w, uint32_t crtc_h, + uint32_t src_x, uint32_t src_y, + uint32_t src_w, uint32_t src_h); + +extern drmModeObjectPropertiesPtr drmModeObjectGetProperties(int fd, + uint32_t object_id, + uint32_t object_type); +extern void drmModeFreeObjectProperties(drmModeObjectPropertiesPtr ptr); +extern int drmModeObjectSetProperty(int fd, uint32_t object_id, + uint32_t object_type, uint32_t property_id, + uint64_t value); + +#if defined(__cplusplus) || defined(c_plusplus) +} +#endif + +#endif diff --git a/xf86drmRandom.c b/xf86drmRandom.c new file mode 100644 index 0000000..ecab9e2 --- /dev/null +++ b/xf86drmRandom.c @@ -0,0 +1,208 @@ +/* xf86drmRandom.c -- "Minimal Standard" PRNG Implementation + * Created: Mon Apr 19 08:28:13 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * + * DESCRIPTION + * + * This file contains a simple, straightforward implementation of the Park + * & Miller "Minimal Standard" PRNG [PM88, PMS93], which is a Lehmer + * multiplicative linear congruential generator (MLCG) with a period of + * 2^31-1. + * + * This implementation is intended to provide a reliable, portable PRNG + * that is suitable for testing a hash table implementation and for + * implementing skip lists. + * + * FUTURE ENHANCEMENTS + * + * If initial seeds are not selected randomly, two instances of the PRNG + * can be correlated. [Knuth81, pp. 32-33] describes a shuffling technique + * that can eliminate this problem. + * + * If PRNGs are used for simulation, the period of the current + * implementation may be too short. [LE88] discusses methods of combining + * MLCGs to produce much longer periods, and suggests some alternative + * values for A and M. [LE90 and Sch92] also provide information on + * long-period PRNGs. + * + * REFERENCES + * + * [Knuth81] Donald E. Knuth. The Art of Computer Programming. Volume 2: + * Seminumerical Algorithms. Reading, Massachusetts: Addison-Wesley, 1981. + * + * [LE88] Pierre L'Ecuyer. "Efficient and Portable Combined Random Number + * Generators". CACM 31(6), June 1988, pp. 742-774. + * + * [LE90] Pierre L'Ecuyer. "Random Numbers for Simulation". CACM 33(10, + * October 1990, pp. 85-97. + * + * [PM88] Stephen K. Park and Keith W. Miller. "Random Number Generators: + * Good Ones are Hard to Find". CACM 31(10), October 1988, pp. 1192-1201. + * + * [Sch92] Bruce Schneier. "Pseudo-Ransom Sequence Generator for 32-Bit + * CPUs". Dr. Dobb's Journal 17(2), February 1992, pp. 34, 37-38, 40. + * + * [PMS93] Stephen K. Park, Keith W. Miller, and Paul K. Stockmeyer. In + * "Technical Correspondence: Remarks on Choosing and Implementing Random + * Number Generators". CACM 36(7), July 1993, pp. 105-110. + * + */ + +#include +#include + +#define RANDOM_MAIN 0 + +#if !RANDOM_MAIN +# include "xf86drm.h" +#endif + +#define RANDOM_MAGIC 0xfeedbeef +#define RANDOM_DEBUG 0 + +#if RANDOM_MAIN +#define RANDOM_ALLOC malloc +#define RANDOM_FREE free +#else +#define RANDOM_ALLOC drmMalloc +#define RANDOM_FREE drmFree +#endif + +typedef struct RandomState { + unsigned long magic; + unsigned long a; + unsigned long m; + unsigned long q; /* m div a */ + unsigned long r; /* m mod a */ + unsigned long check; + long seed; +} RandomState; + +#if RANDOM_MAIN +extern void *drmRandomCreate(unsigned long seed); +extern int drmRandomDestroy(void *state); +extern unsigned long drmRandom(void *state); +extern double drmRandomDouble(void *state); +#endif + +void *drmRandomCreate(unsigned long seed) +{ + RandomState *state; + + state = RANDOM_ALLOC(sizeof(*state)); + if (!state) return NULL; + state->magic = RANDOM_MAGIC; +#if 0 + /* Park & Miller, October 1988 */ + state->a = 16807; + state->m = 2147483647; + state->check = 1043618065; /* After 10000 iterations */ +#else + /* Park, Miller, and Stockmeyer, July 1993 */ + state->a = 48271; + state->m = 2147483647; + state->check = 399268537; /* After 10000 iterations */ +#endif + state->q = state->m / state->a; + state->r = state->m % state->a; + + state->seed = seed; + /* Check for illegal boundary conditions, + and choose closest legal value. */ + if (state->seed <= 0) state->seed = 1; + if (state->seed >= state->m) state->seed = state->m - 1; + + return state; +} + +int drmRandomDestroy(void *state) +{ + RANDOM_FREE(state); + return 0; +} + +unsigned long drmRandom(void *state) +{ + RandomState *s = (RandomState *)state; + long hi; + long lo; + + hi = s->seed / s->q; + lo = s->seed % s->q; + s->seed = s->a * lo - s->r * hi; + if (s->seed <= 0) s->seed += s->m; + + return s->seed; +} + +double drmRandomDouble(void *state) +{ + RandomState *s = (RandomState *)state; + + return (double)drmRandom(state)/(double)s->m; +} + +#if RANDOM_MAIN +static void check_period(long seed) +{ + unsigned long count = 0; + unsigned long initial; + void *state; + + state = drmRandomCreate(seed); + initial = drmRandom(state); + ++count; + while (initial != drmRandom(state)) { + if (!++count) break; + } + printf("With seed of %10ld, period = %10lu (0x%08lx)\n", + seed, count, count); + drmRandomDestroy(state); +} + +int main(void) +{ + RandomState *state; + int i; + unsigned long rand; + + state = drmRandomCreate(1); + for (i = 0; i < 10000; i++) { + rand = drmRandom(state); + } + printf("After 10000 iterations: %lu (%lu expected): %s\n", + rand, state->check, + rand - state->check ? "*INCORRECT*" : "CORRECT"); + drmRandomDestroy(state); + + printf("Checking periods...\n"); + check_period(1); + check_period(2); + check_period(31415926); + + return 0; +} +#endif diff --git a/xf86drmSL.c b/xf86drmSL.c new file mode 100644 index 0000000..1937507 --- /dev/null +++ b/xf86drmSL.c @@ -0,0 +1,477 @@ +/* xf86drmSL.c -- Skip list support + * Created: Mon May 10 09:28:13 1999 by faith@precisioninsight.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: Rickard E. (Rik) Faith + * + * DESCRIPTION + * + * This file contains a straightforward skip list implementation.n + * + * FUTURE ENHANCEMENTS + * + * REFERENCES + * + * [Pugh90] William Pugh. Skip Lists: A Probabilistic Alternative to + * Balanced Trees. CACM 33(6), June 1990, pp. 668-676. + * + */ + +#include +#include + +#define SL_MAIN 0 + +#if !SL_MAIN +# include "xf86drm.h" +#else +# include +#endif + +#define SL_LIST_MAGIC 0xfacade00LU +#define SL_ENTRY_MAGIC 0x00fab1edLU +#define SL_FREED_MAGIC 0xdecea5edLU +#define SL_MAX_LEVEL 16 +#define SL_DEBUG 0 +#define SL_RANDOM_SEED 0xc01055a1LU + +#if SL_MAIN +#define SL_ALLOC malloc +#define SL_FREE free +#define SL_RANDOM_DECL static int state = 0; +#define SL_RANDOM_INIT(seed) if (!state) { srandom(seed); ++state; } +#define SL_RANDOM random() +#else +#define SL_ALLOC drmMalloc +#define SL_FREE drmFree +#define SL_RANDOM_DECL static void *state = NULL +#define SL_RANDOM_INIT(seed) if (!state) state = drmRandomCreate(seed) +#define SL_RANDOM drmRandom(state) + +#endif + +typedef struct SLEntry { + unsigned long magic; /* SL_ENTRY_MAGIC */ + unsigned long key; + void *value; + int levels; + struct SLEntry *forward[1]; /* variable sized array */ +} SLEntry, *SLEntryPtr; + +typedef struct SkipList { + unsigned long magic; /* SL_LIST_MAGIC */ + int level; + int count; + SLEntryPtr head; + SLEntryPtr p0; /* Position for iteration */ +} SkipList, *SkipListPtr; + +#if SL_MAIN +extern void *drmSLCreate(void); +extern int drmSLDestroy(void *l); +extern int drmSLLookup(void *l, unsigned long key, void **value); +extern int drmSLInsert(void *l, unsigned long key, void *value); +extern int drmSLDelete(void *l, unsigned long key); +extern int drmSLNext(void *l, unsigned long *key, void **value); +extern int drmSLFirst(void *l, unsigned long *key, void **value); +extern void drmSLDump(void *l); +extern int drmSLLookupNeighbors(void *l, unsigned long key, + unsigned long *prev_key, void **prev_value, + unsigned long *next_key, void **next_value); +#endif + +static SLEntryPtr SLCreateEntry(int max_level, unsigned long key, void *value) +{ + SLEntryPtr entry; + + if (max_level < 0 || max_level > SL_MAX_LEVEL) max_level = SL_MAX_LEVEL; + + entry = SL_ALLOC(sizeof(*entry) + + (max_level + 1) * sizeof(entry->forward[0])); + if (!entry) return NULL; + entry->magic = SL_ENTRY_MAGIC; + entry->key = key; + entry->value = value; + entry->levels = max_level + 1; + + return entry; +} + +static int SLRandomLevel(void) +{ + int level = 1; + SL_RANDOM_DECL; + + SL_RANDOM_INIT(SL_RANDOM_SEED); + + while ((SL_RANDOM & 0x01) && level < SL_MAX_LEVEL) ++level; + return level; +} + +void *drmSLCreate(void) +{ + SkipListPtr list; + int i; + + list = SL_ALLOC(sizeof(*list)); + if (!list) return NULL; + list->magic = SL_LIST_MAGIC; + list->level = 0; + list->head = SLCreateEntry(SL_MAX_LEVEL, 0, NULL); + list->count = 0; + + for (i = 0; i <= SL_MAX_LEVEL; i++) list->head->forward[i] = NULL; + + return list; +} + +int drmSLDestroy(void *l) +{ + SkipListPtr list = (SkipListPtr)l; + SLEntryPtr entry; + SLEntryPtr next; + + if (list->magic != SL_LIST_MAGIC) return -1; /* Bad magic */ + + for (entry = list->head; entry; entry = next) { + if (entry->magic != SL_ENTRY_MAGIC) return -1; /* Bad magic */ + next = entry->forward[0]; + entry->magic = SL_FREED_MAGIC; + SL_FREE(entry); + } + + list->magic = SL_FREED_MAGIC; + SL_FREE(list); + return 0; +} + +static SLEntryPtr SLLocate(void *l, unsigned long key, SLEntryPtr *update) +{ + SkipListPtr list = (SkipListPtr)l; + SLEntryPtr entry; + int i; + + if (list->magic != SL_LIST_MAGIC) return NULL; + + for (i = list->level, entry = list->head; i >= 0; i--) { + while (entry->forward[i] && entry->forward[i]->key < key) + entry = entry->forward[i]; + update[i] = entry; + } + + return entry->forward[0]; +} + +int drmSLInsert(void *l, unsigned long key, void *value) +{ + SkipListPtr list = (SkipListPtr)l; + SLEntryPtr entry; + SLEntryPtr update[SL_MAX_LEVEL + 1]; + int level; + int i; + + if (list->magic != SL_LIST_MAGIC) return -1; /* Bad magic */ + + entry = SLLocate(list, key, update); + + if (entry && entry->key == key) return 1; /* Already in list */ + + + level = SLRandomLevel(); + if (level > list->level) { + level = ++list->level; + update[level] = list->head; + } + + entry = SLCreateEntry(level, key, value); + + /* Fix up forward pointers */ + for (i = 0; i <= level; i++) { + entry->forward[i] = update[i]->forward[i]; + update[i]->forward[i] = entry; + } + + ++list->count; + return 0; /* Added to table */ +} + +int drmSLDelete(void *l, unsigned long key) +{ + SkipListPtr list = (SkipListPtr)l; + SLEntryPtr update[SL_MAX_LEVEL + 1]; + SLEntryPtr entry; + int i; + + if (list->magic != SL_LIST_MAGIC) return -1; /* Bad magic */ + + entry = SLLocate(list, key, update); + + if (!entry || entry->key != key) return 1; /* Not found */ + + /* Fix up forward pointers */ + for (i = 0; i <= list->level; i++) { + if (update[i]->forward[i] == entry) + update[i]->forward[i] = entry->forward[i]; + } + + entry->magic = SL_FREED_MAGIC; + SL_FREE(entry); + + while (list->level && !list->head->forward[list->level]) --list->level; + --list->count; + return 0; +} + +int drmSLLookup(void *l, unsigned long key, void **value) +{ + SkipListPtr list = (SkipListPtr)l; + SLEntryPtr update[SL_MAX_LEVEL + 1]; + SLEntryPtr entry; + + entry = SLLocate(list, key, update); + + if (entry && entry->key == key) { + *value = entry->value; + return 0; + } + *value = NULL; + return -1; +} + +int drmSLLookupNeighbors(void *l, unsigned long key, + unsigned long *prev_key, void **prev_value, + unsigned long *next_key, void **next_value) +{ + SkipListPtr list = (SkipListPtr)l; + SLEntryPtr update[SL_MAX_LEVEL + 1]; + int retcode = 0; + + *prev_key = *next_key = key; + *prev_value = *next_value = NULL; + + if (update[0]) { + *prev_key = update[0]->key; + *prev_value = update[0]->value; + ++retcode; + if (update[0]->forward[0]) { + *next_key = update[0]->forward[0]->key; + *next_value = update[0]->forward[0]->value; + ++retcode; + } + } + return retcode; +} + +int drmSLNext(void *l, unsigned long *key, void **value) +{ + SkipListPtr list = (SkipListPtr)l; + SLEntryPtr entry; + + if (list->magic != SL_LIST_MAGIC) return -1; /* Bad magic */ + + entry = list->p0; + + if (entry) { + list->p0 = entry->forward[0]; + *key = entry->key; + *value = entry->value; + return 1; + } + list->p0 = NULL; + return 0; +} + +int drmSLFirst(void *l, unsigned long *key, void **value) +{ + SkipListPtr list = (SkipListPtr)l; + + if (list->magic != SL_LIST_MAGIC) return -1; /* Bad magic */ + + list->p0 = list->head->forward[0]; + return drmSLNext(list, key, value); +} + +/* Dump internal data structures for debugging. */ +void drmSLDump(void *l) +{ + SkipListPtr list = (SkipListPtr)l; + SLEntryPtr entry; + int i; + + if (list->magic != SL_LIST_MAGIC) { + printf("Bad magic: 0x%08lx (expected 0x%08lx)\n", + list->magic, SL_LIST_MAGIC); + return; + } + + printf("Level = %d, count = %d\n", list->level, list->count); + for (entry = list->head; entry; entry = entry->forward[0]) { + if (entry->magic != SL_ENTRY_MAGIC) { + printf("Bad magic: 0x%08lx (expected 0x%08lx)\n", + list->magic, SL_ENTRY_MAGIC); + } + printf("\nEntry %p <0x%08lx, %p> has %2d levels\n", + entry, entry->key, entry->value, entry->levels); + for (i = 0; i < entry->levels; i++) { + if (entry->forward[i]) { + printf(" %2d: %p <0x%08lx, %p>\n", + i, + entry->forward[i], + entry->forward[i]->key, + entry->forward[i]->value); + } else { + printf(" %2d: %p\n", i, entry->forward[i]); + } + } + } +} + +#if SL_MAIN +static void print(SkipListPtr list) +{ + unsigned long key; + void *value; + + if (drmSLFirst(list, &key, &value)) { + do { + printf("key = %5lu, value = %p\n", key, value); + } while (drmSLNext(list, &key, &value)); + } +} + +static double do_time(int size, int iter) +{ + SkipListPtr list; + int i, j; + unsigned long keys[1000000]; + unsigned long previous; + unsigned long key; + void *value; + struct timeval start, stop; + double usec; + SL_RANDOM_DECL; + + SL_RANDOM_INIT(12345); + + list = drmSLCreate(); + + for (i = 0; i < size; i++) { + keys[i] = SL_RANDOM; + drmSLInsert(list, keys[i], NULL); + } + + previous = 0; + if (drmSLFirst(list, &key, &value)) { + do { + if (key <= previous) { + printf( "%lu !< %lu\n", previous, key); + } + previous = key; + } while (drmSLNext(list, &key, &value)); + } + + gettimeofday(&start, NULL); + for (j = 0; j < iter; j++) { + for (i = 0; i < size; i++) { + if (drmSLLookup(list, keys[i], &value)) + printf("Error %lu %d\n", keys[i], i); + } + } + gettimeofday(&stop, NULL); + + usec = (double)(stop.tv_sec * 1000000 + stop.tv_usec + - start.tv_sec * 1000000 - start.tv_usec) / (size * iter); + + printf("%0.2f microseconds for list length %d\n", usec, size); + + drmSLDestroy(list); + + return usec; +} + +static void print_neighbors(void *list, unsigned long key) +{ + unsigned long prev_key = 0; + unsigned long next_key = 0; + void *prev_value; + void *next_value; + int retval; + + retval = drmSLLookupNeighbors(list, key, + &prev_key, &prev_value, + &next_key, &next_value); + printf("Neighbors of %5lu: %d %5lu %5lu\n", + key, retval, prev_key, next_key); +} + +int main(void) +{ + SkipListPtr list; + double usec, usec2, usec3, usec4; + + list = drmSLCreate(); + printf( "list at %p\n", list); + + print(list); + printf("\n==============================\n\n"); + + drmSLInsert(list, 123, NULL); + drmSLInsert(list, 213, NULL); + drmSLInsert(list, 50, NULL); + print(list); + printf("\n==============================\n\n"); + + print_neighbors(list, 0); + print_neighbors(list, 50); + print_neighbors(list, 51); + print_neighbors(list, 123); + print_neighbors(list, 200); + print_neighbors(list, 213); + print_neighbors(list, 256); + printf("\n==============================\n\n"); + + drmSLDelete(list, 50); + print(list); + printf("\n==============================\n\n"); + + drmSLDump(list); + drmSLDestroy(list); + printf("\n==============================\n\n"); + + usec = do_time(100, 10000); + usec2 = do_time(1000, 500); + printf("Table size increased by %0.2f, search time increased by %0.2f\n", + 1000.0/100.0, usec2 / usec); + + usec3 = do_time(10000, 50); + printf("Table size increased by %0.2f, search time increased by %0.2f\n", + 10000.0/100.0, usec3 / usec); + + usec4 = do_time(100000, 4); + printf("Table size increased by %0.2f, search time increased by %0.2f\n", + 100000.0/100.0, usec4 / usec); + + return 0; +} +#endif diff --git a/xf86mm.h b/xf86mm.h new file mode 100644 index 0000000..a31de42 --- /dev/null +++ b/xf86mm.h @@ -0,0 +1,198 @@ +/************************************************************************** + * + * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND. USA. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * + **************************************************************************/ + +#ifndef _XF86MM_H_ +#define _XF86MM_H_ +#include +#include +#include "drm.h" + +/* + * Note on multithreaded applications using this interface. + * Libdrm is not threadsafe, so common buffer, TTM, and fence objects need to + * be protected using an external mutex. + * + * Note: Don't protect the following functions, as it may lead to deadlocks: + * drmBOUnmap(). + * The kernel is synchronizing and refcounting buffer maps. + * User space only needs to refcount object usage within the same application. + */ + + +/* + * List macros heavily inspired by the Linux kernel + * list handling. No list looping yet. + */ + +typedef struct _drmMMListHead +{ + struct _drmMMListHead *prev; + struct _drmMMListHead *next; +} drmMMListHead; + +#define DRMINITLISTHEAD(__item) \ + do{ \ + (__item)->prev = (__item); \ + (__item)->next = (__item); \ + } while (0) + +#define DRMLISTADD(__item, __list) \ + do { \ + (__item)->prev = (__list); \ + (__item)->next = (__list)->next; \ + (__list)->next->prev = (__item); \ + (__list)->next = (__item); \ + } while (0) + +#define DRMLISTADDTAIL(__item, __list) \ + do { \ + (__item)->next = (__list); \ + (__item)->prev = (__list)->prev; \ + (__list)->prev->next = (__item); \ + (__list)->prev = (__item); \ + } while(0) + +#define DRMLISTDEL(__item) \ + do { \ + (__item)->prev->next = (__item)->next; \ + (__item)->next->prev = (__item)->prev; \ + } while(0) + +#define DRMLISTDELINIT(__item) \ + do { \ + (__item)->prev->next = (__item)->next; \ + (__item)->next->prev = (__item)->prev; \ + (__item)->next = (__item); \ + (__item)->prev = (__item); \ + } while(0) + +#define DRMLISTENTRY(__type, __item, __field) \ + ((__type *)(((char *) (__item)) - offsetof(__type, __field))) + +#define DRMLISTEMPTY(__item) ((__item)->next == (__item)) + +#define DRMLISTFOREACHSAFE(__item, __temp, __list) \ + for ((__item) = (__list)->next, (__temp) = (__item)->next; \ + (__item) != (__list); \ + (__item) = (__temp), (__temp) = (__item)->next) + +#define DRMLISTFOREACHSAFEREVERSE(__item, __temp, __list) \ + for ((__item) = (__list)->prev, (__temp) = (__item)->prev; \ + (__item) != (__list); \ + (__item) = (__temp), (__temp) = (__item)->prev) + +typedef struct _drmFence +{ + unsigned handle; + int fence_class; + unsigned type; + unsigned flags; + unsigned signaled; + uint32_t sequence; + unsigned pad[4]; /* for future expansion */ +} drmFence; + +typedef struct _drmBO +{ + unsigned handle; + uint64_t mapHandle; + uint64_t flags; + uint64_t proposedFlags; + unsigned mapFlags; + unsigned long size; + unsigned long offset; + unsigned long start; + unsigned replyFlags; + unsigned fenceFlags; + unsigned pageAlignment; + unsigned tileInfo; + unsigned hwTileStride; + unsigned desiredTileStride; + void *virtual; + void *mapVirtual; + int mapCount; + unsigned pad[8]; /* for future expansion */ +} drmBO; + +/* + * Fence functions. + */ + +extern int drmFenceCreate(int fd, unsigned flags, int fence_class, + unsigned type, drmFence *fence); +extern int drmFenceReference(int fd, unsigned handle, drmFence *fence); +extern int drmFenceUnreference(int fd, const drmFence *fence); +extern int drmFenceFlush(int fd, drmFence *fence, unsigned flush_type); +extern int drmFenceSignaled(int fd, drmFence *fence, + unsigned fenceType, int *signaled); +extern int drmFenceWait(int fd, unsigned flags, drmFence *fence, + unsigned flush_type); +extern int drmFenceEmit(int fd, unsigned flags, drmFence *fence, + unsigned emit_type); +extern int drmFenceBuffers(int fd, unsigned flags, uint32_t fence_class, drmFence *fence); + + +/* + * Buffer object functions. + */ + +extern int drmBOCreate(int fd, unsigned long size, + unsigned pageAlignment, void *user_buffer, + uint64_t mask, unsigned hint, drmBO *buf); +extern int drmBOReference(int fd, unsigned handle, drmBO *buf); +extern int drmBOUnreference(int fd, drmBO *buf); +extern int drmBOMap(int fd, drmBO *buf, unsigned mapFlags, unsigned mapHint, + void **address); +extern int drmBOUnmap(int fd, drmBO *buf); +extern int drmBOFence(int fd, drmBO *buf, unsigned flags, unsigned fenceHandle); +extern int drmBOInfo(int fd, drmBO *buf); +extern int drmBOBusy(int fd, drmBO *buf, int *busy); + +extern int drmBOWaitIdle(int fd, drmBO *buf, unsigned hint); + +/* + * Initialization functions. + */ + +extern int drmMMInit(int fd, unsigned long pOffset, unsigned long pSize, + unsigned memType); +extern int drmMMTakedown(int fd, unsigned memType); +extern int drmMMLock(int fd, unsigned memType, int lockBM, int ignoreNoEvict); +extern int drmMMUnlock(int fd, unsigned memType, int unlockBM); +extern int drmMMInfo(int fd, unsigned memType, uint64_t *size); +extern int drmBOSetStatus(int fd, drmBO *buf, + uint64_t flags, uint64_t mask, + unsigned int hint, + unsigned int desired_tile_stride, + unsigned int tile_info); +extern int drmBOVersion(int fd, unsigned int *major, + unsigned int *minor, + unsigned int *patchlevel); + + +#endif -- 2.7.4