From ab68d10eb2a9913da149e5e516185f9e146cea56 Mon Sep 17 00:00:00 2001 From: "Xiang, Haihao" Date: Fri, 22 Apr 2011 10:20:59 +0800 Subject: [PATCH] i965_drv_video/encode: merge global symbols in intra/inter shader Signed-off-by: Xiang, Haihao --- i965_drv_video/shaders/vme/Makefile.am | 6 +- i965_drv_video/shaders/vme/inter_frame.asm | 112 ----------------------------- i965_drv_video/shaders/vme/intra_frame.asm | 93 +----------------------- i965_drv_video/shaders/vme/intra_frame.g6b | 10 +-- i965_drv_video/shaders/vme/vme_header.inc | 111 ++++++++++++++++++++++++++++ 5 files changed, 123 insertions(+), 209 deletions(-) diff --git a/i965_drv_video/shaders/vme/Makefile.am b/i965_drv_video/shaders/vme/Makefile.am index 7945d66..2a8175f 100644 --- a/i965_drv_video/shaders/vme/Makefile.am +++ b/i965_drv_video/shaders/vme/Makefile.am @@ -1,6 +1,8 @@ INTEL_G6B = intra_frame.g6b inter_frame.g6b +INTEL_INC = vme_header.inc -EXTRA_DIST = $(INTEL_G6B) +EXTRA_DIST = $(INTEL_G6B) \ + $(INTEL_INC) if HAVE_GEN4ASM @@ -8,6 +10,8 @@ SUFFIXES = .asm .g6b .asm.g6b: m4 $*.asm > $*.g6m && intel-gen4asm -g 6 -o $@ $*.g6m && rm $*.g6m +$(INTEL_G6B): $(INTEL_INC) + BUILT_SOURCES= $(INTEL_G6B) clean-local: diff --git a/i965_drv_video/shaders/vme/inter_frame.asm b/i965_drv_video/shaders/vme/inter_frame.asm index e374ea8..d589344 100644 --- a/i965_drv_video/shaders/vme/inter_frame.asm +++ b/i965_drv_video/shaders/vme/inter_frame.asm @@ -18,118 +18,6 @@ include(`vme_header.inc') /* - * Constant - */ -define(`VME_MESSAGE_TYPE_INTER', `1') -define(`VME_MESSAGE_TYPE_INTRA', `2') -define(`VME_MESSAGE_TYPE_MIXED', `3') - -define(`BLOCK_32X1', `0x0000001F') -define(`BLOCK_4X16', `0x000F0003') - -define(`LUMA_INTRA_16x16_DISABLE', `0x1') -define(`LUMA_INTRA_8x8_DISABLE', `0x2') -define(`LUMA_INTRA_4x4_DISABLE', `0x4') - -define(`INTRA_PRED_AVAIL_FLAG_AE', `0x60') -define(`INTRA_PRED_AVAIL_FLAG_B', `0x10') -define(`INTRA_PRED_AVAIL_FLAG_C', `0x8') -define(`INTRA_PRED_AVAIL_FLAG_D', `0x4') - -define(`BIND_IDX_VME', `0') -define(`BIND_IDX_VME_REF0', `1') -define(`BIND_IDX_VME_REF1', `2') -define(`BIND_IDX_OUTPUT', `3') -define(`BIND_IDX_INEP', `4') - -define(`SUB_PEL_MODE_INTEGER', `0x00000000') -define(`SUB_PEL_MODE_HALF', `0x00001000') -define(`SUB_PEL_MODE_QUARTER', `0x00003000') - -define(`INTER_SAD_NONE', `0x00000000') -define(`INTER_SAD_HAAR', `0x00200000') - -define(`INTRA_SAD_NONE', `0x00000000') -define(`INTRA_SAD_HAAR', `0x00800000') - -define(`REF_REGION_SIZE', `0x2020:UW') - -define(`BI_SUB_MB_PART_MASK', `0x0c000000') -define(`MAX_NUM_MV', `0x00000020') - -define(`INTRA_PREDICTORE_MODE', `0x11111111:UD') - -/* GRF registers - * r0 header - * r1~r4 constant buffer (reserved) - * r5 inline data - * r6~r11 reserved - * r12 write back of VME message - * r13 write back of Oword Block Write - */ -/* - * GRF 0 -- header - */ -define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ - -/* - * GRF 1~4 -- Constant Buffer (reserved) - */ - -/* - * GRF 5 -- inline data - */ -define(`inline_reg0', `r5') -define(`w_in_mb_uw', `inline_reg0.2') -define(`orig_xy_ub', `inline_reg0.0') -define(`orig_x_ub', `inline_reg0.0') /* in macroblock */ -define(`orig_y_ub', `inline_reg0.1') - -/* - * GRF 6~11 -- reserved - */ - -/* - * GRF 12~15 -- write back for VME message - */ -define(`vme_wb', `r12') -define(`vme_wb0', `r12') -define(`vme_wb1', `r13') -define(`vme_wb2', `r14') -define(`vme_wb3', `r15') - -/* - * GRF 16 -- write back for Oword Block Write message with write commit bit - */ -define(`obw_wb', `r16') - -/* - * GRF 18~21 -- Intra Neighbor Edge Pixels - */ -define(`INEP_ROW', `r18') -define(`INEP_COL0', `r20') -define(`INEP_COL1', `r21') - -/* - * temporary registers - */ -define(`tmp_reg0', `r32') -define(`tmp_reg1', `r33') -define(`intra_part_mask_ub', `tmp_reg1.28') -define(`mb_intra_struct_ub', `tmp_reg1.29') -define(`tmp_reg2', `r34') -define(`tmp_x_w', `tmp_reg2.0') -define(`tmp_reg3', `r35') - -/* - * MRF registers - */ -define(`msg_reg0', `m0') /* m0 */ -define(`msg_reg1', `m1') /* m1 */ -define(`msg_reg2', `m2') /* m2 */ -define(`msg_reg3', `m3') /* m3 */ - -/* * __START */ __INTER_START: diff --git a/i965_drv_video/shaders/vme/intra_frame.asm b/i965_drv_video/shaders/vme/intra_frame.asm index fd4fb4e..65cd58b 100644 --- a/i965_drv_video/shaders/vme/intra_frame.asm +++ b/i965_drv_video/shaders/vme/intra_frame.asm @@ -18,98 +18,9 @@ include(`vme_header.inc') /* - * Constant - */ -define(`BLOCK_32X1', `0x0000001F') -define(`BLOCK_4X16', `0x000F0003') - -define(`LUMA_INTRA_16x16_DISABLE', `0x1') -define(`LUMA_INTRA_8x8_DISABLE', `0x2') -define(`LUMA_INTRA_4x4_DISABLE', `0x4') - -define(`INTRA_PRED_AVAIL_FLAG_AE', `0x60') -define(`INTRA_PRED_AVAIL_FLAG_B', `0x10') -define(`INTRA_PRED_AVAIL_FLAG_C', `0x8') -define(`INTRA_PRED_AVAIL_FLAG_D', `0x4') - -define(`BIND_IDX_VME', `0') -define(`BIND_IDX_VME_REF0', `1') -define(`BIND_IDX_VME_REF1', `2') -define(`BIND_IDX_OUTPUT', `3') -define(`BIND_IDX_INEP', `4') - -define(`INTRA_PREDICTORE_MODE', `0x11111111:UD') - -/* GRF registers - * r0 header - * r1~r4 constant buffer (reserved) - * r5 inline data - * r6~r11 reserved - * r12 write back of VME message - * r13 write back of Oword Block Write - */ -/* - * GRF 0 -- header - */ -define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ - -/* - * GRF 1~4 -- Constant Buffer (reserved) - */ - -/* - * GRF 5 -- inline data - */ -define(`inline_reg0', `r5') -define(`w_in_mb_uw', `inline_reg0.2') -define(`orig_xy_ub', `inline_reg0.0') -define(`orig_x_ub', `inline_reg0.0') /* in macroblock */ -define(`orig_y_ub', `inline_reg0.1') - -/* - * GRF 6~11 -- reserved - */ - -/* - * GRF 12 -- write back for VME message - */ -define(`vme_wb', `r12') - -/* - * GRF 13 -- write back for Oword Block Write message with write commit bit - */ -define(`obw_wb', `r13') - -/* - * GRF 14~17 -- Intra Neighbor Edge Pixels - */ -define(`INEP_ROW', `r14') -define(`INEP_COL0', `r16') -define(`INEP_COL1', `r17') - -/* - * temporary registers - */ -define(`tmp_reg0', `r32') -define(`tmp_reg1', `r33') -define(`intra_part_mask_ub', `tmp_reg1.28') -define(`mb_intra_struct_ub', `tmp_reg1.29') -define(`tmp_reg2', `r34') -define(`tmp_x_w', `tmp_reg2.0') -define(`tmp_reg3', `r35') - -/* - * MRF registers - */ -define(`msg_reg0', `m0') /* m0 */ -define(`msg_reg1', `m1') /* m1 */ -define(`msg_reg2', `m2') /* m2 */ -define(`msg_reg3', `m3') /* m3 */ - -/* * __START */ -__START: +__INTRA_START: mov (16) tmp_reg0.0<1>:UD 0x0:UD {align1}; mov (16) tmp_reg2.0<1>:UD 0x0:UD {align1}; @@ -167,7 +78,7 @@ mov (8) msg_reg2<1>:UD INEP_ROW.0<8,8,1>:UD {align1}; mov (8) msg_reg3<1>:UD 0x0 {align1}; mov (16) msg_reg3.0<1>:UB INEP_COL0.3<32,8,4>:UB {align1}; mov (1) msg_reg3.16<1>:UD INTRA_PREDICTORE_MODE {align1}; -send (8) 0 vme_wb null vme(BIND_IDX_VME,0,0,2) mlen 4 rlen 1 {align1}; +send (8) 0 vme_wb null vme(BIND_IDX_VME,0,0,VME_MESSAGE_TYPE_INTRA) mlen 4 rlen 1 {align1}; /* * Oword Block Write message diff --git a/i965_drv_video/shaders/vme/intra_frame.g6b b/i965_drv_video/shaders/vme/intra_frame.g6b index 7e9de72..3973318 100644 --- a/i965_drv_video/shaders/vme/intra_frame.g6b +++ b/i965_drv_video/shaders/vme/intra_frame.g6b @@ -6,13 +6,13 @@ { 0x00000001, 0x240800e1, 0x00000000, 0x0000001f }, { 0x00000001, 0x24140231, 0x00000014, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d0400, 0x00000000 }, - { 0x05800031, 0x21c01cdd, 0x00000000, 0x02188004 }, + { 0x05800031, 0x22401cdd, 0x00000000, 0x02188004 }, { 0x00200041, 0x24002e25, 0x004500a0, 0x00100010 }, { 0x00000040, 0x24003ca5, 0x00000400, 0xfffcfffc }, { 0x00000001, 0x240800e1, 0x00000000, 0x000f0003 }, { 0x00000001, 0x24140231, 0x00000014, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d0400, 0x00000000 }, - { 0x05800031, 0x22001cdd, 0x00000000, 0x02288004 }, + { 0x05800031, 0x22801cdd, 0x00000000, 0x02288004 }, { 0x00200041, 0x24082e29, 0x004500a0, 0x00100010 }, { 0x00000001, 0x24140231, 0x00000014, 0x00000000 }, { 0x00600001, 0x20000022, 0x008d0400, 0x00000000 }, @@ -28,9 +28,9 @@ { 0x02000041, 0x200045a0, 0x00000440, 0x000000a1 }, { 0x00010040, 0x243d1e31, 0x0000043d, 0x00000008 }, { 0x00600001, 0x20200022, 0x008d0420, 0x00000000 }, - { 0x00600001, 0x20400022, 0x008d01c0, 0x00000000 }, + { 0x00600001, 0x20400022, 0x008d0240, 0x00000000 }, { 0x00600001, 0x206000e2, 0x00000000, 0x00000000 }, - { 0x00800001, 0x20600232, 0x00cf0203, 0x00000000 }, + { 0x00800001, 0x20600232, 0x00cf0283, 0x00000000 }, { 0x00000001, 0x20700062, 0x00000000, 0x11111111 }, { 0x08600031, 0x21801cdd, 0x00000000, 0x08184000 }, { 0x00000041, 0x24684521, 0x000000a2, 0x000000a1 }, @@ -41,6 +41,6 @@ { 0x00000001, 0x20240022, 0x00000190, 0x00000000 }, { 0x00000001, 0x20280022, 0x00000194, 0x00000000 }, { 0x00000001, 0x202c0022, 0x00000198, 0x00000000 }, - { 0x05800031, 0x21a01cdd, 0x00000000, 0x041b0003 }, + { 0x05800031, 0x22001cdd, 0x00000000, 0x041b0003 }, { 0x00600001, 0x20000022, 0x008d0000, 0x00000000 }, { 0x07800031, 0x24001cc8, 0x00000000, 0x82000010 }, diff --git a/i965_drv_video/shaders/vme/vme_header.inc b/i965_drv_video/shaders/vme/vme_header.inc index 930028e..60a61e5 100644 --- a/i965_drv_video/shaders/vme/vme_header.inc +++ b/i965_drv_video/shaders/vme/vme_header.inc @@ -11,6 +11,117 @@ // Global symbols define // +/* + * Constant + */ +define(`VME_MESSAGE_TYPE_INTER', `1') +define(`VME_MESSAGE_TYPE_INTRA', `2') +define(`VME_MESSAGE_TYPE_MIXED', `3') + +define(`BLOCK_32X1', `0x0000001F') +define(`BLOCK_4X16', `0x000F0003') + +define(`LUMA_INTRA_16x16_DISABLE', `0x1') +define(`LUMA_INTRA_8x8_DISABLE', `0x2') +define(`LUMA_INTRA_4x4_DISABLE', `0x4') + +define(`INTRA_PRED_AVAIL_FLAG_AE', `0x60') +define(`INTRA_PRED_AVAIL_FLAG_B', `0x10') +define(`INTRA_PRED_AVAIL_FLAG_C', `0x8') +define(`INTRA_PRED_AVAIL_FLAG_D', `0x4') + +define(`BIND_IDX_VME', `0') +define(`BIND_IDX_VME_REF0', `1') +define(`BIND_IDX_VME_REF1', `2') +define(`BIND_IDX_OUTPUT', `3') +define(`BIND_IDX_INEP', `4') + +define(`SUB_PEL_MODE_INTEGER', `0x00000000') +define(`SUB_PEL_MODE_HALF', `0x00001000') +define(`SUB_PEL_MODE_QUARTER', `0x00003000') + +define(`INTER_SAD_NONE', `0x00000000') +define(`INTER_SAD_HAAR', `0x00200000') + +define(`INTRA_SAD_NONE', `0x00000000') +define(`INTRA_SAD_HAAR', `0x00800000') + +define(`REF_REGION_SIZE', `0x2020:UW') + +define(`BI_SUB_MB_PART_MASK', `0x0c000000') +define(`MAX_NUM_MV', `0x00000020') + +define(`INTRA_PREDICTORE_MODE', `0x11111111:UD') + +/* GRF registers + * r0 header + * r1~r4 constant buffer (reserved) + * r5 inline data + * r6~r11 reserved + * r12 write back of VME message + * r13 write back of Oword Block Write + */ +/* + * GRF 0 -- header + */ +define(`thread_id_ub', `r0.20<0,1,0>:UB') /* thread id in payload */ + +/* + * GRF 1~4 -- Constant Buffer (reserved) + */ + +/* + * GRF 5 -- inline data + */ +define(`inline_reg0', `r5') +define(`w_in_mb_uw', `inline_reg0.2') +define(`orig_xy_ub', `inline_reg0.0') +define(`orig_x_ub', `inline_reg0.0') /* in macroblock */ +define(`orig_y_ub', `inline_reg0.1') + +/* + * GRF 6~11 -- reserved + */ + +/* + * GRF 12~15 -- write back for VME message + */ +define(`vme_wb', `r12') +define(`vme_wb0', `r12') +define(`vme_wb1', `r13') +define(`vme_wb2', `r14') +define(`vme_wb3', `r15') + +/* + * GRF 16 -- write back for Oword Block Write message with write commit bit + */ +define(`obw_wb', `r16') + +/* + * GRF 18~21 -- Intra Neighbor Edge Pixels + */ +define(`INEP_ROW', `r18') +define(`INEP_COL0', `r20') +define(`INEP_COL1', `r21') + +/* + * temporary registers + */ +define(`tmp_reg0', `r32') +define(`tmp_reg1', `r33') +define(`intra_part_mask_ub', `tmp_reg1.28') +define(`mb_intra_struct_ub', `tmp_reg1.29') +define(`tmp_reg2', `r34') +define(`tmp_x_w', `tmp_reg2.0') +define(`tmp_reg3', `r35') + +/* + * MRF registers + */ +define(`msg_reg0', `m0') /* m0 */ +define(`msg_reg1', `m1') /* m1 */ +define(`msg_reg2', `m2') /* m2 */ +define(`msg_reg3', `m3') /* m3 */ -- 2.7.4