From ebd46190b9e02270421587885ba05b67d20ce6d8 Mon Sep 17 00:00:00 2001 From: "jino.cho" Date: Tue, 29 Mar 2016 09:33:38 +0900 Subject: [PATCH] usb: s3c-otg: Add Clock control for EXYNOS3250 In EXYNOS3250, reset value of the phy_fsel is 0x7(50MHz). So, We have to clean the bits before setting to 0x5(24MHz). Change-Id: I173ab48dcc8190ecaf959ea253f938946f31ee0b Signed-off-by: jino.cho --- drivers/usb/gadget/regs-otg.h | 1 + drivers/usb/gadget/s3c_udc_otg_phy.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/drivers/usb/gadget/regs-otg.h b/drivers/usb/gadget/regs-otg.h index e6a332a04..ab0e67e68 100644 --- a/drivers/usb/gadget/regs-otg.h +++ b/drivers/usb/gadget/regs-otg.h @@ -233,6 +233,7 @@ struct s3c_usbotg_reg { #define EXYNOS4X12_COMMON_ON_N0 (0x01 << 4) #define EXYNOS4X12_CLK_SEL_12MHZ (0x02 << 0) #define EXYNOS4X12_CLK_SEL_24MHZ (0x05 << 0) +#define EXYNOS4X12_CLK_SEL_MSK (0x07 << 0) /* Device Configuration Register DCFG */ #define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0) diff --git a/drivers/usb/gadget/s3c_udc_otg_phy.c b/drivers/usb/gadget/s3c_udc_otg_phy.c index f13cb8910..c53641e23 100644 --- a/drivers/usb/gadget/s3c_udc_otg_phy.c +++ b/drivers/usb/gadget/s3c_udc_otg_phy.c @@ -63,6 +63,10 @@ void otg_phy_init(struct s3c_udc *dev) writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 | EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */ + else if (s5p_cpu_id == 0x3250) + writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 | + EXYNOS4X12_COMMON_ON_N0 | EXYNOS4X12_CLK_SEL_MSK)) | + EXYNOS4X12_CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */ else writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) | CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */ -- 2.34.1