From c8391ef4f10941e746e415e5a3c70aeaf2860936 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=C5=81ukasz=20Stelmach?= Date: Fri, 20 Oct 2023 14:26:02 +0200 Subject: [PATCH] RISCV: configs: enable FUSE_FS configuration MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Enable CONFIG_FUSE_FS configs and other missed configs. Change-Id: I83c54355c8e7ad2ea95aadcab9bd6adad988d7eb Signed-off-by: Łukasz Stelmach --- arch/riscv/configs/tizen_qemu_defconfig | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/riscv/configs/tizen_qemu_defconfig b/arch/riscv/configs/tizen_qemu_defconfig index 2881287..bfa8edc 100644 --- a/arch/riscv/configs/tizen_qemu_defconfig +++ b/arch/riscv/configs/tizen_qemu_defconfig @@ -50,6 +50,9 @@ CONFIG_SCSI_VIRTIO=y CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=m CONFIG_NETDEVICES=y CONFIG_VIRTIO_NET=y CONFIG_MACB=y @@ -63,6 +66,8 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_HVC_RISCV_SBI=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y @@ -73,8 +78,8 @@ CONFIG_GPIO_SIFIVE=y # CONFIG_PTP_1588_CLOCK is not set CONFIG_POWER_RESET=y CONFIG_DRM=y -CONFIG_DRM_RADEON=y CONFIG_DRM_VIRTIO_GPU=y +CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y @@ -97,9 +102,13 @@ CONFIG_RPMSG_VIRTIO=y CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y +CONFIG_BTRFS_FS=y +CONFIG_BTRFS_FS_POSIX_ACL=y CONFIG_F2FS_FS=y CONFIG_F2FS_FS_SECURITY=y +CONFIG_FANOTIFY=y CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y -- 2.7.4