From ffeca49a8ba9aa39439d30b7bb51f453706b6a0d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 8 Jun 2022 17:40:19 +0200 Subject: [PATCH] arm64: dts: renesas: r8a779f0: Add L3 cache controller Describe the cache configuration for the first Cortex-A55 CPU core on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Tested-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/a63715ce1d2d2fcc7ab987f7a1b40847965e8d6a.1654701480.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 54474ba..a268617 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -23,6 +23,14 @@ reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA55_0>; + }; + + L3_CA55_0: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A779F0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; }; }; -- 2.7.4