From ffa867b535708cec6e8a4c0edc7a205f081518e5 Mon Sep 17 00:00:00 2001 From: Emma Anholt Date: Wed, 22 Mar 2023 14:31:18 -0700 Subject: [PATCH] tgsi: Drop TGSI_OPCODE_DFRACEXP. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit This is no longer emitted by nir_to_tgsi, so let's drop it. This unlocks some more TGSI DCE, since now all instructions have a single dest, but that's a project for another day. Reviewed-by: Alyssa Rosenzweig Reviewed-by: Marek Olšák Part-of: --- docs/gallium/tgsi.rst | 16 +----- src/gallium/auxiliary/tgsi/tgsi_exec.c | 35 ------------- src/gallium/auxiliary/tgsi/tgsi_info.c | 4 -- src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h | 2 +- src/gallium/auxiliary/tgsi/tgsi_util.c | 1 - src/gallium/drivers/r600/r600_shader.c | 68 +------------------------- src/gallium/drivers/svga/svga_tgsi_vgpu10.c | 4 +- src/gallium/include/pipe/p_shader_tokens.h | 1 - 8 files changed, 4 insertions(+), 127 deletions(-) diff --git a/docs/gallium/tgsi.rst b/docs/gallium/tgsi.rst index 986c67b..be7e9df 100644 --- a/docs/gallium/tgsi.rst +++ b/docs/gallium/tgsi.rst @@ -1902,23 +1902,9 @@ two-component vectors with doubled precision in each component. dst.zw = (src.zw > 0) ? 1.0 : (src.zw < 0) ? -1.0 : 0.0 -.. opcode:: DFRACEXP - Convert Number to Fractional and Integral Components - -Like the ``frexp()`` routine in many math libraries, this opcode stores the -exponent of its source to ``dst0``, and the significand to ``dst1``, such that -:math:`dst1 \times 2^{dst0} = src` . The results are replicated across -channels. - -.. math:: - - dst0.xy = dst.zw = frac(src.xy) - - dst1 = frac(src.xy) - - .. opcode:: DLDEXP - Multiply Number by Integral Power of 2 -This opcode is the inverse of :opcode:`DFRACEXP`. The second +This opcode is the inverse of frexp. The second source is an integer. .. math:: diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c b/src/gallium/auxiliary/tgsi/tgsi_exec.c index 8486668..abafc6d 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_exec.c +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c @@ -408,17 +408,6 @@ micro_dldexp(union tgsi_double_channel *dst, } static void -micro_dfracexp(union tgsi_double_channel *dst, - union tgsi_exec_channel *dst_exp, - const union tgsi_double_channel *src) -{ - dst->d[0] = frexp(src->d[0], &dst_exp->i[0]); - dst->d[1] = frexp(src->d[1], &dst_exp->i[1]); - dst->d[2] = frexp(src->d[2], &dst_exp->i[2]); - dst->d[3] = frexp(src->d[3], &dst_exp->i[3]); -} - -static void micro_exp2(union tgsi_exec_channel *dst, const union tgsi_exec_channel *src) { @@ -3568,26 +3557,6 @@ exec_dldexp(struct tgsi_exec_machine *mach, } static void -exec_dfracexp(struct tgsi_exec_machine *mach, - const struct tgsi_full_instruction *inst) -{ - union tgsi_double_channel src; - union tgsi_double_channel dst; - union tgsi_exec_channel dst_exp; - - fetch_double_channel(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_CHAN_Y); - micro_dfracexp(&dst, &dst_exp, &src); - if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) == TGSI_WRITEMASK_XY) - store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_CHAN_Y); - if ((inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_ZW) == TGSI_WRITEMASK_ZW) - store_double_channel(mach, &dst, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_CHAN_W); - for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++) { - if (inst->Dst[1].Register.WriteMask & (1 << chan)) - store_dest(mach, &dst_exp, &inst->Dst[1], inst, chan); - } -} - -static void exec_arg0_64_arg1_32(struct tgsi_exec_machine *mach, const struct tgsi_full_instruction *inst, micro_dop_sop op) @@ -5804,10 +5773,6 @@ exec_instruction( exec_dldexp(mach, inst); break; - case TGSI_OPCODE_DFRACEXP: - exec_dfracexp(mach, inst); - break; - case TGSI_OPCODE_I2D: exec_t_2_64(mach, inst, micro_i2d, TGSI_EXEC_DATA_FLOAT); break; diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c b/src/gallium/auxiliary/tgsi/tgsi_info.c index 477876d..8b926ba 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_info.c +++ b/src/gallium/auxiliary/tgsi/tgsi_info.c @@ -201,7 +201,6 @@ tgsi_opcode_infer_type(enum tgsi_opcode opcode) case TGSI_OPCODE_DSQRT: case TGSI_OPCODE_DMAD: case TGSI_OPCODE_DLDEXP: - case TGSI_OPCODE_DFRACEXP: case TGSI_OPCODE_DFRAC: case TGSI_OPCODE_DRSQ: case TGSI_OPCODE_DTRUNC: @@ -335,8 +334,5 @@ tgsi_opcode_infer_src_type(enum tgsi_opcode opcode, uint src_idx) enum tgsi_opcode_type tgsi_opcode_infer_dst_type(enum tgsi_opcode opcode, uint dst_idx) { - if (dst_idx == 1 && opcode == TGSI_OPCODE_DFRACEXP) - return TGSI_TYPE_SIGNED; - return tgsi_opcode_infer_type(opcode); } diff --git a/src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h b/src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h index 7aecda4..99ee14d 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h +++ b/src/gallium/auxiliary/tgsi/tgsi_info_opcodes.h @@ -212,7 +212,7 @@ OPCODE(1, 1, COMP, DSQRT) OPCODE(1, 3, COMP, DMAD) OPCODE(1, 1, COMP, DFRAC) OPCODE(1, 2, COMP, DLDEXP) -OPCODE(2, 1, REPL, DFRACEXP) +OPCODE_GAP(212) /* removed */ OPCODE(1, 1, COMP, D2I) OPCODE(1, 1, COMP, I2D) OPCODE(1, 1, COMP, D2U) diff --git a/src/gallium/auxiliary/tgsi/tgsi_util.c b/src/gallium/auxiliary/tgsi/tgsi_util.c index a101cce..d879d2e 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_util.c +++ b/src/gallium/auxiliary/tgsi/tgsi_util.c @@ -146,7 +146,6 @@ tgsi_util_get_src_usage_mask(enum tgsi_opcode opcode, case TGSI_OPCODE_DP2: case TGSI_OPCODE_PK2H: case TGSI_OPCODE_PK2US: - case TGSI_OPCODE_DFRACEXP: case TGSI_OPCODE_F2D: case TGSI_OPCODE_I2D: case TGSI_OPCODE_U2D: diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index ceec7c7..11f71c4 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -538,7 +538,7 @@ static int tgsi_is_supported(struct r600_shader_ctx *ctx) struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction; unsigned j; - if (i->Instruction.NumDstRegs > 1 && i->Instruction.Opcode != TGSI_OPCODE_DFRACEXP) { + if (i->Instruction.NumDstRegs > 1) { R600_ERR("too many dst (%d)\n", i->Instruction.NumDstRegs); return -EINVAL; } @@ -4883,70 +4883,6 @@ static int tgsi_dneg(struct r600_shader_ctx *ctx) } -static int tgsi_dfracexp(struct r600_shader_ctx *ctx) -{ - struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; - struct r600_bytecode_alu alu; - unsigned write_mask = inst->Dst[0].Register.WriteMask; - int i, j, r; - - for (i = 0; i <= 3; i++) { - memset(&alu, 0, sizeof(struct r600_bytecode_alu)); - alu.op = ctx->inst_info->op; - - alu.dst.sel = ctx->temp_reg; - alu.dst.chan = i; - alu.dst.write = 1; - for (j = 0; j < inst->Instruction.NumSrcRegs; j++) { - r600_bytecode_src(&alu.src[j], &ctx->src[j], fp64_switch(i)); - } - - if (i == 3) - alu.last = 1; - - r = r600_bytecode_add_alu(ctx->bc, &alu); - if (r) - return r; - } - - /* Replicate significand result across channels. */ - for (i = 0; i <= 3; i++) { - if (!(write_mask & (1 << i))) - continue; - - memset(&alu, 0, sizeof(struct r600_bytecode_alu)); - alu.op = ALU_OP1_MOV; - alu.src[0].chan = (i & 1) + 2; - alu.src[0].sel = ctx->temp_reg; - - tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); - alu.dst.write = 1; - alu.last = 1; - r = r600_bytecode_add_alu(ctx->bc, &alu); - if (r) - return r; - } - - for (i = 0; i <= 3; i++) { - if (inst->Dst[1].Register.WriteMask & (1 << i)) { - /* MOV third channels to writemask dst1 */ - memset(&alu, 0, sizeof(struct r600_bytecode_alu)); - alu.op = ALU_OP1_MOV; - alu.src[0].chan = 1; - alu.src[0].sel = ctx->temp_reg; - - tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst); - alu.last = 1; - r = r600_bytecode_add_alu(ctx->bc, &alu); - if (r) - return r; - break; - } - } - return 0; -} - - static int egcm_int_to_double(struct r600_shader_ctx *ctx) { struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; @@ -12222,7 +12158,6 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64}, [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64}, [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64}, - [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp}, [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int}, [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double}, [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int}, @@ -12449,7 +12384,6 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = [TGSI_OPCODE_DFMA] = { ALU_OP3_FMA_64, tgsi_op3_64}, [TGSI_OPCODE_DFRAC] = { ALU_OP1_FRACT_64, tgsi_op2_64}, [TGSI_OPCODE_DLDEXP] = { ALU_OP2_LDEXP_64, tgsi_op2_64}, - [TGSI_OPCODE_DFRACEXP] = { ALU_OP1_FREXP_64, tgsi_dfracexp}, [TGSI_OPCODE_D2I] = { ALU_OP1_FLT_TO_INT, egcm_double_to_int}, [TGSI_OPCODE_I2D] = { ALU_OP1_INT_TO_FLT, egcm_int_to_double}, [TGSI_OPCODE_D2U] = { ALU_OP1_FLT_TO_UINT, egcm_double_to_int}, diff --git a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c index 7a462cd..05a1ff6 100644 --- a/src/gallium/drivers/svga/svga_tgsi_vgpu10.c +++ b/src/gallium/drivers/svga/svga_tgsi_vgpu10.c @@ -9258,7 +9258,6 @@ opcode_has_dbl_src(unsigned opcode) case TGSI_OPCODE_DSQRT: case TGSI_OPCODE_DMAD: case TGSI_OPCODE_DLDEXP: - case TGSI_OPCODE_DFRACEXP: case TGSI_OPCODE_DRSQ: case TGSI_OPCODE_DTRUNC: case TGSI_OPCODE_DCEIL: @@ -11116,11 +11115,10 @@ emit_instruction(struct svga_shader_emitter_v10 *emit, return emit_dtrunc(emit, inst); /* The following opcodes should never be seen here. We return zero - * for all the PIPE_CAP_TGSI_DROUND_SUPPORTED, DFRACEXP_DLDEXP_SUPPORTED queries. + * for PIPE_CAP_TGSI_DROUND_SUPPORTED. */ case TGSI_OPCODE_LDEXP: case TGSI_OPCODE_DSSG: - case TGSI_OPCODE_DFRACEXP: case TGSI_OPCODE_DLDEXP: case TGSI_OPCODE_DCEIL: case TGSI_OPCODE_DFLR: diff --git a/src/gallium/include/pipe/p_shader_tokens.h b/src/gallium/include/pipe/p_shader_tokens.h index 260916e..170c5e4 100644 --- a/src/gallium/include/pipe/p_shader_tokens.h +++ b/src/gallium/include/pipe/p_shader_tokens.h @@ -568,7 +568,6 @@ enum tgsi_opcode { TGSI_OPCODE_DMAD = 209, TGSI_OPCODE_DFRAC = 210 /* eg, cayman */, TGSI_OPCODE_DLDEXP = 211 /* eg, cayman */, - TGSI_OPCODE_DFRACEXP = 212 /* eg, cayman */, TGSI_OPCODE_D2I = 213, TGSI_OPCODE_I2D = 214, TGSI_OPCODE_D2U = 215, -- 2.7.4