From ff9f02580dcc33bb2d1e313800c4fafd4b5e2654 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 8 Oct 2018 20:02:59 +0000 Subject: [PATCH] [X86] Prefer isTypeLegal over checking isSimple in a DAG combine. Simple types are a superset of what all in tree targets in LLVM could possibly have a legal type. This means the behavior of using isSimple to check for a supported type for X86 could change over time. For example, this could would change if a v256i1 type was added to MVT in the future. llvm-svn: 343995 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 556dcd3..7484181 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -40211,7 +40211,9 @@ static SDValue combineExtractSubvector(SDNode *N, SelectionDAG &DAG, EVT VT = N->getValueType(0); EVT WideVecVT = N->getOperand(0).getValueType(); SDValue WideVec = peekThroughBitcasts(N->getOperand(0)); - if (Subtarget.hasAVX() && !Subtarget.hasAVX2() && WideVecVT.isSimple() && + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); + if (Subtarget.hasAVX() && !Subtarget.hasAVX2() && + TLI.isTypeLegal(WideVecVT) && WideVecVT.getSizeInBits() == 256 && WideVec.getOpcode() == ISD::AND) { auto isConcatenatedNot = [] (SDValue V) { V = peekThroughBitcasts(V); -- 2.7.4