From ff0fb6936b43d575ca23cf769bf24d9a963e6f19 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Thu, 4 Jun 2015 22:05:51 +0000 Subject: [PATCH] [SDAG switch lowering] Fix switch case -> or merging for 0 and INT_MIN The big/small ordering here is based on signed values so SmallValue will be INT_MIN and BigValue 0. This shouldn't be a problem but the code assumed that BigValue always had more bits set than SmallValue. We used to just miss the transformation, but a recent refactoring of mine turned this into an assertion failure. llvm-svn: 239105 --- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 14 +++++--------- llvm/test/CodeGen/X86/switch-or.ll | 21 ++++++++++++++++++++- 2 files changed, 25 insertions(+), 10 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index cf0900f..8ba957d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -7807,21 +7807,17 @@ void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond, const APInt &BigValue = Big.Low->getValue(); // Check that there is only one bit different. - if ((BigValue ^ SmallValue).isPowerOf2()) { - // Isolate the common bit. - APInt CommonBit = BigValue & ~SmallValue; - assert((SmallValue | CommonBit) == BigValue && - CommonBit.countPopulation() == 1 && "Not a common bit?"); - + APInt CommonBit = BigValue ^ SmallValue; + if (CommonBit.isPowerOf2()) { SDValue CondLHS = getValue(Cond); EVT VT = CondLHS.getValueType(); SDLoc DL = getCurSDLoc(); SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, DAG.getConstant(CommonBit, DL, VT)); - SDValue Cond = DAG.getSetCC(DL, MVT::i1, Or, - DAG.getConstant(BigValue, DL, VT), - ISD::SETEQ); + SDValue Cond = DAG.getSetCC( + DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT), + ISD::SETEQ); // Update successor info. // Both Small and Big will jump to Small.BB, so we sum up the weights. diff --git a/llvm/test/CodeGen/X86/switch-or.ll b/llvm/test/CodeGen/X86/switch-or.ll index 6e6b013..4642acc 100644 --- a/llvm/test/CodeGen/X86/switch-or.ll +++ b/llvm/test/CodeGen/X86/switch-or.ll @@ -1,10 +1,11 @@ ; RUN: llc -march=x86 -asm-verbose=false < %s | FileCheck %s ; Check that merging switch cases that differ in one bit works. +; CHECK-LABEL: test1 ; CHECK: orl $2 ; CHECK-NEXT: cmpl $6 -define void @foo(i32 %variable) nounwind { +define void @test1(i32 %variable) nounwind { entry: switch i32 %variable, label %if.end [ i32 4, label %if.then @@ -19,4 +20,22 @@ if.end: ret void } +; CHECK-LABEL: test2 +; CHECK: orl $-2147483648 +; CHECK-NEXT: cmpl $-2147483648 +define void @test2(i32 %variable) nounwind { +entry: + switch i32 %variable, label %if.end [ + i32 0, label %if.then + i32 -2147483648, label %if.then + ] + +if.then: + %call = tail call i32 (...) @bar() nounwind + ret void + +if.end: + ret void +} + declare i32 @bar(...) nounwind -- 2.7.4