From fedf90c774d63c0423858f2948cb63d2dcd9de3a Mon Sep 17 00:00:00 2001
From: Carol Eidt <carol.eidt@microsoft.com>
Date: Tue, 6 Sep 2016 12:39:29 -0700
Subject: [PATCH] Fix Arm64 build breaks

The `GT_STORE_OBJ` case in codegen was missing a break.
`getStructHandleIfPresent` wasn't correctly handling `GT_ASG'.
The `srcCount` was not being set correctly for block ops with a constant size.
And I lost some code in `fgMakeTmpArgNode` with a merge.
Also, I had introduced a dumping issue in gentree.cpp when I made `GT_OBJ` a `GTK_UNOP` as a result of some PR comments.
---
 src/jit/codegenarm64.cpp |  1 +
 src/jit/gentree.cpp      |  6 +++++-
 src/jit/lowerarm64.cpp   | 16 ++++++++++------
 src/jit/morph.cpp        |  7 ++++++-
 4 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/src/jit/codegenarm64.cpp b/src/jit/codegenarm64.cpp
index edd8693..ca0df53 100644
--- a/src/jit/codegenarm64.cpp
+++ b/src/jit/codegenarm64.cpp
@@ -3523,6 +3523,7 @@ void CodeGen::genCodeForTreeNode(GenTreePtr treeNode)
             {
                 assert(treeNode->AsObj()->gtGcPtrCount != 0);
                 genCodeForCpObj(treeNode->AsObj());
+                break;
             }
             __fallthrough;
 
diff --git a/src/jit/gentree.cpp b/src/jit/gentree.cpp
index 548c874..9490e04 100644
--- a/src/jit/gentree.cpp
+++ b/src/jit/gentree.cpp
@@ -2535,6 +2535,10 @@ AGAIN:
                                                     reinterpret_cast<uintptr_t>(tree->gtAllocObj.gtAllocObjClsHnd)));
                     hash = genTreeHashAdd(hash, tree->gtAllocObj.gtNewHelper);
                     break;
+                case GT_OBJ:
+                    hash = genTreeHashAdd(hash, static_cast<unsigned>(
+                                                    reinterpret_cast<uintptr_t>(tree->gtObj.gtClass)));
+                    break;
 
                 // For the ones below no extra argument matters for comparison.
                 case GT_BOX:
@@ -15829,7 +15833,7 @@ CORINFO_CLASS_HANDLE Compiler::gtGetStructHandleIfPresent(GenTree* tree)
                 info.compCompHnd->getFieldType(tree->gtField.gtFldHnd, &structHnd);
                 break;
             case GT_ASG:
-                structHnd = gtGetStructHandle(tree->gtGetOp1());
+                structHnd = gtGetStructHandleIfPresent(tree->gtGetOp1());
                 break;
             case GT_LCL_VAR:
             case GT_LCL_FLD:
diff --git a/src/jit/lowerarm64.cpp b/src/jit/lowerarm64.cpp
index e2f5b8d..709639d 100644
--- a/src/jit/lowerarm64.cpp
+++ b/src/jit/lowerarm64.cpp
@@ -1223,8 +1223,9 @@ void Lowering::TreeNodeInfoInitBlockStore(GenTreeBlk* blkNode)
     LinearScan* l        = m_lsra;
     Compiler*   compiler = comp;
 
-    // Sources are dest address, initVal or source, and size
-    blkNode->gtLsraInfo.srcCount = 3;
+    // Sources are dest address and initVal or source.
+    // We may require an additional source or temp register for the size.
+    blkNode->gtLsraInfo.srcCount = 2;
     blkNode->gtLsraInfo.dstCount = 0;
 
     if ((blkNode->OperGet() == GT_STORE_OBJ) && (blkNode->AsObj()->gtGcPtrCount == 0))
@@ -1304,8 +1305,6 @@ void Lowering::TreeNodeInfoInitBlockStore(GenTreeBlk* blkNode)
     {
         // CopyObj or CopyBlk
         // Sources are src and dest and size if not constant.
-        blkNode->gtLsraInfo.srcCount = 3;
-        blkNode->gtLsraInfo.dstCount = 0;
         unsigned   size              = blkNode->gtBlkSize;
         GenTreePtr source            = blkNode->Data();
         GenTree*   srcAddr           = nullptr;
@@ -1499,7 +1498,7 @@ void Lowering::TreeNodeInfoInitSIMD(GenTree* tree)
 
         case SIMDIntrinsicInitN:
             info->srcCount = (int)(simdTree->gtSIMDSize / genTypeSize(simdTree->gtSIMDBaseType));
-            // Need an internal register to stitch together all the values into a single vector in an XMM reg
+            // Need an internal register to stitch together all the values into a single vector in an XMM reg.
             info->internalFloatCount = 1;
             info->setInternalCandidates(lsra, lsra->allSIMDRegs());
             break;
@@ -1719,7 +1718,12 @@ void Lowering::LowerGCWriteBarrier(GenTree* tree)
 void Lowering::SetIndirAddrOpCounts(GenTreePtr indirTree)
 {
     assert(indirTree->OperIsIndir());
-    assert(indirTree->TypeGet() != TYP_STRUCT);
+    // If this is the rhs of a block copy (i.e. non-enregisterable struct),
+    // it has no register requirements.
+    if (indirTree->TypeGet() == TYP_STRUCT)
+    {
+        return;
+    }
 
     GenTreePtr    addr = indirTree->gtGetOp1();
     TreeNodeInfo* info = &(indirTree->gtLsraInfo);
diff --git a/src/jit/morph.cpp b/src/jit/morph.cpp
index 18380a0..00df17b 100644
--- a/src/jit/morph.cpp
+++ b/src/jit/morph.cpp
@@ -2045,8 +2045,13 @@ GenTreePtr Compiler::fgMakeTmpArgNode(
             {
                 // ToDo-ARM64: Consider using:  arg->ChangeOper(GT_LCL_FLD);
                 // as that is how FEATURE_UNIX_AMD64_STRUCT_PASSING works.
+                // We will create a GT_OBJ for the argument below.
+                // This will be passed by value in two registers.
+                assert(addrNode != nullptr);
+
+                // Create an Obj of the temp to use it as a call argument.
+                arg = gtNewObjNode(lvaGetStruct(tmpVarNum), arg);
 
-                // Pass by value in two registers, using a regular GT_OBJ node, created below.
                 // TODO-1stClassStructs: We should not need to set the GTF_DONT_CSE flag here;
                 // this is only to preserve former behavior (though some CSE'ing of struct
                 // values can be pessimizing, so enabling this may require some additional tuning).
-- 
2.7.4